ctlreg.h revision 1.35
1 /* $NetBSD: ctlreg.h,v 1.35 2004/07/01 14:57:46 heas Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _SPARC_CTLREG_H_ 27 #define _SPARC_CTLREG_H_ 28 29 /* 30 * Sun 4u control registers. (includes address space definitions 31 * and some registers in control space). 32 */ 33 34 /* 35 * The Alternate address spaces. 36 * 37 * 0x00-0x7f are privileged 38 * 0x80-0xff can be used by users 39 */ 40 41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 42 43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 45 46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 48 49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 51 52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */ 54 55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 57 58 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 59 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 60 61 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 62 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 63 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 64 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 65 66 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 67 68 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 69 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 70 71 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 72 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 73 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 74 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 75 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 76 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 77 78 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 79 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 80 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 81 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 82 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 83 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 84 85 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 86 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 87 88 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 89 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 90 91 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 92 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 93 94 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 95 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 96 97 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 98 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 99 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 100 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 101 102 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 103 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 104 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 105 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 106 107 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 108 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 109 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 110 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 111 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 112 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 113 114 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 115 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 116 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 117 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 118 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 119 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 120 121 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 122 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 123 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 124 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 125 126 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 127 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 128 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 129 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 130 131 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 132 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 133 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 134 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 135 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 136 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 137 138 139 /* 140 * These are the shorter names used by Solaris 141 */ 142 143 #define ASI_N ASI_NUCLEUS 144 #define ASI_NL ASI_NUCLEUS_LITTLE 145 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 146 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 147 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 148 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 149 #define ASI_P ASI_PRIMARY 150 #define ASI_S ASI_SECONDARY 151 #define ASI_PNF ASI_PRIMARY_NOFAULT 152 #define ASI_SNF ASI_SECONDARY_NOFAULT 153 #define ASI_PL ASI_PRIMARY_LITTLE 154 #define ASI_SL ASI_SECONDARY_LITTLE 155 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 156 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 157 #define ASI_FL8_P ASI_FL8_PRIMARY 158 #define ASI_FL8_S ASI_FL8_SECONDARY 159 #define ASI_FL16_P ASI_FL16_PRIMARY 160 #define ASI_FL16_S ASI_FL16_SECONDARY 161 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 162 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 163 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 164 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 165 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 166 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 167 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 168 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 169 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 170 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 171 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 172 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 173 #define ASI_BLK_P ASI_BLOCK_PRIMARY 174 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 175 #define ASI_BLK_S ASI_BLOCK_SECONDARY 176 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 177 178 /* Alternative spellings */ 179 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 180 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 181 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 182 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 183 184 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 185 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 186 187 /* 188 * The following are 4u control registers 189 */ 190 191 /* Get the CPU's UPAID */ 192 #define UPA_CR_MID(x) (((x)>>17)&0x1f) 193 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 194 195 /* 196 * [4u] MMU and Cache Control Register (MCCR) 197 * use ASI = 0x45 198 */ 199 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 200 #define MCCR 0x00 201 202 /* MCCR Bits and their meanings */ 203 #define MCCR_DMMU_EN 0x08 204 #define MCCR_IMMU_EN 0x04 205 #define MCCR_DCACHE_EN 0x02 206 #define MCCR_ICACHE_EN 0x01 207 208 209 /* 210 * MMU control registers 211 */ 212 213 /* Choose an MMU */ 214 #define ASI_DMMU 0x58 215 #define ASI_IMMU 0x50 216 217 /* Other assorted MMU ASIs */ 218 #define ASI_IMMU_8KPTR 0x51 219 #define ASI_IMMU_64KPTR 0x52 220 #define ASI_IMMU_DATA_IN 0x54 221 #define ASI_IMMU_TLB_DATA 0x55 222 #define ASI_IMMU_TLB_TAG 0x56 223 #define ASI_DMMU_8KPTR 0x59 224 #define ASI_DMMU_64KPTR 0x5a 225 #define ASI_DMMU_DATA_IN 0x5c 226 #define ASI_DMMU_TLB_DATA 0x5d 227 #define ASI_DMMU_TLB_TAG 0x5e 228 229 /* 230 * The following are the control registers 231 * They work on both MMUs unless noted. 232 * 233 * Register contents are defined later on individual registers. 234 */ 235 #define TSB_TAG_TARGET 0x0 236 #define TLB_DATA_IN 0x0 237 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 238 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 239 #define SFSR 0x18 240 #define SFAR 0x20 /* fault address -- DMMU only */ 241 #define TSB 0x28 242 #define TLB_TAG_ACCESS 0x30 243 #define VIRTUAL_WATCHPOINT 0x38 244 #define PHYSICAL_WATCHPOINT 0x40 245 246 /* Tag Target bits */ 247 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 248 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 249 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 250 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 251 252 /* SFSR bits for both D_SFSR and I_SFSR */ 253 #define SFSR_ASI(x) ((x)>>16) 254 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 255 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 256 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 257 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 258 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 259 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 260 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 261 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 262 #define SFSR_CTXT(x) (((x)>>4)&0x3) 263 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 264 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 265 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 266 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 267 #define SFSR_W 0x00004 /* DMMU: attempted write */ 268 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 269 #define SFSR_FV 0x00001 /* Fault is valid */ 270 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \ 271 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 272 273 #define SFSR_BITS "\177\20" \ 274 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \ 275 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \ 276 "b\3W\0" "b\2OW\0" "b\1FV\0" 277 278 /* ASFR bits */ 279 #define ASFR_ME 0x100000000LL 280 #define ASFR_PRIV 0x080000000LL 281 #define ASFR_ISAP 0x040000000LL 282 #define ASFR_ETP 0x020000000LL 283 #define ASFR_IVUE 0x010000000LL 284 #define ASFR_TO 0x008000000LL 285 #define ASFR_BERR 0x004000000LL 286 #define ASFR_LDP 0x002000000LL 287 #define ASFR_CP 0x001000000LL 288 #define ASFR_WP 0x000800000LL 289 #define ASFR_EDP 0x000400000LL 290 #define ASFR_UE 0x000200000LL 291 #define ASFR_CE 0x000100000LL 292 #define ASFR_ETS 0x0000f0000LL 293 #define ASFT_P_SYND 0x00000ffffLL 294 295 #define AFSR_BITS "\177\20" \ 296 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 297 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 298 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 299 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 300 301 /* 302 * Here's the spitfire TSB control register bits. 303 * 304 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 305 */ 306 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 307 #define TSB_SIZE_1K 0x01 308 #define TSB_SIZE_2K 0x02 309 #define TSB_SIZE_4K 0x03 310 #define TSB_SIZE_8K 0x04 311 #define TSB_SIZE_16K 0x05 312 #define TSB_SIZE_32K 0x06 313 #define TSB_SIZE_64K 0x07 314 #define TSB_SPLIT 0x1000 315 #define TSB_BASE 0xffffffffffffe000 316 317 /* TLB Tag Access bits */ 318 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 319 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 320 321 /* 322 * TLB demap registers. TTEs are defined in v9pte.h 323 * 324 * Use the address space to select between IMMU and DMMU. 325 * The address of the register selects which context register 326 * to read the ASI from. 327 * 328 * The data stored in the register is interpreted as the VA to 329 * use. The DEMAP_CTX_<> registers ignore the address and demap the 330 * entire ASI. 331 * 332 */ 333 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 334 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 335 336 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 337 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 338 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 339 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 340 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 341 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 342 343 /* 344 * Interrupt registers. This really gets hairy. 345 */ 346 347 /* IRSR -- Interrupt Receive Status Ragister */ 348 #define ASI_IRSR 0x49 349 #define IRSR 0x00 350 #define IRSR_BUSY 0x020 351 #define IRSR_MID(x) (x&0x1f) 352 353 /* IRDR -- Interrupt Receive Data Registers */ 354 #define ASI_IRDR 0x7f 355 #define IRDR_0H 0x40 356 #define IRDR_0L 0x48 /* unimplemented */ 357 #define IRDR_1H 0x50 358 #define IRDR_1L 0x58 /* unimplemented */ 359 #define IRDR_2H 0x60 360 #define IRDR_2L 0x68 /* unimplemented */ 361 #define IRDR_3H 0x70 /* unimplemented */ 362 #define IRDR_3L 0x78 /* unimplemented */ 363 364 /* SOFTINT ASRs */ 365 #define SET_SOFTINT %asr20 /* Sets these bits */ 366 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 367 #define SOFTINT %asr22 /* Reads the register */ 368 #define TICK_CMPR %asr23 369 370 #define TICK_INT 0x01 /* level-14 clock tick */ 371 #define SOFTINT1 (0x1<<1) 372 #define SOFTINT2 (0x1<<2) 373 #define SOFTINT3 (0x1<<3) 374 #define SOFTINT4 (0x1<<4) 375 #define SOFTINT5 (0x1<<5) 376 #define SOFTINT6 (0x1<<6) 377 #define SOFTINT7 (0x1<<7) 378 #define SOFTINT8 (0x1<<8) 379 #define SOFTINT9 (0x1<<9) 380 #define SOFTINT10 (0x1<<10) 381 #define SOFTINT11 (0x1<<11) 382 #define SOFTINT12 (0x1<<12) 383 #define SOFTINT13 (0x1<<13) 384 #define SOFTINT14 (0x1<<14) 385 #define SOFTINT15 (0x1<<15) 386 387 /* Interrupt Dispatch -- usually reserved for cross-calls */ 388 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 389 #define IDSR 0x00 390 #define IDSR_NACK 0x02 391 #define IDSR_BUSY 0x01 392 393 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 394 395 /* Interrupt delivery initiation */ 396 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 397 398 #define IDDR_0H 0x40 /* Store data to send in these regs */ 399 #define IDDR_0L 0x48 /* unimplemented */ 400 #define IDDR_1H 0x50 401 #define IDDR_1L 0x58 /* unimplemented */ 402 #define IDDR_2H 0x60 403 #define IDDR_2L 0x68 /* unimplemented */ 404 #define IDDR_3H 0x70 /* unimplemented */ 405 #define IDDR_3L 0x78 /* unimplemented */ 406 407 /* 408 * Error registers 409 */ 410 411 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 412 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 413 #define AFAR 0x00 414 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 415 #define AFSR 0x00 416 417 #define ASI_P_EER 0x4b /* Error enable register */ 418 #define P_EER 0x00 419 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 420 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 421 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 422 423 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 424 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 425 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 426 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 427 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 428 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 429 430 431 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 432 433 #ifndef _LOCORE 434 /* 435 * GCC __asm constructs for doing assembly stuff. 436 */ 437 438 /* 439 * ``Routines'' to load and store from/to alternate address space. 440 * The location can be a variable, the asi value (address space indicator) 441 * must be a constant. 442 * 443 * N.B.: You can put as many special functions here as you like, since 444 * they cost no kernel space or time if they are not used. 445 * 446 * These were static inline functions, but gcc screws up the constraints 447 * on the address space identifiers (the "n"umeric value part) because 448 * it inlines too late, so we have to use the funny valued-macro syntax. 449 */ 450 451 /* 452 * Apparently the definition of bypass ASIs is that they all use the 453 * D$ so we need to flush the D$ to make sure we don't get data pollution. 454 */ 455 456 #ifdef __arch64__ 457 static __inline__ u_char 458 lduba(paddr_t loc, int asi) 459 { 460 register unsigned int _lduba_v; 461 462 __asm __volatile( 463 "wr %2,%%g0,%%asi; " 464 "lduba [%1]%%asi,%0; " 465 "wr %%g0, 0x82, %%asi" 466 : "=r" (_lduba_v) 467 : "r" ((unsigned long)(loc)), "r" (asi)); 468 return (_lduba_v); 469 } 470 #else 471 static __inline__ u_char 472 lduba(paddr_t loc, int asi) 473 { 474 register unsigned int _lduba_v, _loc_hi, _pstate; 475 476 _loc_hi = (((u_int64_t)loc)>>32); 477 if (PHYS_ASI(asi)) { 478 __asm __volatile( 479 "wr %4,%%g0,%%asi; " 480 "sllx %3,32,%0; " 481 "rdpr %%pstate,%1; " 482 "or %0,%2,%0; " 483 "wrpr %1,8,%%pstate; " 484 "membar #Sync; " 485 "lduba [%0]%%asi,%0; " 486 "wrpr %1,0,%%pstate; " 487 "membar #Sync; " 488 "wr %%g0, 0x82, %%asi " 489 : "=&r" (_lduba_v), "=&r" (_pstate) 490 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 491 } else { 492 __asm __volatile( 493 "wr %3,%%g0,%%asi; " 494 "sllx %2,32,%0; " 495 "or %0,%1,%0; " 496 "lduba [%0]%%asi,%0; " 497 "wr %%g0, 0x82, %%asi " 498 : "=&r" (_lduba_v) 499 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 500 } 501 return (_lduba_v); 502 } 503 #endif 504 505 #ifdef __arch64__ 506 /* load half-word from alternate address space */ 507 static __inline__ u_short 508 lduha(paddr_t loc, int asi) 509 { 510 register unsigned int _lduha_v; 511 512 __asm __volatile( 513 "wr %2,%%g0,%%asi; " 514 "lduha [%1]%%asi,%0; " 515 "wr %%g0, 0x82, %%asi " 516 : "=r" (_lduha_v) 517 : "r" ((unsigned long)(loc)), "r" (asi)); 518 return (_lduha_v); 519 } 520 #else 521 /* load half-word from alternate address space */ 522 static __inline__ u_short 523 lduha(paddr_t loc, int asi) { 524 register unsigned int _lduha_v, _loc_hi, _pstate; 525 526 _loc_hi = (((u_int64_t)loc)>>32); 527 528 if (PHYS_ASI(asi)) { 529 __asm __volatile( 530 "wr %4,%%g0,%%asi; " 531 "sllx %3,32,%0; " 532 "rdpr %%pstate,%1; " 533 "wrpr %1,8,%%pstate; " 534 "or %0,%2,%0; " 535 "membar #Sync; " 536 "lduha [%0]%%asi,%0; " 537 "wrpr %1,0,%%pstate; " 538 "membar #Sync; " 539 "wr %%g0, 0x82, %%asi " 540 : "=&r" (_lduha_v), "=&r" (_pstate) 541 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 542 } else { 543 __asm __volatile( 544 "wr %3,%%g0,%%asi; " 545 "sllx %2,32,%0; " 546 "or %0,%1,%0; " 547 "lduha [%0]%%asi,%0; " 548 "wr %%g0, 0x82, %%asi " 549 : "=&r" (_lduha_v) 550 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 551 } 552 return (_lduha_v); 553 } 554 #endif 555 556 557 #ifdef __arch64__ 558 /* load unsigned int from alternate address space */ 559 static __inline__ u_int 560 lda(paddr_t loc, int asi) 561 { 562 register unsigned int _lda_v; 563 564 __asm __volatile( 565 "wr %2,%%g0,%%asi; " 566 "lda [%1]%%asi,%0 " 567 : "=r" (_lda_v) 568 : "r" ((unsigned long)(loc)), "r" (asi)); 569 return (_lda_v); 570 } 571 572 /* load signed int from alternate address space */ 573 static __inline__ int 574 ldswa(paddr_t loc, int asi) 575 { 576 register int _lda_v; 577 578 __asm __volatile( 579 "wr %2,%%g0,%%asi; " 580 "ldswa [%1]%%asi,%0; " 581 "wr %%g0, 0x82, %%asi " 582 : "=r" (_lda_v) 583 : "r" ((unsigned long)(loc)), "r" (asi)); 584 return (_lda_v); 585 } 586 #else /* __arch64__ */ 587 /* load unsigned int from alternate address space */ 588 static __inline__ u_int 589 lda(paddr_t loc, int asi) 590 { 591 register unsigned int _lda_v, _loc_hi, _pstate; 592 593 _loc_hi = (((u_int64_t)loc)>>32); 594 if (PHYS_ASI(asi)) { 595 __asm __volatile( 596 "wr %4,%%g0,%%asi; " 597 "rdpr %%pstate,%1; " 598 "sllx %3,32,%0; " 599 "wrpr %1,8,%%pstate; " 600 "or %0,%2,%0; " 601 "membar #Sync; " 602 "lda [%0]%%asi,%0; " 603 "wrpr %1,0,%%pstate; " 604 "membar #Sync; " 605 "wr %%g0, 0x82, %%asi " 606 : "=&r" (_lda_v), "=&r" (_pstate) 607 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 608 } else { 609 __asm __volatile( 610 "wr %3,%%g0,%%asi; " 611 "sllx %2,32,%0; " 612 "or %0,%1,%0; " 613 "lda [%0]%%asi,%0; " 614 "wr %%g0, 0x82, %%asi " 615 : "=&r" (_lda_v) 616 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 617 } 618 return (_lda_v); 619 } 620 621 /* load signed int from alternate address space */ 622 static __inline__ int 623 ldswa(paddr_t loc, int asi) 624 { 625 register int _lda_v, _loc_hi, _pstate; 626 627 _loc_hi = (((u_int64_t)loc)>>32); 628 if (PHYS_ASI(asi)) { 629 __asm __volatile( 630 "wr %4,%%g0,%%asi; " 631 "rdpr %%pstate,%1; " 632 "wrpr %1,8,%%pstate; " 633 "sllx %3,32,%0; " 634 " or %0,%2,%0; " 635 "membar #Sync; " 636 "ldswa [%0]%%asi,%0; " 637 "wrpr %1,0,%%pstate; " 638 "membar #Sync; " 639 "wr %%g0, 0x82, %%asi " 640 : "=&r" (_lda_v), "=&r" (_pstate) 641 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 642 } else { 643 __asm __volatile( 644 "wr %3,%%g0,%%asi; " 645 "sllx %2,32,%0; " 646 "or %0,%1,%0; " 647 "ldswa [%0]%%asi,%0; " 648 "wr %%g0, 0x82, %%asi " 649 : "=&r" (_lda_v) 650 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 651 } 652 return (_lda_v); 653 } 654 #endif /* __arch64__ */ 655 656 #ifdef __arch64__ 657 /* load 64-bit int from alternate address space -- these should never be used */ 658 static __inline__ u_int64_t 659 ldda(paddr_t loc, int asi) 660 { 661 register long long _lda_v; 662 663 __asm __volatile( 664 "wr %2,%%g0,%%asi; " 665 "ldda [%1]%%asi,%0; " 666 "wr %%g0, 0x82, %%asi " 667 : "=r" (_lda_v) 668 : "r" ((unsigned long)(loc)), "r" (asi)); 669 return (_lda_v); 670 } 671 #else 672 /* load 64-bit int from alternate address space */ 673 static __inline__ u_int64_t 674 ldda(paddr_t loc, int asi) 675 { 676 register long long _lda_v, _loc_hi, _pstate; 677 678 _loc_hi = (((u_int64_t)loc)>>32); 679 if (PHYS_ASI(asi)) { 680 __asm __volatile( 681 "wr %4,%%g0,%%asi; " 682 "rdpr %%pstate,%1; " 683 "wrpr %1,8,%%pstate; " 684 "sllx %3,32,%0; " 685 "or %0,%2,%0; " 686 "membar #Sync; " 687 "ldda [%0]%%asi,%0; " 688 "wrpr %1,0,%%pstate; " 689 "membar #Sync; " 690 "wr %%g0, 0x82, %%asi " 691 : "=&r" (_lda_v), "=&r" (_pstate) 692 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 693 } else { 694 __asm __volatile( 695 "wr %3,%%g0,%%asi; " 696 "sllx %2,32,%0; " 697 " or %0,%1,%0; " 698 "ldda [%0]%%asi,%0; " 699 "wr %%g0, 0x82, %%asi " 700 : "=&r" (_lda_v) 701 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 702 } 703 return (_lda_v); 704 } 705 #endif 706 707 708 #ifdef __arch64__ 709 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 710 static __inline__ u_int64_t 711 ldxa(paddr_t loc, int asi) 712 { 713 register unsigned long _lda_v; 714 715 __asm __volatile( 716 "wr %2,%%g0,%%asi; " 717 "ldxa [%1]%%asi,%0; " 718 "wr %%g0, 0x82, %%asi " 719 : "=r" (_lda_v) 720 : "r" ((unsigned long)(loc)), "r" (asi)); 721 return (_lda_v); 722 } 723 #else 724 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 725 static __inline__ u_int64_t 726 ldxa(paddr_t loc, int asi) 727 { 728 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; 729 730 _loc_hi = (((u_int64_t)loc)>>32); 731 if (PHYS_ASI(asi)) { 732 __asm __volatile( 733 "wr %4,%%g0,%%asi; " 734 "rdpr %%pstate,%1; " 735 "sllx %3,32,%0; " 736 "wrpr %1,8,%%pstate; " 737 "or %0, %2, %0; " 738 "membar #Sync; " 739 "ldxa [%0]%%asi,%0; " 740 "wrpr %1,0,%%pstate; " 741 "membar #Sync; " 742 "srlx %0, 32, %1; " 743 "srl %0, 0, %0; " 744 "wr %%g0, 0x82, %%asi " 745 : "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) 746 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 747 } else { 748 __asm __volatile( 749 "wr %4,%%g0,%%asi; " 750 "sllx %3,32,%0; " 751 "or %0,%2,%0; " 752 "ldxa [%0]%%asi,%0; " 753 "srlx %0,32,%1; " 754 "srl %0, 0, %0; " 755 "wr %%g0, 0x82, %%asi " 756 : "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) 757 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 758 } 759 return ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); 760 } 761 #endif 762 763 /* store byte to alternate address space */ 764 #ifdef __arch64__ 765 static __inline__ void 766 stba(paddr_t loc, int asi, u_char value) 767 { 768 __asm __volatile( 769 "wr %2, %%g0, %%asi; " 770 "stba %0, [%1]%%asi; " 771 "wr %%g0, 0x82, %%asi " 772 : : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); 773 } 774 #else 775 static __inline__ void 776 stba(paddr_t loc, int asi, u_char value) 777 { 778 register int _loc_hi, _pstate; 779 780 _loc_hi = (((u_int64_t)loc)>>32); 781 if (PHYS_ASI(asi)) { 782 __asm __volatile( 783 "wr %5,%%g0,%%asi; " 784 "sllx %4,32,%0; " 785 "rdpr %%pstate,%1; " 786 "or %3,%0,%0; " 787 "wrpr %1,8,%%pstate; " 788 "stba %2,[%0]%%asi; " 789 "wrpr %1,0,%%pstate; " 790 "membar #Sync; " 791 "wr %%g0, 0x82, %%asi " 792 : "=&r" (_loc_hi), "=&r" (_pstate) 793 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 794 } else { 795 __asm __volatile( 796 "wr %4,%%g0,%%asi; " 797 "sllx %3,32,%0; " 798 "or %2,%0,%0; " 799 "stba %1,[%0]%%asi; " 800 "wr %%g0, 0x82, %%asi " 801 : "=&r" (_loc_hi) 802 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 803 } 804 } 805 #endif 806 807 /* store half-word to alternate address space */ 808 #ifdef __arch64__ 809 static __inline__ void 810 stha(paddr_t loc, int asi, u_short value) 811 { 812 __asm __volatile( 813 "wr %2,%%g0,%%asi; " 814 "stha %0,[%1]%%asi; " 815 "wr %%g0, 0x82, %%asi " 816 : : "r" ((int)(value)), "r" ((unsigned long)(loc)), 817 "r" (asi) : "memory"); 818 } 819 #else 820 static __inline__ void 821 stha(paddr_t loc, int asi, u_short value) 822 { 823 register int _loc_hi, _pstate; 824 825 _loc_hi = (((u_int64_t)loc)>>32); 826 if (PHYS_ASI(asi)) { 827 __asm __volatile( 828 "wr %5,%%g0,%%asi; " 829 "sllx %4,32,%0; " 830 "rdpr %%pstate,%1; " 831 "or %3,%0,%0; " 832 "wrpr %1,8,%%pstate; " 833 "stha %2,[%0]%%asi; " 834 "wrpr %1,0,%%pstate; " 835 "membar #Sync; " 836 "wr %%g0, 0x82, %%asi " 837 : "=&r" (_loc_hi), "=&r" (_pstate) 838 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 839 : "memory"); 840 } else { 841 __asm __volatile( 842 "wr %4,%%g0,%%asi; " 843 "sllx %3,32,%0; " 844 "or %2,%0,%0; " 845 "stha %1,[%0]%%asi; " 846 "wr %%g0, 0x82, %%asi " 847 : "=&r" (_loc_hi) 848 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 849 : "memory"); 850 } 851 } 852 #endif 853 854 855 /* store int to alternate address space */ 856 #ifdef __arch64__ 857 static __inline__ void 858 sta(paddr_t loc, int asi, u_int value) 859 { 860 __asm __volatile( 861 "wr %2,%%g0,%%asi; " 862 "sta %0,[%1]%%asi; " 863 "wr %%g0, 0x82, %%asi " 864 : : "r" ((int)(value)), "r" ((unsigned long)(loc)), 865 "r" (asi) : "memory"); 866 } 867 #else 868 static __inline__ void 869 sta(paddr_t loc, int asi, u_int value) 870 { 871 register int _loc_hi, _pstate; 872 873 _loc_hi = (((u_int64_t)loc)>>32); 874 if (PHYS_ASI(asi)) { 875 __asm __volatile( 876 "wr %5,%%g0,%%asi; " 877 "sllx %4,32,%0; " 878 "rdpr %%pstate,%1; " 879 "or %3,%0,%0; " 880 "wrpr %1,8,%%pstate; " 881 "sta %2,[%0]%%asi; " 882 "wrpr %1,0,%%pstate; " 883 "membar #Sync; " 884 "wr %%g0, 0x82, %%asi " 885 : "=&r" (_loc_hi), "=&r" (_pstate) 886 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 887 : "memory"); 888 } else { 889 __asm __volatile( 890 "wr %4,%%g0,%%asi; " 891 "sllx %3,32,%0; " 892 "or %2,%0,%0; " 893 "sta %1,[%0]%%asi; " 894 "wr %%g0, 0x82, %%asi " 895 : "=&r" (_loc_hi) 896 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 897 : "memory"); 898 } 899 } 900 #endif 901 902 /* store 64-bit int to alternate address space */ 903 #ifdef __arch64__ 904 static __inline__ void 905 stda(paddr_t loc, int asi, u_int64_t value) 906 { 907 __asm __volatile( 908 "wr %2,%%g0,%%asi; " 909 "stda %0,[%1]%%asi; " 910 "wr %%g0, 0x82, %%asi " 911 : : "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi) 912 : "memory"); 913 } 914 #else 915 static __inline__ void 916 stda(paddr_t loc, int asi, u_int64_t value) 917 { 918 register int _loc_hi, _pstate; 919 920 _loc_hi = (((u_int64_t)loc)>>32); 921 if (PHYS_ASI(asi)) { 922 __asm __volatile( 923 "wr %5,%%g0,%%asi; " 924 "sllx %4,32,%0; " 925 "rdpr %%pstate,%1; " 926 "or %3,%0,%0; " 927 "wrpr %1,8,%%pstate; " 928 "stda %2,[%0]%%asi; " 929 "wrpr %1,0,%%pstate; " 930 "membar #Sync; " 931 "wr %%g0, 0x82, %%asi " 932 : "=&r" (_loc_hi), "=&r" (_pstate) 933 : "r" ((long long)(value)), "r" ((unsigned long)(loc)), 934 "r" (_loc_hi), "r" (asi) 935 : "memory"); 936 } else { 937 __asm __volatile( 938 "wr %4,%%g0,%%asi; " 939 "sllx %3,32,%0; " 940 "or %2,%0,%0; " 941 "stda %1,[%0]%%asi; " 942 "wr %%g0, 0x82, %%asi " 943 : "=&r" (_loc_hi) 944 : "r" ((long long)(value)), "r" ((unsigned long)(loc)), 945 "r" (_loc_hi), "r" (asi) 946 : "memory"); 947 } 948 } 949 #endif 950 951 #ifdef __arch64__ 952 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 953 static __inline__ void 954 stxa(paddr_t loc, int asi, u_int64_t value) 955 { 956 __asm __volatile( 957 "wr %2,%%g0,%%asi; " 958 "stxa %0,[%1]%%asi; " 959 "wr %%g0, 0x82, %%asi " 960 : : "r" ((unsigned long)(value)), 961 "r" ((unsigned long)(loc)), "r" (asi) 962 : "memory"); 963 } 964 #else 965 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 966 static __inline__ void 967 stxa(paddr_t loc, int asi, u_int64_t value) 968 { 969 int _stxa_lo, _stxa_hi, _loc_hi; 970 971 _stxa_lo = value; 972 _stxa_hi = ((u_int64_t)value)>>32; 973 _loc_hi = (((u_int64_t)loc)>>32); 974 975 if (PHYS_ASI(asi)) { 976 __asm __volatile( 977 "wr %7,%%g0,%%asi; " 978 "sllx %4,32,%1; " 979 "sllx %6,32,%0; " 980 "or %1,%3,%1; " 981 "rdpr %%pstate,%2; " 982 "or %0,%5,%0; " 983 "wrpr %2,8,%%pstate; " 984 "stxa %1,[%0]%%asi; " 985 "wrpr %2,0,%%pstate; " 986 "membar #Sync; " 987 "wr %%g0, 0x82, %%asi " 988 : "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)) 989 : "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 990 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 991 : "memory"); 992 } else { 993 __asm __volatile( 994 "wr %6,%%g0,%%asi; " 995 "sllx %3,32,%1; " 996 "sllx %5,32,%0; " 997 "or %1,%2,%1; " 998 "or %0,%4,%0; " 999 "stxa %1,[%0]%%asi; " 1000 "wr %%g0, 0x82, %%asi " 1001 : "=&r" (_loc_hi), "=&r" (_stxa_hi) 1002 : "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 1003 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 1004 : "memory"); 1005 } 1006 } 1007 #endif 1008 1009 #if 0 1010 #ifdef __arch64__ 1011 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 1012 static __inline__ u_int64_t 1013 casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) 1014 { 1015 __asm __volatile( 1016 "wr %3,%%g0,%%asi; " 1017 "casxa [%1]%%asi,%2,%0; " 1018 "wr %%g0, 0x82, %%asi " 1019 : "+r" (value) 1020 : "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) 1021 : "memory"); 1022 return (value); 1023 } 1024 #else 1025 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 1026 static __inline__ u_int64_t 1027 casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue) 1028 { 1029 int _casxa_lo, _casxa_hi, _loc_hi, _oval_hi; 1030 1031 _casxa_lo = value; 1032 _casxa_hi = ((u_int64_t)value)>>32; 1033 _oval_hi = ((u_int64_t)oldvalue)>>32; 1034 _loc_hi = (((u_int64_t)loc)>>32); 1035 1036 #ifdef __notyet 1037 /* 1038 * gcc cannot handle this since it thinks it has >10 asm operands. 1039 */ 1040 if (PHYS_ASI(asi)) { 1041 __asm __volatile( 1042 "wr %6,%%g0,%%asi; " 1043 "sllx %1,32,%1; " 1044 "rdpr %%pstate,%2; " 1045 "sllx %0,32,%0; " 1046 "or %1,%2,%1; " 1047 "sllx %3,32,%3; " 1048 "or %0,%4,%0; " 1049 "or %3,%5,%3; " 1050 "wrpr %2,8,%%pstate; " 1051 "casxa [%0]%%asi,%3,%1; " 1052 "wrpr %2,0,%%pstate; " 1053 "andn %0,0x1f,%3; " 1054 "membar #Sync; " 1055 "sll %1,0,%2; " 1056 "srax %1,32,%1; " 1057 "wr %%g0, 0x82, %%asi " 1058 : "+r" (_loc_hi), "+r" (_casxa_hi), "+r" (_casxa_lo), "+r" (_oval_hi) 1059 : "r" ((unsigned long)(loc)), "r" ((unsigned int)(oldvalue)), 1060 "r" (asi) 1061 : "memory"); 1062 } else { 1063 __asm __volatile( 1064 "wr %7,%%g0,%%asi; " 1065 "sllx %1,32,%1; " 1066 "sllx %5,32,%0; " 1067 "or %1,%2,%1; " 1068 "sllx %3,32,%2; " 1069 "or %0,%4,%0; " 1070 "or %2,%4,%2; " 1071 "casxa [%0]%%asi,%2,%1; " 1072 "sll %1,0,%2; " 1073 "srax %o1,32,%o1; " 1074 "wr %%g0, 0x82, %%asi " 1075 : "=&r" (_loc_hi), "+r" (_casxa_hi), "+r" (_casxa_lo) 1076 : "r" ((int)(_oval_hi)), "r" ((int)(oldvalue)), 1077 "r" ((unsigned long)(loc)), "r" (_loc_hi), 1078 "r" (asi) 1079 : "memory"); 1080 } 1081 #endif 1082 return (((u_int64_t)_casxa_hi<<32)|(u_int64_t)_casxa_lo); 1083 } 1084 #endif 1085 #endif /* 0 */ 1086 1087 /* flush address from data cache */ 1088 #define flush(loc) ({ \ 1089 __asm __volatile("flush %0" : : \ 1090 "r" ((unsigned long)(loc))); \ 1091 }) 1092 1093 /* Flush a D$ line */ 1094 #if 0 1095 #define flushline(loc) ({ \ 1096 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 1097 membar_sync(); \ 1098 }) 1099 #endif 1100 1101 /* The following two enable or disable the dcache in the LSU control register */ 1102 #define dcenable() ({ \ 1103 int res; \ 1104 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 1105 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 1106 }) 1107 #define dcdisable() ({ \ 1108 int res; \ 1109 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 1110 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 1111 }) 1112 1113 /* 1114 * SPARC V9 memory barrier instructions. 1115 */ 1116 /* Make all stores complete before next store */ 1117 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 1118 /* Make all loads complete before next store */ 1119 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 1120 /* Make all stores complete before next load */ 1121 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 1122 /* Make all loads complete before next load */ 1123 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 1124 /* Complete all outstanding memory operations and exceptions */ 1125 #define membar_sync() __asm __volatile("membar #Sync" : :) 1126 /* Complete all outstanding memory operations */ 1127 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 1128 /* Complete all outstanding stores before any new loads */ 1129 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 1130 1131 #ifdef __arch64__ 1132 /* read 64-bit %tick register */ 1133 #define tick() ({ \ 1134 register u_long _tick_tmp; \ 1135 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 1136 _tick_tmp; \ 1137 }) 1138 #else 1139 /* read 64-bit %tick register on 32-bit system */ 1140 #define tick() ({ \ 1141 register u_int _tick_hi = 0, _tick_lo = 0; \ 1142 __asm __volatile("rdpr %%tick, %0; srl %0,0,%1; srlx %0,32,%0 " \ 1143 : "=r" (_tick_hi), "=r" (_tick_lo) : ); \ 1144 (((u_int64_t)_tick_hi)<<32)|((u_int64_t)_tick_lo); \ 1145 }) 1146 #endif 1147 1148 extern void next_tick __P((long)); 1149 #endif 1150 1151 #endif /* _SPARC_CTLREG_H_ */ 1152
Indexes created Mon Sep 29 21:09:56 GMT 2025