ctlreg.h revision 1.44.38.3
1 /* $NetBSD: ctlreg.h,v 1.44.38.3 2010/08/11 22:52:47 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _SPARC_CTLREG_H_ 27 #define _SPARC_CTLREG_H_ 28 29 /* 30 * Sun 4u control registers. (includes address space definitions 31 * and some registers in control space). 32 */ 33 34 /* 35 * The Alternate address spaces. 36 * 37 * 0x00-0x7f are privileged 38 * 0x80-0xff can be used by users 39 */ 40 41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 42 43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 45 46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 48 49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 51 52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */ 54 55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 57 58 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 59 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 60 61 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 62 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 63 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 64 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 65 66 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */ 67 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */ 68 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */ 69 70 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 71 72 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 73 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 74 75 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 76 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 77 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 78 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 79 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 80 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 81 82 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to I-cache data RAM */ 83 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to I-cache tag RAM */ 84 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush I-cache page using primary context */ 85 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush I-cache page using secondary context */ 86 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush I-cache context using primary context */ 87 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush I-cache context using secondary context */ 88 89 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 90 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 91 92 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 93 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 94 95 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 96 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 97 98 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 99 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 100 101 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 102 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 103 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 104 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 105 106 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 107 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 108 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 109 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 110 111 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 112 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 113 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 114 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 115 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 116 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 117 118 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 119 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 120 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 121 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 122 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 123 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 124 125 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 126 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 127 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 128 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 129 130 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 131 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 132 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 133 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 134 135 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 136 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 137 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 138 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 139 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 140 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 141 142 143 /* 144 * These are the shorter names used by Solaris 145 */ 146 147 #define ASI_N ASI_NUCLEUS 148 #define ASI_NL ASI_NUCLEUS_LITTLE 149 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 150 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 151 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 152 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 153 #define ASI_P ASI_PRIMARY 154 #define ASI_S ASI_SECONDARY 155 #define ASI_PNF ASI_PRIMARY_NOFAULT 156 #define ASI_SNF ASI_SECONDARY_NOFAULT 157 #define ASI_PL ASI_PRIMARY_LITTLE 158 #define ASI_SL ASI_SECONDARY_LITTLE 159 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 160 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 161 #define ASI_FL8_P ASI_FL8_PRIMARY 162 #define ASI_FL8_S ASI_FL8_SECONDARY 163 #define ASI_FL16_P ASI_FL16_PRIMARY 164 #define ASI_FL16_S ASI_FL16_SECONDARY 165 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 166 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 167 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 168 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 169 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 170 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 171 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 172 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 173 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 174 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 175 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 176 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 177 #define ASI_BLK_P ASI_BLOCK_PRIMARY 178 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 179 #define ASI_BLK_S ASI_BLOCK_SECONDARY 180 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 181 182 /* Alternative spellings */ 183 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 184 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 185 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 186 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 187 188 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 189 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 190 191 /* 192 * The following are 4u control registers 193 */ 194 195 /* Get the CPU's UPAID */ 196 #define UPA_CR_MID_SHIFT (17) 197 #define UPA_CR_MID_SIZE (5) 198 #define UPA_CR_MID_MASK \ 199 (((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT) 200 201 #define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1)) 202 203 #ifdef _LOCORE 204 205 #define UPA_GET_MID(r1) \ 206 ldxa [%g0] ASI_MID_REG, r1 ; \ 207 srlx r1, UPA_CR_MID_SHIFT, r1 ; \ 208 and r1, (1 << UPA_CR_MID_SIZE) - 1, r1 209 210 #else 211 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 212 #endif 213 214 /* 215 * [4u] MMU and Cache Control Register (MCCR) 216 * use ASI = 0x45 217 */ 218 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 219 #define MCCR 0x00 220 221 /* MCCR Bits and their meanings */ 222 #define MCCR_DMMU_EN 0x08 223 #define MCCR_IMMU_EN 0x04 224 #define MCCR_DCACHE_EN 0x02 225 #define MCCR_ICACHE_EN 0x01 226 227 228 /* 229 * MMU control registers 230 */ 231 232 /* Choose an MMU */ 233 #define ASI_DMMU 0x58 234 #define ASI_IMMU 0x50 235 236 /* Other assorted MMU ASIs */ 237 #define ASI_IMMU_8KPTR 0x51 238 #define ASI_IMMU_64KPTR 0x52 239 #define ASI_IMMU_DATA_IN 0x54 240 #define ASI_IMMU_TLB_DATA 0x55 241 #define ASI_IMMU_TLB_TAG 0x56 242 #define ASI_DMMU_8KPTR 0x59 243 #define ASI_DMMU_64KPTR 0x5a 244 #define ASI_DMMU_DATA_IN 0x5c 245 #define ASI_DMMU_TLB_DATA 0x5d 246 #define ASI_DMMU_TLB_TAG 0x5e 247 248 /* 249 * The following are the control registers 250 * They work on both MMUs unless noted. 251 * III = cheetah only 252 * 253 * Register contents are defined later on individual registers. 254 */ 255 #define TSB_TAG_TARGET 0x0 256 #define TLB_DATA_IN 0x0 257 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 258 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 259 #define SFSR 0x18 260 #define SFAR 0x20 /* fault address -- DMMU only */ 261 #define TSB 0x28 262 #define TLB_TAG_ACCESS 0x30 263 #define VIRTUAL_WATCHPOINT 0x38 264 #define PHYSICAL_WATCHPOINT 0x40 265 #define TSB_PEXT 0x48 /* III primary ext */ 266 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */ 267 #define TSB_NEXT 0x58 /* III nucleus ext */ 268 269 /* Tag Target bits */ 270 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 271 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 272 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 273 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 274 275 /* SFSR bits for both D_SFSR and I_SFSR */ 276 #define SFSR_ASI(x) ((x)>>16) 277 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 278 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 279 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 280 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 281 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 282 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 283 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 284 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 285 #define SFSR_CTXT(x) (((x)>>4)&0x3) 286 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 287 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 288 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 289 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 290 #define SFSR_W 0x00004 /* DMMU: attempted write */ 291 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 292 #define SFSR_FV 0x00001 /* Fault is valid */ 293 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \ 294 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 295 296 #define SFSR_BITS "\177\20" \ 297 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \ 298 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \ 299 "b\3W\0" "b\2OW\0" "b\1FV\0" 300 301 /* ASFR bits */ 302 #define ASFR_ME 0x100000000LL 303 #define ASFR_PRIV 0x080000000LL 304 #define ASFR_ISAP 0x040000000LL 305 #define ASFR_ETP 0x020000000LL 306 #define ASFR_IVUE 0x010000000LL 307 #define ASFR_TO 0x008000000LL 308 #define ASFR_BERR 0x004000000LL 309 #define ASFR_LDP 0x002000000LL 310 #define ASFR_CP 0x001000000LL 311 #define ASFR_WP 0x000800000LL 312 #define ASFR_EDP 0x000400000LL 313 #define ASFR_UE 0x000200000LL 314 #define ASFR_CE 0x000100000LL 315 #define ASFR_ETS 0x0000f0000LL 316 #define ASFT_P_SYND 0x00000ffffLL 317 318 #define AFSR_BITS "\177\20" \ 319 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 320 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 321 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 322 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 323 324 /* 325 * Here's the spitfire TSB control register bits. 326 * 327 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 328 */ 329 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 330 #define TSB_SIZE_1K 0x01 331 #define TSB_SIZE_2K 0x02 332 #define TSB_SIZE_4K 0x03 333 #define TSB_SIZE_8K 0x04 334 #define TSB_SIZE_16K 0x05 335 #define TSB_SIZE_32K 0x06 336 #define TSB_SIZE_64K 0x07 337 #define TSB_SPLIT 0x1000 338 #define TSB_BASE 0xffffffffffffe000 339 340 /* TLB Tag Access bits */ 341 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 342 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 343 344 /* 345 * TLB demap registers. TTEs are defined in v9pte.h 346 * 347 * Use the address space to select between IMMU and DMMU. 348 * The address of the register selects which context register 349 * to read the ASI from. 350 * 351 * The data stored in the register is interpreted as the VA to 352 * use. The DEMAP_CTX_<> registers ignore the address and demap the 353 * entire ASI. 354 * 355 */ 356 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 357 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 358 359 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 360 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 361 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 362 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 363 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 364 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 365 #define DEMAP_ALL ((0x08)<<4) /* Demap all non-locked TLB entries [USIII] */ 366 367 /* 368 * These define the sizes of the TLB in various CPUs. 369 * They're mostly not necessary except for diagnostic code. 370 */ 371 #define TLB_SIZE_SPITFIRE 64 372 #define TLB_SIZE_CHEETAH_I16 16 373 #define TLB_SIZE_CHEETAH_I128 128 374 #define TLB_SIZE_CHEETAH_D16 16 375 #define TLB_SIZE_CHEETAH_D512_0 512 376 #define TLB_SIZE_CHEETAH_D512_1 512 377 #define TLB_CHEETAH_I16 (0 << 16) 378 #define TLB_CHEETAH_I128 (2 << 16) 379 #define TLB_CHEETAH_D16 (0 << 16) 380 #define TLB_CHEETAH_D512_0 (2 << 16) 381 #define TLB_CHEETAH_D512_1 (3 << 16) 382 383 /* 384 * Interrupt registers. This really gets hairy. 385 */ 386 387 /* IRSR -- Interrupt Receive Status Ragister */ 388 #define ASI_IRSR 0x49 389 #define IRSR 0x00 390 #define IRSR_BUSY 0x020 391 #define IRSR_MID(x) (x&0x1f) 392 393 /* IRDR -- Interrupt Receive Data Registers */ 394 #define ASI_IRDR 0x7f 395 #define IRDR_0H 0x40 396 #define IRDR_0L 0x48 /* unimplemented */ 397 #define IRDR_1H 0x50 398 #define IRDR_1L 0x58 /* unimplemented */ 399 #define IRDR_2H 0x60 400 #define IRDR_2L 0x68 /* unimplemented */ 401 #define IRDR_3H 0x70 /* unimplemented */ 402 #define IRDR_3L 0x78 /* unimplemented */ 403 404 /* SOFTINT ASRs */ 405 #define SET_SOFTINT %asr20 /* Sets these bits */ 406 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 407 #define SOFTINT %asr22 /* Reads the register */ 408 #define TICK_CMPR %asr23 409 410 #define TICK_INT 0x01 /* level-14 clock tick */ 411 #define SOFTINT1 (0x1<<1) 412 #define SOFTINT2 (0x1<<2) 413 #define SOFTINT3 (0x1<<3) 414 #define SOFTINT4 (0x1<<4) 415 #define SOFTINT5 (0x1<<5) 416 #define SOFTINT6 (0x1<<6) 417 #define SOFTINT7 (0x1<<7) 418 #define SOFTINT8 (0x1<<8) 419 #define SOFTINT9 (0x1<<9) 420 #define SOFTINT10 (0x1<<10) 421 #define SOFTINT11 (0x1<<11) 422 #define SOFTINT12 (0x1<<12) 423 #define SOFTINT13 (0x1<<13) 424 #define SOFTINT14 (0x1<<14) 425 #define SOFTINT15 (0x1<<15) 426 427 /* Interrupt Dispatch -- usually reserved for cross-calls */ 428 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 429 #define IDSR 0x00 430 #define IDSR_NACK 0x02 431 #define IDSR_BUSY 0x01 432 433 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 434 435 /* Interrupt delivery initiation */ 436 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 437 438 #define IDDR_0H 0x40 /* Store data to send in these regs */ 439 #define IDDR_0L 0x48 /* unimplemented */ 440 #define IDDR_1H 0x50 441 #define IDDR_1L 0x58 /* unimplemented */ 442 #define IDDR_2H 0x60 443 #define IDDR_2L 0x68 /* unimplemented */ 444 #define IDDR_3H 0x70 /* unimplemented */ 445 #define IDDR_3L 0x78 /* unimplemented */ 446 447 /* 448 * Error registers 449 */ 450 451 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 452 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 453 #define AFAR 0x00 454 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 455 #define AFSR 0x00 456 457 #define ASI_P_EER 0x4b /* Error enable register */ 458 #define P_EER 0x00 459 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 460 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 461 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 462 463 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 464 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 465 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 466 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 467 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 468 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 469 470 471 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 472 473 #ifndef _LOCORE 474 /* 475 * GCC __asm constructs for doing assembly stuff. 476 */ 477 478 /* 479 * ``Routines'' to load and store from/to alternate address space. 480 * The location can be a variable, the asi value (address space indicator) 481 * must be a constant. 482 * 483 * N.B.: You can put as many special functions here as you like, since 484 * they cost no kernel space or time if they are not used. 485 * 486 * These were static inline functions, but gcc screws up the constraints 487 * on the address space identifiers (the "n"umeric value part) because 488 * it inlines too late, so we have to use the funny valued-macro syntax. 489 */ 490 491 /* 492 * Apparently the definition of bypass ASIs is that they all use the 493 * D$ so we need to flush the D$ to make sure we don't get data pollution. 494 */ 495 496 #ifdef __arch64__ 497 498 /* 64-bit kernel, non-constant */ 499 #define SPARC64_LD_NONCONST(ld) \ 500 __asm volatile( \ 501 "wr %2,%%g0,%%asi; " \ 502 #ld " [%1]%%asi,%0 " \ 503 : "=r" (_v) \ 504 : "r" ((__uintptr_t)(loc)), "r" (asi)) 505 506 #if defined(__GNUC__) && defined(__OPTIMIZE__) 507 #define SPARC64_LD_DEF(ld, type, vtype) \ 508 static __inline type ld(paddr_t loc, int asi) \ 509 { \ 510 vtype _v; \ 511 if (__builtin_constant_p(asi)) \ 512 __asm volatile( \ 513 #ld " [%1]%2,%0 " \ 514 : "=r" (_v) \ 515 : "r" ((__uintptr_t)(loc)), "n" (asi)); \ 516 else \ 517 SPARC64_LD_NONCONST(ld); \ 518 return _v; \ 519 } 520 #else 521 #define SPARC64_LD_DEF(ld, type, vtype) \ 522 static __inline type ld(paddr_t loc, int asi) \ 523 { \ 524 vtype _v; \ 525 SPARC64_LD_NONCONST(ld); \ 526 return _v; \ 527 } 528 #endif 529 #define SPARC64_LD_DEF64(ld, type) SPARC64_LD_DEF(ld, type, uint64_t) 530 531 #else /* __arch64__ */ 532 533 /* 32-bit kernel, MMU bypass, non-constant */ 534 #define SPARC64_LD_PHYS_NONCONST(ld) \ 535 __asm volatile( \ 536 "clruw %2; " \ 537 "rdpr %%pstate,%1; " \ 538 "sllx %3,32,%0; " \ 539 "wrpr %1,8,%%pstate; " \ 540 "or %0,%2,%0; " \ 541 "wr %4,%%g0,%%asi; " \ 542 #ld " [%0]%%asi,%0; " \ 543 "wrpr %1,0,%%pstate " \ 544 : "=&r" (_v), "=&r" (_pstate) \ 545 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 546 /* 32-bit kernel, non-constant */ 547 #define SPARC64_LD_NONCONST(ld) \ 548 __asm volatile( \ 549 "wr %2,%%g0,%%asi; " \ 550 #ld " [%1]%%asi,%0 " \ 551 : "=&r" (_v) \ 552 : "r" ((uint32_t)(loc)), "r" (asi)) 553 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 554 #define SPARC64_LD_PHYS_NONCONST64(ld) \ 555 __asm volatile( \ 556 "clruw %2; " \ 557 "rdpr %%pstate,%1; " \ 558 "sllx %3,32,%0; " \ 559 "wrpr %1,8,%%pstate; " \ 560 "or %0,%2,%0; " \ 561 "wr %4,%%g0,%%asi; " \ 562 #ld " [%0]%%asi,%0; " \ 563 "wrpr %1,0,%%pstate; " \ 564 "srlx %0,32,%1; " \ 565 "srl %0,0,%0 " \ 566 : "=&r" (_vlo), "=&r" (_vhi) \ 567 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 568 /* 32-bit kernel, non-constant, 64-bit value */ 569 #define SPARC64_LD_NONCONST64(ld) \ 570 __asm volatile( \ 571 "wr %3,%%g0,%%asi; " \ 572 #ld " [%2]%%asi,%0; " \ 573 "srlx %0,32,%1; " \ 574 "srl %0,0,%0 " \ 575 : "=&r" (_vlo), "=&r" (_vhi) \ 576 : "r" ((uint32_t)(loc)), "r" (asi)) 577 578 #if defined(__GNUC__) && defined(__OPTIMIZE__) 579 #define SPARC64_LD_DEF(ld, type, vtype) \ 580 static __inline type ld(paddr_t loc, int asi) \ 581 { \ 582 vtype _v; \ 583 uint32_t _hi, _pstate; \ 584 if (PHYS_ASI(asi)) { \ 585 _hi = (uint64_t)(loc) >> 32; \ 586 if (__builtin_constant_p(asi)) \ 587 __asm volatile( \ 588 "clruw %2; " \ 589 "rdpr %%pstate,%1; " \ 590 "sllx %3,32,%0; " \ 591 "wrpr %1,8,%%pstate; " \ 592 "or %0,%2,%0; " \ 593 #ld " [%0]%4,%0; " \ 594 "wrpr %1,0,%%pstate; " \ 595 : "=&r" (_v), "=&r" (_pstate) \ 596 : "r" ((uint32_t)(loc)), "r" (_hi), \ 597 "n" (asi)); \ 598 else \ 599 SPARC64_LD_PHYS_NONCONST(ld); \ 600 } else { \ 601 if (__builtin_constant_p(asi)) \ 602 __asm volatile( \ 603 #ld " [%1]%2,%0 " \ 604 : "=&r" (_v) \ 605 : "r" ((uint32_t)(loc)), "n" (asi)); \ 606 else \ 607 SPARC64_LD_NONCONST(ld); \ 608 } \ 609 return _v; \ 610 } 611 #define SPARC64_LD_DEF64(ld, type) \ 612 static __inline type ld(paddr_t loc, int asi) \ 613 { \ 614 uint32_t _vlo, _vhi, _hi; \ 615 if (PHYS_ASI(asi)) { \ 616 _hi = (uint64_t)(loc) >> 32; \ 617 if (__builtin_constant_p(asi)) \ 618 __asm volatile( \ 619 "clruw %2; " \ 620 "rdpr %%pstate,%1; " \ 621 "sllx %3,32,%0; " \ 622 "wrpr %1,8,%%pstate; " \ 623 "or %0,%2,%0; " \ 624 #ld " [%0]%4,%0; " \ 625 "wrpr %1,0,%%pstate; " \ 626 "srlx %0,32,%1; " \ 627 "srl %0,0,%0 " \ 628 : "=&r" (_vlo), "=&r" (_vhi) \ 629 : "r" ((uint32_t)(loc)), "r" (_hi), \ 630 "n" (asi)); \ 631 else \ 632 SPARC64_LD_PHYS_NONCONST64(ld); \ 633 } else { \ 634 if (__builtin_constant_p(asi)) \ 635 __asm volatile( \ 636 #ld " [%2]%3,%0; " \ 637 "srlx %0,32,%1; " \ 638 "srl %0,0,%0 " \ 639 : "=&r" (_vlo), "=&r" (_vhi) \ 640 : "r" ((uint32_t)(loc)), "n" (asi)); \ 641 else \ 642 SPARC64_LD_NONCONST64(ld); \ 643 } \ 644 return ((uint64_t)_vhi << 32) | _vlo; \ 645 } 646 #else 647 #define SPARC64_LD_DEF(ld, type, vtype) \ 648 static __inline type ld(paddr_t loc, int asi) \ 649 { \ 650 vtype _v; \ 651 uint32_t _hi, _pstate; \ 652 if (PHYS_ASI(asi)) { \ 653 _hi = (uint64_t)(loc) >> 32; \ 654 SPARC64_LD_PHYS_NONCONST(ld); \ 655 } else \ 656 SPARC64_LD_NONCONST(ld); \ 657 return _v; \ 658 } 659 #define SPARC64_LD_DEF64(ld, type) \ 660 static __inline type ld(paddr_t loc, int asi) \ 661 { \ 662 uint32_t _vlo, _vhi, _hi; \ 663 if (PHYS_ASI(asi)) { \ 664 _hi = (uint64_t)(loc) >> 32; \ 665 SPARC64_LD_PHYS_NONCONST64(ld); \ 666 } else \ 667 SPARC64_LD_NONCONST64(ld); \ 668 return ((uint64_t)_vhi << 32) | _vlo; \ 669 } 670 #endif 671 672 #endif /* __arch64__ */ 673 674 /* load byte from alternate address space */ 675 SPARC64_LD_DEF(lduba, uint8_t, uint32_t) 676 /* load half-word from alternate address space */ 677 SPARC64_LD_DEF(lduha, uint16_t, uint32_t) 678 /* load unsigned int from alternate address space */ 679 SPARC64_LD_DEF(lda, uint32_t, uint32_t) 680 /* load signed int from alternate address space */ 681 SPARC64_LD_DEF(ldswa, int, int) 682 /* load 64-bit unsigned int from alternate address space */ 683 SPARC64_LD_DEF64(ldxa, uint64_t) 684 685 686 #ifdef __arch64__ 687 688 /* 64-bit kernel, non-constant */ 689 #define SPARC64_ST_NONCONST(st) \ 690 __asm volatile( \ 691 "wr %2,%%g0,%%asi; " \ 692 #st " %0,[%1]%%asi " \ 693 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 694 "r" (asi)) 695 696 #if defined(__GNUC__) && defined(__OPTIMIZE__) 697 #define SPARC64_ST_DEF(st, type) \ 698 static __inline void st(paddr_t loc, int asi, type value) \ 699 { \ 700 if (__builtin_constant_p(asi)) \ 701 __asm volatile( \ 702 #st " %0,[%1]%2 " \ 703 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 704 "n" (asi)); \ 705 else \ 706 SPARC64_ST_NONCONST(st); \ 707 } 708 #else 709 #define SPARC64_ST_DEF(st, type) \ 710 static __inline void st(paddr_t loc, int asi, type value) \ 711 { \ 712 SPARC64_ST_NONCONST(st); \ 713 } 714 #endif 715 #define SPARC64_ST_DEF64(st, type) SPARC64_ST_DEF(st, type) 716 717 #else /* __arch64__ */ 718 719 /* 32-bit kernel, MMU bypass, non-constant */ 720 #define SPARC64_ST_PHYS_NONCONST(st) \ 721 __asm volatile( \ 722 "clruw %3; " \ 723 "rdpr %%pstate,%1; " \ 724 "sllx %4,32,%0; " \ 725 "wrpr %1,8,%%pstate; " \ 726 "or %0,%3,%0; " \ 727 "wr %5,%%g0,%%asi; " \ 728 #st " %2,[%0]%%asi; " \ 729 "wrpr %1,0,%%pstate " \ 730 : "=&r" (_hi), "=&r" (_pstate) \ 731 : "r" (value), "r" ((uint32_t)(loc)), \ 732 "r" (_hi), "r" (asi)) 733 /* 32-bit kernel, non-constant */ 734 #define SPARC64_ST_NONCONST(st) \ 735 __asm volatile( \ 736 "wr %2,%%g0,%%asi; " \ 737 #st " %0,[%1]%%asi " \ 738 : : "r" (value), "r" ((uint32_t)(loc)), "r" (asi)) 739 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 740 #define SPARC64_ST_PHYS_NONCONST64(st) \ 741 __asm volatile( \ 742 "clruw %3; " \ 743 "clruw %5; " \ 744 "sllx %4,32,%1; " \ 745 "sllx %6,32,%0; " \ 746 "rdpr %%pstate,%2; " \ 747 "or %1,%3,%1; " \ 748 "wrpr %2,8,%%pstate; " \ 749 "or %0,%5,%0; " \ 750 "wr %7,%%g0,%%asi; " \ 751 #st " %1,[%0]%%asi; " \ 752 "wrpr %2,0,%%pstate " \ 753 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 754 : "r" (_vlo), "r" (_vhi), \ 755 "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 756 /* 32-bit kernel, non-constant, 64-bit value */ 757 #define SPARC64_ST_NONCONST64(st) \ 758 __asm volatile( \ 759 "clruw %1; " \ 760 "sllx %2,32,%0; " \ 761 "or %0,%1,%0; " \ 762 "wr %4,%%g0,%%asi; " \ 763 #st " %0,[%3]%%asi " \ 764 : "=&r" (_vhi) \ 765 : "r" (_vlo), "r" (_vhi), \ 766 "r" ((uint32_t)(loc)), "r" (asi)) 767 768 #if defined(__GNUC__) && defined(__OPTIMIZE__) 769 #define SPARC64_ST_DEF(st, type) \ 770 static __inline void st(paddr_t loc, int asi, type value) \ 771 { \ 772 uint32_t _hi, _pstate; \ 773 if (PHYS_ASI(asi)) { \ 774 _hi = (uint64_t)(loc) >> 32; \ 775 if (__builtin_constant_p(asi)) \ 776 __asm volatile( \ 777 "clruw %3; " \ 778 "sllx %4,32,%0; " \ 779 "rdpr %%pstate,%1; " \ 780 "or %0,%3,%0; " \ 781 "wrpr %1,8,%%pstate; " \ 782 #st " %2,[%0]%5; " \ 783 "wrpr %1,0,%%pstate " \ 784 : "=&r" (_hi), "=&r" (_pstate) \ 785 : "r" (value), "r" ((uint32_t)(loc)), \ 786 "r" (_hi), "n" (asi)); \ 787 else \ 788 SPARC64_ST_PHYS_NONCONST(st); \ 789 } else { \ 790 if (__builtin_constant_p(asi)) \ 791 __asm volatile( \ 792 #st " %0,[%1]%2 " \ 793 : : "r" (value), "r" ((uint32_t)(loc)), \ 794 "n" (asi)); \ 795 else \ 796 SPARC64_ST_NONCONST(st); \ 797 } \ 798 } 799 #define SPARC64_ST_DEF64(st, type) \ 800 static __inline void st(paddr_t loc, int asi, type value) \ 801 { \ 802 uint32_t _vlo, _vhi, _hi; \ 803 _vlo = value; \ 804 _vhi = (uint64_t)(value) >> 32; \ 805 if (PHYS_ASI(asi)) { \ 806 _hi = (uint64_t)(loc) >> 32; \ 807 if (__builtin_constant_p(asi)) \ 808 __asm volatile( \ 809 "clruw %3; " \ 810 "clruw %5; " \ 811 "sllx %4,32,%1; " \ 812 "sllx %6,32,%0; " \ 813 "rdpr %%pstate,%2; " \ 814 "or %1,%3,%1; " \ 815 "or %0,%5,%0; " \ 816 "wrpr %2,8,%%pstate; " \ 817 #st " %1,[%0]%7; " \ 818 "wrpr %2,0,%%pstate " \ 819 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 820 : "r" (_vlo), "r" (_vhi), \ 821 "r" ((uint32_t)(loc)), "r" (_hi), \ 822 "n" (asi)); \ 823 else \ 824 SPARC64_ST_PHYS_NONCONST64(st); \ 825 } else { \ 826 if (__builtin_constant_p(asi)) \ 827 __asm volatile( \ 828 "clruw %1; " \ 829 "sllx %2,32,%0; " \ 830 "or %0,%1,%0; " \ 831 #st " %0,[%3]%4 " \ 832 : "=&r" (_vhi) \ 833 : "r" (_vlo), "r" (_vhi), \ 834 "r" ((uint32_t)(loc)), "n" (asi)); \ 835 else \ 836 SPARC64_ST_NONCONST64(st); \ 837 } \ 838 } 839 #else 840 #define SPARC64_ST_DEF(st, type) \ 841 static __inline void st(paddr_t loc, int asi, type value) \ 842 { \ 843 uint32_t _hi, _pstate; \ 844 if (PHYS_ASI(asi)) { \ 845 _hi = (uint64_t)(loc) >> 32; \ 846 SPARC64_ST_PHYS_NONCONST(st); \ 847 } else \ 848 SPARC64_ST_NONCONST(st); \ 849 } 850 #define SPARC64_ST_DEF64(st, type) \ 851 static __inline void st(paddr_t loc, int asi, type value) \ 852 { \ 853 uint32_t _vlo, _vhi, _hi; \ 854 _vlo = value; \ 855 _vhi = (uint64_t)(value) >> 32; \ 856 if (PHYS_ASI(asi)) { \ 857 _hi = (uint64_t)(loc) >> 32; \ 858 SPARC64_ST_PHYS_NONCONST64(st); \ 859 } else \ 860 SPARC64_ST_NONCONST64(st); \ 861 } 862 #endif 863 864 #endif /* __arch64__ */ 865 866 /* store byte to alternate address space */ 867 SPARC64_ST_DEF(stba, uint8_t) 868 /* store half-word to alternate address space */ 869 SPARC64_ST_DEF(stha, uint16_t) 870 /* store unsigned int to alternate address space */ 871 SPARC64_ST_DEF(sta, uint32_t) 872 /* store 64-bit unsigned int to alternate address space */ 873 SPARC64_ST_DEF64(stxa, uint64_t) 874 875 876 /* set dmmu secondary context */ 877 static __inline void 878 dmmu_set_secondary_context(uint ctx) 879 { 880 __asm volatile( 881 "stxa %0,[%1]%2; " 882 "membar #Sync " 883 : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU) 884 : "memory"); 885 } 886 887 /* flush address from data cache */ 888 #define flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc))) 889 890 /* 891 * SPARC V9 memory barrier instructions. 892 */ 893 /* Make all stores complete before next store */ 894 #define membar_storestore() __asm volatile("membar #StoreStore" : :) 895 /* Make all loads complete before next store */ 896 #define membar_loadstore() __asm volatile("membar #LoadStore" : :) 897 /* Make all stores complete before next load */ 898 #define membar_storeload() __asm volatile("membar #StoreLoad" : :) 899 /* Make all loads complete before next load */ 900 #define membar_loadload() __asm volatile("membar #LoadLoad" : :) 901 /* Complete all outstanding memory operations and exceptions */ 902 #define membar_sync() __asm volatile("membar #Sync" : :) 903 /* Complete all outstanding memory operations */ 904 #define membar_memissue() __asm volatile("membar #MemIssue" : :) 905 /* Complete all outstanding stores before any new loads */ 906 #define membar_lookaside() __asm volatile("membar #Lookaside" : :) 907 908 #define membar_load() __asm volatile("membar #LoadLoad | #LoadStore" : :) 909 #define membar_store() __asm volatile("membar #LoadStore | #StoreStore" : :) 910 911 #endif 912 913 #endif /* _SPARC_CTLREG_H_ */ 914
Indexes created Sat Oct 25 07:10:08 GMT 2025