ctlreg.h revision 1.46
1 /* $NetBSD: ctlreg.h,v 1.46 2009/11/28 21:07:02 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _SPARC_CTLREG_H_ 27 #define _SPARC_CTLREG_H_ 28 29 /* 30 * Sun 4u control registers. (includes address space definitions 31 * and some registers in control space). 32 */ 33 34 /* 35 * The Alternate address spaces. 36 * 37 * 0x00-0x7f are privileged 38 * 0x80-0xff can be used by users 39 */ 40 41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 42 43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 45 46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 48 49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 51 52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */ 54 55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 57 58 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 59 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 60 61 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 62 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 63 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 64 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 65 66 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */ 67 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */ 68 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */ 69 70 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 71 72 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 73 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 74 75 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 76 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 77 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 78 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 79 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 80 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 81 82 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 83 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 84 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 85 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 86 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 87 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 88 89 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 90 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 91 92 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 93 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 94 95 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 96 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 97 98 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 99 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 100 101 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 102 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 103 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 104 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 105 106 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 107 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 108 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 109 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 110 111 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 112 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 113 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 114 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 115 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 116 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 117 118 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 119 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 120 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 121 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 122 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 123 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 124 125 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 126 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 127 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 128 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 129 130 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 131 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 132 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 133 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 134 135 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 136 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 137 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 138 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 139 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 140 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 141 142 143 /* 144 * These are the shorter names used by Solaris 145 */ 146 147 #define ASI_N ASI_NUCLEUS 148 #define ASI_NL ASI_NUCLEUS_LITTLE 149 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 150 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 151 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 152 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 153 #define ASI_P ASI_PRIMARY 154 #define ASI_S ASI_SECONDARY 155 #define ASI_PNF ASI_PRIMARY_NOFAULT 156 #define ASI_SNF ASI_SECONDARY_NOFAULT 157 #define ASI_PL ASI_PRIMARY_LITTLE 158 #define ASI_SL ASI_SECONDARY_LITTLE 159 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 160 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 161 #define ASI_FL8_P ASI_FL8_PRIMARY 162 #define ASI_FL8_S ASI_FL8_SECONDARY 163 #define ASI_FL16_P ASI_FL16_PRIMARY 164 #define ASI_FL16_S ASI_FL16_SECONDARY 165 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 166 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 167 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 168 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 169 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 170 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 171 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 172 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 173 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 174 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 175 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 176 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 177 #define ASI_BLK_P ASI_BLOCK_PRIMARY 178 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 179 #define ASI_BLK_S ASI_BLOCK_SECONDARY 180 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 181 182 /* Alternative spellings */ 183 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 184 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 185 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 186 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 187 188 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 189 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 190 191 /* 192 * The following are 4u control registers 193 */ 194 195 /* Get the CPU's UPAID */ 196 #define UPA_CR_MID_SHIFT (17) 197 #define UPA_CR_MID_SIZE (5) 198 #define UPA_CR_MID_MASK \ 199 (((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT) 200 201 #define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1)) 202 203 #ifdef _LOCORE 204 205 #define UPA_GET_MID(r1) \ 206 ldxa [%g0] ASI_MID_REG, r1 ; \ 207 srlx r1, UPA_CR_MID_SHIFT, r1 ; \ 208 and r1, (1 << UPA_CR_MID_SIZE) - 1, r1 209 210 #else 211 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 212 #endif 213 214 /* 215 * [4u] MMU and Cache Control Register (MCCR) 216 * use ASI = 0x45 217 */ 218 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 219 #define MCCR 0x00 220 221 /* MCCR Bits and their meanings */ 222 #define MCCR_DMMU_EN 0x08 223 #define MCCR_IMMU_EN 0x04 224 #define MCCR_DCACHE_EN 0x02 225 #define MCCR_ICACHE_EN 0x01 226 227 228 /* 229 * MMU control registers 230 */ 231 232 /* Choose an MMU */ 233 #define ASI_DMMU 0x58 234 #define ASI_IMMU 0x50 235 236 /* Other assorted MMU ASIs */ 237 #define ASI_IMMU_8KPTR 0x51 238 #define ASI_IMMU_64KPTR 0x52 239 #define ASI_IMMU_DATA_IN 0x54 240 #define ASI_IMMU_TLB_DATA 0x55 241 #define ASI_IMMU_TLB_TAG 0x56 242 #define ASI_DMMU_8KPTR 0x59 243 #define ASI_DMMU_64KPTR 0x5a 244 #define ASI_DMMU_DATA_IN 0x5c 245 #define ASI_DMMU_TLB_DATA 0x5d 246 #define ASI_DMMU_TLB_TAG 0x5e 247 248 /* 249 * The following are the control registers 250 * They work on both MMUs unless noted. 251 * III = cheetah only 252 * 253 * Register contents are defined later on individual registers. 254 */ 255 #define TSB_TAG_TARGET 0x0 256 #define TLB_DATA_IN 0x0 257 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 258 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 259 #define SFSR 0x18 260 #define SFAR 0x20 /* fault address -- DMMU only */ 261 #define TSB 0x28 262 #define TLB_TAG_ACCESS 0x30 263 #define VIRTUAL_WATCHPOINT 0x38 264 #define PHYSICAL_WATCHPOINT 0x40 265 #define TSB_PEXT 0x48 /* III primary ext */ 266 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */ 267 #define TSB_NEXT 0x58 /* III nucleus ext */ 268 269 /* Tag Target bits */ 270 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 271 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 272 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 273 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 274 275 /* SFSR bits for both D_SFSR and I_SFSR */ 276 #define SFSR_ASI(x) ((x)>>16) 277 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 278 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 279 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 280 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 281 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 282 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 283 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 284 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 285 #define SFSR_CTXT(x) (((x)>>4)&0x3) 286 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 287 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 288 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 289 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 290 #define SFSR_W 0x00004 /* DMMU: attempted write */ 291 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 292 #define SFSR_FV 0x00001 /* Fault is valid */ 293 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \ 294 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 295 296 #define SFSR_BITS "\177\20" \ 297 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \ 298 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \ 299 "b\3W\0" "b\2OW\0" "b\1FV\0" 300 301 /* ASFR bits */ 302 #define ASFR_ME 0x100000000LL 303 #define ASFR_PRIV 0x080000000LL 304 #define ASFR_ISAP 0x040000000LL 305 #define ASFR_ETP 0x020000000LL 306 #define ASFR_IVUE 0x010000000LL 307 #define ASFR_TO 0x008000000LL 308 #define ASFR_BERR 0x004000000LL 309 #define ASFR_LDP 0x002000000LL 310 #define ASFR_CP 0x001000000LL 311 #define ASFR_WP 0x000800000LL 312 #define ASFR_EDP 0x000400000LL 313 #define ASFR_UE 0x000200000LL 314 #define ASFR_CE 0x000100000LL 315 #define ASFR_ETS 0x0000f0000LL 316 #define ASFT_P_SYND 0x00000ffffLL 317 318 #define AFSR_BITS "\177\20" \ 319 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 320 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 321 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 322 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 323 324 /* 325 * Here's the spitfire TSB control register bits. 326 * 327 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 328 */ 329 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 330 #define TSB_SIZE_1K 0x01 331 #define TSB_SIZE_2K 0x02 332 #define TSB_SIZE_4K 0x03 333 #define TSB_SIZE_8K 0x04 334 #define TSB_SIZE_16K 0x05 335 #define TSB_SIZE_32K 0x06 336 #define TSB_SIZE_64K 0x07 337 #define TSB_SPLIT 0x1000 338 #define TSB_BASE 0xffffffffffffe000 339 340 /* TLB Tag Access bits */ 341 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 342 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 343 344 /* 345 * TLB demap registers. TTEs are defined in v9pte.h 346 * 347 * Use the address space to select between IMMU and DMMU. 348 * The address of the register selects which context register 349 * to read the ASI from. 350 * 351 * The data stored in the register is interpreted as the VA to 352 * use. The DEMAP_CTX_<> registers ignore the address and demap the 353 * entire ASI. 354 * 355 */ 356 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 357 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 358 359 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 360 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 361 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 362 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 363 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 364 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 365 366 /* 367 * Interrupt registers. This really gets hairy. 368 */ 369 370 /* IRSR -- Interrupt Receive Status Ragister */ 371 #define ASI_IRSR 0x49 372 #define IRSR 0x00 373 #define IRSR_BUSY 0x020 374 #define IRSR_MID(x) (x&0x1f) 375 376 /* IRDR -- Interrupt Receive Data Registers */ 377 #define ASI_IRDR 0x7f 378 #define IRDR_0H 0x40 379 #define IRDR_0L 0x48 /* unimplemented */ 380 #define IRDR_1H 0x50 381 #define IRDR_1L 0x58 /* unimplemented */ 382 #define IRDR_2H 0x60 383 #define IRDR_2L 0x68 /* unimplemented */ 384 #define IRDR_3H 0x70 /* unimplemented */ 385 #define IRDR_3L 0x78 /* unimplemented */ 386 387 /* SOFTINT ASRs */ 388 #define SET_SOFTINT %asr20 /* Sets these bits */ 389 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 390 #define SOFTINT %asr22 /* Reads the register */ 391 #define TICK_CMPR %asr23 392 393 #define TICK_INT 0x01 /* level-14 clock tick */ 394 #define SOFTINT1 (0x1<<1) 395 #define SOFTINT2 (0x1<<2) 396 #define SOFTINT3 (0x1<<3) 397 #define SOFTINT4 (0x1<<4) 398 #define SOFTINT5 (0x1<<5) 399 #define SOFTINT6 (0x1<<6) 400 #define SOFTINT7 (0x1<<7) 401 #define SOFTINT8 (0x1<<8) 402 #define SOFTINT9 (0x1<<9) 403 #define SOFTINT10 (0x1<<10) 404 #define SOFTINT11 (0x1<<11) 405 #define SOFTINT12 (0x1<<12) 406 #define SOFTINT13 (0x1<<13) 407 #define SOFTINT14 (0x1<<14) 408 #define SOFTINT15 (0x1<<15) 409 410 /* Interrupt Dispatch -- usually reserved for cross-calls */ 411 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 412 #define IDSR 0x00 413 #define IDSR_NACK 0x02 414 #define IDSR_BUSY 0x01 415 416 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 417 418 /* Interrupt delivery initiation */ 419 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 420 421 #define IDDR_0H 0x40 /* Store data to send in these regs */ 422 #define IDDR_0L 0x48 /* unimplemented */ 423 #define IDDR_1H 0x50 424 #define IDDR_1L 0x58 /* unimplemented */ 425 #define IDDR_2H 0x60 426 #define IDDR_2L 0x68 /* unimplemented */ 427 #define IDDR_3H 0x70 /* unimplemented */ 428 #define IDDR_3L 0x78 /* unimplemented */ 429 430 /* 431 * Error registers 432 */ 433 434 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 435 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 436 #define AFAR 0x00 437 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 438 #define AFSR 0x00 439 440 #define ASI_P_EER 0x4b /* Error enable register */ 441 #define P_EER 0x00 442 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 443 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 444 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 445 446 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 447 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 448 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 449 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 450 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 451 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 452 453 454 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 455 456 #ifndef _LOCORE 457 /* 458 * GCC __asm constructs for doing assembly stuff. 459 */ 460 461 /* 462 * ``Routines'' to load and store from/to alternate address space. 463 * The location can be a variable, the asi value (address space indicator) 464 * must be a constant. 465 * 466 * N.B.: You can put as many special functions here as you like, since 467 * they cost no kernel space or time if they are not used. 468 * 469 * These were static inline functions, but gcc screws up the constraints 470 * on the address space identifiers (the "n"umeric value part) because 471 * it inlines too late, so we have to use the funny valued-macro syntax. 472 */ 473 474 /* 475 * Apparently the definition of bypass ASIs is that they all use the 476 * D$ so we need to flush the D$ to make sure we don't get data pollution. 477 */ 478 479 #ifdef __arch64__ 480 static __inline u_char 481 lduba(paddr_t loc, int asi) 482 { 483 register unsigned int _lduba_v; 484 485 __asm volatile( 486 "wr %2, %%g0, %%asi; " 487 "lduba [%1]%%asi, %0 " 488 : "=r" (_lduba_v) 489 : "r" ((unsigned long)(loc)), "r" (asi)); 490 return (_lduba_v); 491 } 492 #else 493 static __inline u_char 494 lduba(paddr_t loc, int asi) 495 { 496 register unsigned int _lduba_v, _loc_hi, _pstate; 497 498 _loc_hi = (((uint64_t)loc)>>32); 499 if (PHYS_ASI(asi)) { 500 __asm volatile( 501 "wr %4,%%g0,%%asi; " 502 "sllx %3,32,%0; " 503 "rdpr %%pstate,%1; " 504 "or %0,%2,%0; " 505 "wrpr %1,8,%%pstate; " 506 "membar #Sync; " 507 "lduba [%0]%%asi,%0; " 508 "wrpr %1,0,%%pstate; " 509 "membar #Sync; " 510 "wr %%g0, 0x82, %%asi " 511 : "=&r" (_lduba_v), "=&r" (_pstate) 512 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 513 } else { 514 __asm volatile( 515 "wr %3,%%g0,%%asi; " 516 "sllx %2,32,%0; " 517 "or %0,%1,%0; " 518 "lduba [%0]%%asi,%0; " 519 "wr %%g0, 0x82, %%asi " 520 : "=&r" (_lduba_v) 521 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 522 } 523 return (_lduba_v); 524 } 525 #endif 526 527 #ifdef __arch64__ 528 /* load half-word from alternate address space */ 529 static __inline u_short 530 lduha(paddr_t loc, int asi) 531 { 532 register unsigned int _lduha_v; 533 534 __asm volatile( 535 "wr %2, %%g0, %%asi; " 536 "lduha [%1]%%asi, %0 " 537 : "=r" (_lduha_v) 538 : "r" ((unsigned long)(loc)), "r" (asi)); 539 return (_lduha_v); 540 } 541 #else 542 /* load half-word from alternate address space */ 543 static __inline u_short 544 lduha(paddr_t loc, int asi) { 545 register unsigned int _lduha_v, _loc_hi, _pstate; 546 547 _loc_hi = (((uint64_t)loc)>>32); 548 549 if (PHYS_ASI(asi)) { 550 __asm volatile( 551 "wr %4,%%g0,%%asi; " 552 "sllx %3,32,%0; " 553 "rdpr %%pstate,%1; " 554 "wrpr %1,8,%%pstate; " 555 "or %0,%2,%0; " 556 "membar #Sync; " 557 "lduha [%0]%%asi,%0; " 558 "wrpr %1,0,%%pstate; " 559 "membar #Sync; " 560 "wr %%g0, 0x82, %%asi " 561 : "=&r" (_lduha_v), "=&r" (_pstate) 562 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 563 } else { 564 __asm volatile( 565 "wr %3,%%g0,%%asi; " 566 "sllx %2,32,%0; " 567 "or %0,%1,%0; " 568 "lduha [%0]%%asi,%0; " 569 "wr %%g0, 0x82, %%asi " 570 : "=&r" (_lduha_v) 571 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 572 } 573 return (_lduha_v); 574 } 575 #endif 576 577 578 #ifdef __arch64__ 579 /* load unsigned int from alternate address space */ 580 static __inline u_int 581 lda(paddr_t loc, int asi) 582 { 583 register unsigned int _lda_v; 584 585 __asm volatile( 586 "wr %2,%%g0,%%asi; " 587 "lda [%1]%%asi,%0 " 588 : "=r" (_lda_v) 589 : "r" ((unsigned long)(loc)), "r" (asi)); 590 return (_lda_v); 591 } 592 593 /* load signed int from alternate address space */ 594 static __inline int 595 ldswa(paddr_t loc, int asi) 596 { 597 register int _lda_v; 598 599 __asm volatile( 600 "wr %2,%%g0,%%asi; " 601 "ldswa [%1]%%asi,%0; " 602 : "=r" (_lda_v) 603 : "r" ((unsigned long)(loc)), "r" (asi)); 604 return (_lda_v); 605 } 606 #else /* __arch64__ */ 607 /* load unsigned int from alternate address space */ 608 static __inline u_int 609 lda(paddr_t loc, int asi) 610 { 611 register unsigned int _lda_v, _loc_hi, _pstate; 612 613 _loc_hi = (((uint64_t)loc)>>32); 614 if (PHYS_ASI(asi)) { 615 __asm volatile( 616 "wr %4,%%g0,%%asi; " 617 "rdpr %%pstate,%1; " 618 "sllx %3,32,%0; " 619 "wrpr %1,8,%%pstate; " 620 "or %0,%2,%0; " 621 "membar #Sync; " 622 "lda [%0]%%asi,%0; " 623 "wrpr %1,0,%%pstate; " 624 "membar #Sync; " 625 "wr %%g0, 0x82, %%asi " 626 : "=&r" (_lda_v), "=&r" (_pstate) 627 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 628 } else { 629 __asm volatile( 630 "wr %3,%%g0,%%asi; " 631 "sllx %2,32,%0; " 632 "or %0,%1,%0; " 633 "lda [%0]%%asi,%0; " 634 "wr %%g0, 0x82, %%asi " 635 : "=&r" (_lda_v) 636 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 637 } 638 return (_lda_v); 639 } 640 641 /* load signed int from alternate address space */ 642 static __inline int 643 ldswa(paddr_t loc, int asi) 644 { 645 register int _lda_v, _loc_hi, _pstate; 646 647 _loc_hi = (((uint64_t)loc)>>32); 648 if (PHYS_ASI(asi)) { 649 __asm volatile( 650 "wr %4,%%g0,%%asi; " 651 "rdpr %%pstate,%1; " 652 "wrpr %1,8,%%pstate; " 653 "sllx %3,32,%0; " 654 " or %0,%2,%0; " 655 "membar #Sync; " 656 "ldswa [%0]%%asi,%0; " 657 "wrpr %1,0,%%pstate; " 658 "membar #Sync; " 659 "wr %%g0, 0x82, %%asi " 660 : "=&r" (_lda_v), "=&r" (_pstate) 661 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 662 } else { 663 __asm volatile( 664 "wr %3,%%g0,%%asi; " 665 "sllx %2,32,%0; " 666 "or %0,%1,%0; " 667 "ldswa [%0]%%asi,%0; " 668 "wr %%g0, 0x82, %%asi " 669 : "=&r" (_lda_v) 670 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 671 } 672 return (_lda_v); 673 } 674 #endif /* __arch64__ */ 675 676 #ifdef __arch64__ 677 /* load 64-bit int from alternate address space -- these should never be used */ 678 static __inline uint64_t 679 ldda(paddr_t loc, int asi) 680 { 681 register long long _lda_v; 682 683 __asm volatile( 684 "wr %2,%%g0,%%asi; " 685 "ldda [%1]%%asi,%0 " 686 : "=r" (_lda_v) 687 : "r" ((unsigned long)(loc)), "r" (asi)); 688 return (_lda_v); 689 } 690 #else 691 /* load 64-bit int from alternate address space */ 692 static __inline uint64_t 693 ldda(paddr_t loc, int asi) 694 { 695 register long long _lda_v, _loc_hi, _pstate; 696 697 _loc_hi = (((uint64_t)loc)>>32); 698 if (PHYS_ASI(asi)) { 699 __asm volatile( 700 "wr %4,%%g0,%%asi; " 701 "rdpr %%pstate,%1; " 702 "wrpr %1,8,%%pstate; " 703 "sllx %3,32,%0; " 704 "or %0,%2,%0; " 705 "membar #Sync; " 706 "ldda [%0]%%asi,%0; " 707 "wrpr %1,0,%%pstate; " 708 "membar #Sync; " 709 "wr %%g0, 0x82, %%asi " 710 : "=&r" (_lda_v), "=&r" (_pstate) 711 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 712 } else { 713 __asm volatile( 714 "wr %3,%%g0,%%asi; " 715 "sllx %2,32,%0; " 716 " or %0,%1,%0; " 717 "ldda [%0]%%asi,%0; " 718 "wr %%g0, 0x82, %%asi " 719 : "=&r" (_lda_v) 720 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 721 } 722 return (_lda_v); 723 } 724 #endif 725 726 727 #ifdef __arch64__ 728 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 729 static __inline uint64_t 730 ldxa(paddr_t loc, int asi) 731 { 732 register unsigned long _lda_v; 733 734 __asm volatile( 735 "wr %2,%%g0,%%asi; " 736 "ldxa [%1]%%asi,%0 " 737 : "=r" (_lda_v) 738 : "r" ((unsigned long)(loc)), "r" (asi)); 739 return (_lda_v); 740 } 741 #else 742 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 743 static __inline uint64_t 744 ldxa(paddr_t loc, int asi) 745 { 746 register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; 747 748 _loc_hi = (((uint64_t)loc)>>32); 749 if (PHYS_ASI(asi)) { 750 __asm volatile( 751 "wr %4,%%g0,%%asi; " 752 "rdpr %%pstate,%1; " 753 "sllx %3,32,%0; " 754 "wrpr %1,8,%%pstate; " 755 "or %0, %2, %0; " 756 "membar #Sync; " 757 "ldxa [%0]%%asi,%0; " 758 "wrpr %1,0,%%pstate; " 759 "membar #Sync; " 760 "srlx %0, 32, %1; " 761 "srl %0, 0, %0; " 762 "wr %%g0, 0x82, %%asi " 763 : "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) 764 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 765 } else { 766 __asm volatile( 767 "wr %4,%%g0,%%asi; " 768 "sllx %3,32,%0; " 769 "or %0,%2,%0; " 770 "ldxa [%0]%%asi,%0; " 771 "srlx %0,32,%1; " 772 "srl %0, 0, %0; " 773 "wr %%g0, 0x82, %%asi " 774 : "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) 775 : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 776 } 777 return ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); 778 } 779 #endif 780 781 /* store byte to alternate address space */ 782 #ifdef __arch64__ 783 static __inline void 784 stba(paddr_t loc, int asi, u_char value) 785 { 786 __asm volatile( 787 "wr %2, %%g0, %%asi; " 788 "stba %0, [%1]%%asi " 789 : : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (asi)); 790 } 791 #else 792 static __inline void 793 stba(paddr_t loc, int asi, u_char value) 794 { 795 register int _loc_hi, _pstate; 796 797 _loc_hi = (((uint64_t)loc)>>32); 798 if (PHYS_ASI(asi)) { 799 __asm volatile( 800 "wr %5,%%g0,%%asi; " 801 "sllx %4,32,%0; " 802 "rdpr %%pstate,%1; " 803 "or %3,%0,%0; " 804 "wrpr %1,8,%%pstate; " 805 "stba %2,[%0]%%asi; " 806 "wrpr %1,0,%%pstate; " 807 "membar #Sync; " 808 "wr %%g0, 0x82, %%asi " 809 : "=&r" (_loc_hi), "=&r" (_pstate) 810 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 811 } else { 812 __asm volatile( 813 "wr %4,%%g0,%%asi; " 814 "sllx %3,32,%0; " 815 "or %2,%0,%0; " 816 "stba %1,[%0]%%asi; " 817 "wr %%g0, 0x82, %%asi " 818 : "=&r" (_loc_hi) 819 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); 820 } 821 } 822 #endif 823 824 /* store half-word to alternate address space */ 825 #ifdef __arch64__ 826 static __inline void 827 stha(paddr_t loc, int asi, u_short value) 828 { 829 __asm volatile( 830 "wr %2,%%g0,%%asi; " 831 "stha %0,[%1]%%asi " 832 : : "r" ((int)(value)), "r" ((unsigned long)(loc)), 833 "r" (asi) : "memory"); 834 } 835 #else 836 static __inline void 837 stha(paddr_t loc, int asi, u_short value) 838 { 839 register int _loc_hi, _pstate; 840 841 _loc_hi = (((uint64_t)loc)>>32); 842 if (PHYS_ASI(asi)) { 843 __asm volatile( 844 "wr %5,%%g0,%%asi; " 845 "sllx %4,32,%0; " 846 "rdpr %%pstate,%1; " 847 "or %3,%0,%0; " 848 "wrpr %1,8,%%pstate; " 849 "stha %2,[%0]%%asi; " 850 "wrpr %1,0,%%pstate; " 851 "membar #Sync; " 852 "wr %%g0, 0x82, %%asi " 853 : "=&r" (_loc_hi), "=&r" (_pstate) 854 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 855 : "memory"); 856 } else { 857 __asm volatile( 858 "wr %4,%%g0,%%asi; " 859 "sllx %3,32,%0; " 860 "or %2,%0,%0; " 861 "stha %1,[%0]%%asi; " 862 "wr %%g0, 0x82, %%asi " 863 : "=&r" (_loc_hi) 864 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 865 : "memory"); 866 } 867 } 868 #endif 869 870 871 /* store int to alternate address space */ 872 #ifdef __arch64__ 873 static __inline void 874 sta(paddr_t loc, int asi, u_int value) 875 { 876 __asm volatile( 877 "wr %2,%%g0,%%asi; " 878 "sta %0,[%1]%%asi " 879 : : "r" ((int)(value)), "r" ((unsigned long)(loc)), 880 "r" (asi) : "memory"); 881 } 882 #else 883 static __inline void 884 sta(paddr_t loc, int asi, u_int value) 885 { 886 register int _loc_hi, _pstate; 887 888 _loc_hi = (((uint64_t)loc)>>32); 889 if (PHYS_ASI(asi)) { 890 __asm volatile( 891 "wr %5,%%g0,%%asi; " 892 "sllx %4,32,%0; " 893 "rdpr %%pstate,%1; " 894 "or %3,%0,%0; " 895 "wrpr %1,8,%%pstate; " 896 "sta %2,[%0]%%asi; " 897 "wrpr %1,0,%%pstate; " 898 "membar #Sync; " 899 "wr %%g0, 0x82, %%asi " 900 : "=&r" (_loc_hi), "=&r" (_pstate) 901 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 902 : "memory"); 903 } else { 904 __asm volatile( 905 "wr %4,%%g0,%%asi; " 906 "sllx %3,32,%0; " 907 "or %2,%0,%0; " 908 "sta %1,[%0]%%asi; " 909 "wr %%g0, 0x82, %%asi " 910 : "=&r" (_loc_hi) 911 : "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 912 : "memory"); 913 } 914 } 915 #endif 916 917 /* store 64-bit int to alternate address space */ 918 #ifdef __arch64__ 919 static __inline void 920 stda(paddr_t loc, int asi, uint64_t value) 921 { 922 __asm volatile( 923 "wr %2,%%g0,%%asi; " 924 "stda %0,[%1]%%asi " 925 : : "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (asi) 926 : "memory"); 927 } 928 #else 929 static __inline void 930 stda(paddr_t loc, int asi, uint64_t value) 931 { 932 register int _loc_hi, _pstate; 933 934 _loc_hi = (((uint64_t)loc)>>32); 935 if (PHYS_ASI(asi)) { 936 __asm volatile( 937 "wr %5,%%g0,%%asi; " 938 "sllx %4,32,%0; " 939 "rdpr %%pstate,%1; " 940 "or %3,%0,%0; " 941 "wrpr %1,8,%%pstate; " 942 "stda %2,[%0]%%asi; " 943 "wrpr %1,0,%%pstate; " 944 "membar #Sync; " 945 "wr %%g0, 0x82, %%asi " 946 : "=&r" (_loc_hi), "=&r" (_pstate) 947 : "r" ((long long)(value)), "r" ((unsigned long)(loc)), 948 "r" (_loc_hi), "r" (asi) 949 : "memory"); 950 } else { 951 __asm volatile( 952 "wr %4,%%g0,%%asi; " 953 "sllx %3,32,%0; " 954 "or %2,%0,%0; " 955 "stda %1,[%0]%%asi; " 956 "wr %%g0, 0x82, %%asi " 957 : "=&r" (_loc_hi) 958 : "r" ((long long)(value)), "r" ((unsigned long)(loc)), 959 "r" (_loc_hi), "r" (asi) 960 : "memory"); 961 } 962 } 963 #endif 964 965 /* set dmmu secondary context */ 966 static __inline void 967 dmmu_set_secondary_context(uint ctx) 968 { 969 __asm volatile( 970 "stxa %0,[%1]%2; " 971 "membar #Sync " 972 : : "r" (ctx), 973 "r" (CTX_SECONDARY), "n" (ASI_DMMU) 974 : "memory"); 975 } 976 977 #ifdef __arch64__ 978 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 979 static __inline void 980 stxa(paddr_t loc, int asi, uint64_t value) 981 { 982 __asm volatile( 983 "wr %2,%%g0,%%asi; " 984 "stxa %0,[%1]%%asi " 985 : : "r" ((unsigned long)(value)), 986 "r" ((unsigned long)(loc)), "r" (asi) 987 : "memory"); 988 } 989 #else 990 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 991 static __inline void 992 stxa(paddr_t loc, int asi, uint64_t value) 993 { 994 int _stxa_lo, _stxa_hi, _loc_hi; 995 996 _stxa_lo = value; 997 _stxa_hi = ((uint64_t)value)>>32; 998 _loc_hi = (((uint64_t)loc)>>32); 999 1000 if (PHYS_ASI(asi)) { 1001 __asm volatile( 1002 "wr %7,%%g0,%%asi; " 1003 "sllx %4,32,%1; " 1004 "sllx %6,32,%0; " 1005 "or %1,%3,%1; " 1006 "rdpr %%pstate,%2; " 1007 "or %0,%5,%0; " 1008 "wrpr %2,8,%%pstate; " 1009 "stxa %1,[%0]%%asi; " 1010 "wrpr %2,0,%%pstate; " 1011 "membar #Sync; " 1012 "wr %%g0, 0x82, %%asi " 1013 : "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)) 1014 : "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 1015 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 1016 : "memory"); 1017 } else { 1018 __asm volatile( 1019 "wr %6,%%g0,%%asi; " 1020 "sllx %3,32,%1; " 1021 "sllx %5,32,%0; " 1022 "or %1,%2,%1; " 1023 "or %0,%4,%0; " 1024 "stxa %1,[%0]%%asi; " 1025 "wr %%g0, 0x82, %%asi " 1026 : "=&r" (_loc_hi), "=&r" (_stxa_hi) 1027 : "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), 1028 "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi) 1029 : "memory"); 1030 } 1031 } 1032 #endif 1033 1034 #ifdef __arch64__ 1035 /* native store 32-bit int to alternate address space w/64-bit compiler*/ 1036 static __inline uint32_t 1037 casa(paddr_t loc, int asi, uint32_t value, uint32_t oldvalue) 1038 { 1039 __asm volatile( 1040 "wr %3,%%g0,%%asi; " 1041 "casa [%1]%%asi,%2,%0 " 1042 : "+r" (value) 1043 : "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) 1044 : "memory"); 1045 return (value); 1046 } 1047 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 1048 static __inline uint64_t 1049 casxa(paddr_t loc, int asi, uint64_t value, uint64_t oldvalue) 1050 { 1051 __asm volatile( 1052 "wr %3,%%g0,%%asi; " 1053 "casxa [%1]%%asi,%2,%0 " 1054 : "+r" (value) 1055 : "r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) 1056 : "memory"); 1057 return (value); 1058 } 1059 #else 1060 #if 0 1061 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 1062 static __inline uint64_t 1063 casxa(paddr_t loc, int asi, uint64_t value, uint64_t oldvalue) 1064 { 1065 int _casxa_lo, _casxa_hi, _loc_hi, _oval_hi; 1066 1067 _casxa_lo = value; 1068 _casxa_hi = ((uint64_t)value)>>32; 1069 _oval_hi = ((uint64_t)oldvalue)>>32; 1070 _loc_hi = (((uint64_t)loc)>>32); 1071 1072 #ifdef __notyet 1073 /* 1074 * gcc cannot handle this since it thinks it has >10 asm operands. 1075 */ 1076 if (PHYS_ASI(asi)) { 1077 __asm volatile( 1078 "wr %6,%%g0,%%asi; " 1079 "sllx %1,32,%1; " 1080 "rdpr %%pstate,%2; " 1081 "sllx %0,32,%0; " 1082 "or %1,%2,%1; " 1083 "sllx %3,32,%3; " 1084 "or %0,%4,%0; " 1085 "or %3,%5,%3; " 1086 "wrpr %2,8,%%pstate; " 1087 "casxa [%0]%%asi,%3,%1; " 1088 "wrpr %2,0,%%pstate; " 1089 "andn %0,0x1f,%3; " 1090 "membar #Sync; " 1091 "sll %1,0,%2; " 1092 "srax %1,32,%1; " 1093 "wr %%g0, 0x82, %%asi " 1094 : "+r" (_loc_hi), "+r" (_casxa_hi), "+r" (_casxa_lo), "+r" (_oval_hi) 1095 : "r" ((unsigned long)(loc)), "r" ((unsigned int)(oldvalue)), 1096 "r" (asi) 1097 : "memory"); 1098 } else { 1099 __asm volatile( 1100 "wr %7,%%g0,%%asi; " 1101 "sllx %1,32,%1; " 1102 "sllx %5,32,%0; " 1103 "or %1,%2,%1; " 1104 "sllx %3,32,%2; " 1105 "or %0,%4,%0; " 1106 "or %2,%4,%2; " 1107 "casxa [%0]%%asi,%2,%1; " 1108 "sll %1,0,%2; " 1109 "srax %o1,32,%o1; " 1110 "wr %%g0, 0x82, %%asi " 1111 : "=&r" (_loc_hi), "+r" (_casxa_hi), "+r" (_casxa_lo) 1112 : "r" ((int)(_oval_hi)), "r" ((int)(oldvalue)), 1113 "r" ((unsigned long)(loc)), "r" (_loc_hi), 1114 "r" (asi) 1115 : "memory"); 1116 } 1117 #endif 1118 return (((uint64_t)_casxa_hi<<32)|(uint64_t)_casxa_lo); 1119 } 1120 #endif 1121 #endif 1122 1123 /* flush address from data cache */ 1124 #define flush(loc) ({ \ 1125 __asm volatile("flush %0" : : \ 1126 "r" ((unsigned long)(loc))); \ 1127 }) 1128 1129 /* Flush a D$ line */ 1130 #if 0 1131 #define flushline(loc) ({ \ 1132 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 1133 membar_sync(); \ 1134 }) 1135 #endif 1136 1137 /* The following two enable or disable the dcache in the LSU control register */ 1138 #define dcenable() ({ \ 1139 int res; \ 1140 __asm volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 1141 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 1142 }) 1143 #define dcdisable() ({ \ 1144 int res; \ 1145 __asm volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 1146 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 1147 }) 1148 1149 /* 1150 * SPARC V9 memory barrier instructions. 1151 */ 1152 /* Make all stores complete before next store */ 1153 #define membar_storestore() __asm volatile("membar #StoreStore" : :) 1154 /* Make all loads complete before next store */ 1155 #define membar_loadstore() __asm volatile("membar #LoadStore" : :) 1156 /* Make all stores complete before next load */ 1157 #define membar_storeload() __asm volatile("membar #StoreLoad" : :) 1158 /* Make all loads complete before next load */ 1159 #define membar_loadload() __asm volatile("membar #LoadLoad" : :) 1160 /* Complete all outstanding memory operations and exceptions */ 1161 #define membar_sync() __asm volatile("membar #Sync" : :) 1162 /* Complete all outstanding memory operations */ 1163 #define membar_memissue() __asm volatile("membar #MemIssue" : :) 1164 /* Complete all outstanding stores before any new loads */ 1165 #define membar_lookaside() __asm volatile("membar #Lookaside" : :) 1166 1167 #define membar_load() __asm volatile("membar #LoadLoad | #LoadStore" : :) 1168 #define membar_store() __asm volatile("membar #LoadStore | #StoreStore" : :) 1169 1170 #endif 1171 1172 #endif /* _SPARC_CTLREG_H_ */ 1173
Indexes created Mon Sep 29 21:09:56 GMT 2025