ctlreg.h revision 1.60
1 /* $NetBSD: ctlreg.h,v 1.60 2013/12/16 20:17:35 palle Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _SPARC_CTLREG_H_ 27 #define _SPARC_CTLREG_H_ 28 29 /* 30 * Sun 4u control registers. (includes address space definitions 31 * and some registers in control space). 32 */ 33 34 /* 35 * The Alternate address spaces. 36 * 37 * 0x00-0x7f are privileged 38 * 0x80-0xff can be used by users 39 */ 40 41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 42 43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 45 46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 48 49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 51 52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */ 54 55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 57 58 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 59 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 60 61 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 62 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 63 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 64 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 65 66 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */ 67 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */ 68 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */ 69 70 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 71 72 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 73 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 74 75 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 76 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 77 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 78 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 79 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 80 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 81 82 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to I-cache data RAM */ 83 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to I-cache tag RAM */ 84 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush I-cache page using primary context */ 85 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush I-cache page using secondary context */ 86 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush I-cache context using primary context */ 87 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush I-cache context using secondary context */ 88 89 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 90 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 91 92 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 93 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 94 95 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 96 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 97 98 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 99 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 100 101 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 102 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 103 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 104 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 105 106 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 107 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 108 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 109 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 110 111 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 112 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 113 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 114 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 115 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 116 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 117 118 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 119 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 120 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 121 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 122 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 123 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 124 125 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 126 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 127 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 128 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 129 130 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 131 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 132 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 133 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 134 135 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 136 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 137 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 138 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 139 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 140 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 141 142 143 /* 144 * These are the shorter names used by Solaris 145 */ 146 147 #define ASI_N ASI_NUCLEUS 148 #define ASI_NL ASI_NUCLEUS_LITTLE 149 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 150 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 151 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 152 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 153 #define ASI_P ASI_PRIMARY 154 #define ASI_S ASI_SECONDARY 155 #define ASI_PNF ASI_PRIMARY_NOFAULT 156 #define ASI_SNF ASI_SECONDARY_NOFAULT 157 #define ASI_PL ASI_PRIMARY_LITTLE 158 #define ASI_SL ASI_SECONDARY_LITTLE 159 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 160 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 161 #define ASI_FL8_P ASI_FL8_PRIMARY 162 #define ASI_FL8_S ASI_FL8_SECONDARY 163 #define ASI_FL16_P ASI_FL16_PRIMARY 164 #define ASI_FL16_S ASI_FL16_SECONDARY 165 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 166 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 167 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 168 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 169 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 170 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 171 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 172 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 173 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 174 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 175 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 176 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 177 #define ASI_BLK_P ASI_BLOCK_PRIMARY 178 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 179 #define ASI_BLK_S ASI_BLOCK_SECONDARY 180 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 181 182 /* Alternative spellings */ 183 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 184 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 185 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 186 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 187 188 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 189 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 190 191 /* 192 * The following are 4u control registers 193 */ 194 195 /* Get the CPU's UPAID */ 196 #define UPA_CR_MID_SHIFT (17) 197 #define UPA_CR_MID_SIZE (5) 198 #define UPA_CR_MID_MASK \ 199 (((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT) 200 201 #define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1)) 202 203 #ifdef _LOCORE 204 205 #define UPA_GET_MID(r1) \ 206 ldxa [%g0] ASI_MID_REG, r1 ; \ 207 srlx r1, UPA_CR_MID_SHIFT, r1 ; \ 208 and r1, (1 << UPA_CR_MID_SIZE) - 1, r1 209 210 #else 211 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 212 #endif 213 214 /* Get the CPU's Fireplane agent ID */ 215 #define FIREPLANE_CR_AID(x) (((x) >> 17) & 0x3ff) 216 #define CPU_FIREPLANEID FIREPLANE_CR_AID(ldxa(0, ASI_MID_REG)) 217 218 /* Get the CPU's Jupiter Bus interrupt target ID */ 219 #define JUPITER_CR_ITID(x) ((x) & 0x3ff) 220 #define CPU_JUPITERID JUPITER_CR_ITID(ldxa(0, ASI_MID_REG)) 221 222 /* 223 * [4u] MMU and Cache Control Register (MCCR) 224 * use ASI = 0x45 225 */ 226 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 227 #define MCCR 0x00 228 229 /* MCCR Bits and their meanings */ 230 #define MCCR_DMMU_EN 0x08 231 #define MCCR_IMMU_EN 0x04 232 #define MCCR_DCACHE_EN 0x02 233 #define MCCR_ICACHE_EN 0x01 234 #define MCCR_RAW_EN 0x400000000000 235 236 237 /* 238 * MMU control registers 239 */ 240 241 /* Choose an MMU */ 242 #define ASI_DMMU 0x58 243 #define ASI_IMMU 0x50 244 245 /* Other assorted MMU ASIs */ 246 #define ASI_IMMU_8KPTR 0x51 247 #define ASI_IMMU_64KPTR 0x52 248 #define ASI_IMMU_DATA_IN 0x54 249 #define ASI_IMMU_TLB_DATA 0x55 250 #define ASI_IMMU_TLB_TAG 0x56 251 #define ASI_DMMU_8KPTR 0x59 252 #define ASI_DMMU_64KPTR 0x5a 253 #define ASI_DMMU_DATA_IN 0x5c 254 #define ASI_DMMU_TLB_DATA 0x5d 255 #define ASI_DMMU_TLB_TAG 0x5e 256 257 /* 258 * The following are the control registers 259 * They work on both MMUs unless noted. 260 * III = cheetah only 261 * 262 * Register contents are defined later on individual registers. 263 */ 264 #define TSB_TAG_TARGET 0x0 265 #define TLB_DATA_IN 0x0 266 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 267 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 268 #define SFSR 0x18 269 #define SFAR 0x20 /* fault address -- DMMU only */ 270 #define TSB 0x28 271 #define TLB_TAG_ACCESS 0x30 272 #define VIRTUAL_WATCHPOINT 0x38 273 #define PHYSICAL_WATCHPOINT 0x40 274 #define TSB_PEXT 0x48 /* III primary ext */ 275 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */ 276 #define TSB_NEXT 0x58 /* III nucleus ext */ 277 278 /* Tag Target bits */ 279 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 280 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 281 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 282 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 283 284 /* SFSR bits for both D_SFSR and I_SFSR */ 285 #define SFSR_ASI(x) ((x)>>16) 286 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 287 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 288 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 289 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 290 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 291 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 292 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 293 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 294 #define SFSR_CTXT(x) (((x)>>4)&0x3) 295 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 296 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 297 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 298 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 299 #define SFSR_W 0x00004 /* DMMU: attempted write */ 300 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 301 #define SFSR_FV 0x00001 /* Fault is valid */ 302 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \ 303 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 304 305 #define SFSR_BITS "\177\20" \ 306 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \ 307 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \ 308 "b\3W\0" "b\2OW\0" "b\1FV\0" 309 310 /* ASFR bits */ 311 #define ASFR_ME 0x100000000LL 312 #define ASFR_PRIV 0x080000000LL 313 #define ASFR_ISAP 0x040000000LL 314 #define ASFR_ETP 0x020000000LL 315 #define ASFR_IVUE 0x010000000LL 316 #define ASFR_TO 0x008000000LL 317 #define ASFR_BERR 0x004000000LL 318 #define ASFR_LDP 0x002000000LL 319 #define ASFR_CP 0x001000000LL 320 #define ASFR_WP 0x000800000LL 321 #define ASFR_EDP 0x000400000LL 322 #define ASFR_UE 0x000200000LL 323 #define ASFR_CE 0x000100000LL 324 #define ASFR_ETS 0x0000f0000LL 325 #define ASFT_P_SYND 0x00000ffffLL 326 327 #define AFSR_BITS "\177\20" \ 328 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 329 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 330 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 331 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 332 333 /* 334 * Here's the spitfire TSB control register bits. 335 * 336 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 337 */ 338 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 339 #define TSB_SIZE_1K 0x01 340 #define TSB_SIZE_2K 0x02 341 #define TSB_SIZE_4K 0x03 342 #define TSB_SIZE_8K 0x04 343 #define TSB_SIZE_16K 0x05 344 #define TSB_SIZE_32K 0x06 345 #define TSB_SIZE_64K 0x07 346 #define TSB_SPLIT 0x1000 347 #define TSB_BASE 0xffffffffffffe000 348 349 /* TLB Tag Access bits */ 350 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 351 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 352 353 /* 354 * TLB demap registers. TTEs are defined in v9pte.h 355 * 356 * Use the address space to select between IMMU and DMMU. 357 * The address of the register selects which context register 358 * to read the ASI from. 359 * 360 * The data stored in the register is interpreted as the VA to 361 * use. The DEMAP_CTX_<> registers ignore the address and demap the 362 * entire ASI. 363 * 364 */ 365 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 366 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 367 368 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 369 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 370 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 371 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 372 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 373 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 374 #define DEMAP_ALL ((0x08)<<4) /* Demap all non-locked TLB entries [USIII] */ 375 376 /* 377 * These define the sizes of the TLB in various CPUs. 378 * They're mostly not necessary except for diagnostic code. 379 */ 380 #define TLB_SIZE_SPITFIRE 64 381 #define TLB_SIZE_CHEETAH_I16 16 382 #define TLB_SIZE_CHEETAH_I128 128 383 #define TLB_SIZE_CHEETAH_D16 16 384 #define TLB_SIZE_CHEETAH_D512_0 512 385 #define TLB_SIZE_CHEETAH_D512_1 512 386 #define TLB_CHEETAH_I16 (0 << 16) 387 #define TLB_CHEETAH_I128 (2 << 16) 388 #define TLB_CHEETAH_D16 (0 << 16) 389 #define TLB_CHEETAH_D512_0 (2 << 16) 390 #define TLB_CHEETAH_D512_1 (3 << 16) 391 392 /* 393 * Interrupt registers. This really gets hairy. 394 */ 395 396 /* IRSR -- Interrupt Receive Status Ragister */ 397 #define ASI_IRSR 0x49 398 #define IRSR 0x00 399 #define IRSR_BUSY 0x020 400 #define IRSR_MID(x) (x&0x1f) 401 402 /* IRDR -- Interrupt Receive Data Registers */ 403 #define ASI_IRDR 0x7f 404 #define IRDR_0H 0x40 405 #define IRDR_0L 0x48 /* unimplemented */ 406 #define IRDR_1H 0x50 407 #define IRDR_1L 0x58 /* unimplemented */ 408 #define IRDR_2H 0x60 409 #define IRDR_2L 0x68 /* unimplemented */ 410 #define IRDR_3H 0x70 /* unimplemented */ 411 #define IRDR_3L 0x78 /* unimplemented */ 412 413 /* Interrupt Dispatch -- usually reserved for cross-calls */ 414 #define ASI_IDSR 0x48 /* Interrupt dispatch status reg */ 415 #define IDSR 0x00 416 #define IDSR_NACK 0x02 417 #define IDSR_BUSY 0x01 418 419 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 420 421 /* Interrupt delivery initiation */ 422 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 423 424 #define IDDR_0H 0x40 /* Store data to send in these regs */ 425 #define IDDR_0L 0x48 /* unimplemented */ 426 #define IDDR_1H 0x50 427 #define IDDR_1L 0x58 /* unimplemented */ 428 #define IDDR_2H 0x60 429 #define IDDR_2L 0x68 /* unimplemented */ 430 #define IDDR_3H 0x70 /* unimplemented */ 431 #define IDDR_3L 0x78 /* unimplemented */ 432 433 /* 434 * Error registers 435 */ 436 437 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 438 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 439 #define AFAR 0x00 440 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 441 #define AFSR 0x00 442 443 #define ASI_P_EER 0x4b /* Error enable register */ 444 #define P_EER 0x00 445 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 446 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 447 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 448 449 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 450 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 451 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 452 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 453 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 454 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 455 456 457 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 458 459 #ifndef _LOCORE 460 /* 461 * GCC __asm constructs for doing assembly stuff. 462 */ 463 464 /* 465 * ``Routines'' to load and store from/to alternate address space. 466 * The location can be a variable, the asi value (address space indicator) 467 * must be a constant. 468 * 469 * N.B.: You can put as many special functions here as you like, since 470 * they cost no kernel space or time if they are not used. 471 * 472 * These were static inline functions, but gcc screws up the constraints 473 * on the address space identifiers (the "n"umeric value part) because 474 * it inlines too late, so we have to use the funny valued-macro syntax. 475 */ 476 477 /* 478 * Apparently the definition of bypass ASIs is that they all use the 479 * D$ so we need to flush the D$ to make sure we don't get data pollution. 480 */ 481 482 #ifdef __arch64__ 483 484 /* 64-bit kernel, non-constant */ 485 #define SPARC64_LD_NONCONST(ld) \ 486 __asm volatile( \ 487 "wr %2,%%g0,%%asi; " \ 488 #ld " [%1]%%asi,%0 " \ 489 : "=r" (_v) \ 490 : "r" ((__uintptr_t)(loc)), "r" (asi)) 491 492 #if defined(__GNUC__) && defined(__OPTIMIZE__) 493 #define SPARC64_LD_DEF(ld, type, vtype) \ 494 static __inline type ld(paddr_t loc, int asi) \ 495 { \ 496 vtype _v; \ 497 if (__builtin_constant_p(asi)) \ 498 __asm volatile( \ 499 #ld " [%1]%2,%0 " \ 500 : "=r" (_v) \ 501 : "r" ((__uintptr_t)(loc)), "n" (asi)); \ 502 else \ 503 SPARC64_LD_NONCONST(ld); \ 504 return _v; \ 505 } 506 #else 507 #define SPARC64_LD_DEF(ld, type, vtype) \ 508 static __inline type ld(paddr_t loc, int asi) \ 509 { \ 510 vtype _v; \ 511 SPARC64_LD_NONCONST(ld); \ 512 return _v; \ 513 } 514 #endif 515 #define SPARC64_LD_DEF64(ld, type) SPARC64_LD_DEF(ld, type, uint64_t) 516 517 #else /* __arch64__ */ 518 519 /* 32-bit kernel, MMU bypass, non-constant */ 520 #define SPARC64_LD_PHYS_NONCONST(ld) \ 521 __asm volatile( \ 522 "clruw %2; " \ 523 "rdpr %%pstate,%1; " \ 524 "sllx %3,32,%0; " \ 525 "wrpr %1,8,%%pstate; " \ 526 "or %0,%2,%0; " \ 527 "wr %4,%%g0,%%asi; " \ 528 #ld " [%0]%%asi,%0; " \ 529 "wrpr %1,0,%%pstate " \ 530 : "=&r" (_v), "=&r" (_pstate) \ 531 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 532 /* 32-bit kernel, non-constant */ 533 #define SPARC64_LD_NONCONST(ld) \ 534 __asm volatile( \ 535 "wr %2,%%g0,%%asi; " \ 536 #ld " [%1]%%asi,%0 " \ 537 : "=&r" (_v) \ 538 : "r" ((uint32_t)(loc)), "r" (asi)) 539 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 540 #define SPARC64_LD_PHYS_NONCONST64(ld) \ 541 __asm volatile( \ 542 "clruw %2; " \ 543 "rdpr %%pstate,%1; " \ 544 "sllx %3,32,%0; " \ 545 "wrpr %1,8,%%pstate; " \ 546 "or %0,%2,%0; " \ 547 "wr %4,%%g0,%%asi; " \ 548 #ld " [%0]%%asi,%0; " \ 549 "wrpr %1,0,%%pstate; " \ 550 "srlx %0,32,%1; " \ 551 "srl %0,0,%0 " \ 552 : "=&r" (_vlo), "=&r" (_vhi) \ 553 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 554 /* 32-bit kernel, non-constant, 64-bit value */ 555 #define SPARC64_LD_NONCONST64(ld) \ 556 __asm volatile( \ 557 "wr %3,%%g0,%%asi; " \ 558 #ld " [%2]%%asi,%0; " \ 559 "srlx %0,32,%1; " \ 560 "srl %0,0,%0 " \ 561 : "=&r" (_vlo), "=&r" (_vhi) \ 562 : "r" ((uint32_t)(loc)), "r" (asi)) 563 564 #if defined(__GNUC__) && defined(__OPTIMIZE__) 565 #define SPARC64_LD_DEF(ld, type, vtype) \ 566 static __inline type ld(paddr_t loc, int asi) \ 567 { \ 568 vtype _v; \ 569 uint32_t _hi, _pstate; \ 570 if (PHYS_ASI(asi)) { \ 571 _hi = (uint64_t)(loc) >> 32; \ 572 if (__builtin_constant_p(asi)) \ 573 __asm volatile( \ 574 "clruw %2; " \ 575 "rdpr %%pstate,%1; " \ 576 "sllx %3,32,%0; " \ 577 "wrpr %1,8,%%pstate; " \ 578 "or %0,%2,%0; " \ 579 #ld " [%0]%4,%0; " \ 580 "wrpr %1,0,%%pstate; " \ 581 : "=&r" (_v), "=&r" (_pstate) \ 582 : "r" ((uint32_t)(loc)), "r" (_hi), \ 583 "n" (asi)); \ 584 else \ 585 SPARC64_LD_PHYS_NONCONST(ld); \ 586 } else { \ 587 if (__builtin_constant_p(asi)) \ 588 __asm volatile( \ 589 #ld " [%1]%2,%0 " \ 590 : "=&r" (_v) \ 591 : "r" ((uint32_t)(loc)), "n" (asi)); \ 592 else \ 593 SPARC64_LD_NONCONST(ld); \ 594 } \ 595 return _v; \ 596 } 597 #define SPARC64_LD_DEF64(ld, type) \ 598 static __inline type ld(paddr_t loc, int asi) \ 599 { \ 600 uint32_t _vlo, _vhi, _hi; \ 601 if (PHYS_ASI(asi)) { \ 602 _hi = (uint64_t)(loc) >> 32; \ 603 if (__builtin_constant_p(asi)) \ 604 __asm volatile( \ 605 "clruw %2; " \ 606 "rdpr %%pstate,%1; " \ 607 "sllx %3,32,%0; " \ 608 "wrpr %1,8,%%pstate; " \ 609 "or %0,%2,%0; " \ 610 #ld " [%0]%4,%0; " \ 611 "wrpr %1,0,%%pstate; " \ 612 "srlx %0,32,%1; " \ 613 "srl %0,0,%0 " \ 614 : "=&r" (_vlo), "=&r" (_vhi) \ 615 : "r" ((uint32_t)(loc)), "r" (_hi), \ 616 "n" (asi)); \ 617 else \ 618 SPARC64_LD_PHYS_NONCONST64(ld); \ 619 } else { \ 620 if (__builtin_constant_p(asi)) \ 621 __asm volatile( \ 622 #ld " [%2]%3,%0; " \ 623 "srlx %0,32,%1; " \ 624 "srl %0,0,%0 " \ 625 : "=&r" (_vlo), "=&r" (_vhi) \ 626 : "r" ((uint32_t)(loc)), "n" (asi)); \ 627 else \ 628 SPARC64_LD_NONCONST64(ld); \ 629 } \ 630 return ((uint64_t)_vhi << 32) | _vlo; \ 631 } 632 #else 633 #define SPARC64_LD_DEF(ld, type, vtype) \ 634 static __inline type ld(paddr_t loc, int asi) \ 635 { \ 636 vtype _v; \ 637 uint32_t _hi, _pstate; \ 638 if (PHYS_ASI(asi)) { \ 639 _hi = (uint64_t)(loc) >> 32; \ 640 SPARC64_LD_PHYS_NONCONST(ld); \ 641 } else \ 642 SPARC64_LD_NONCONST(ld); \ 643 return _v; \ 644 } 645 #define SPARC64_LD_DEF64(ld, type) \ 646 static __inline type ld(paddr_t loc, int asi) \ 647 { \ 648 uint32_t _vlo, _vhi, _hi; \ 649 if (PHYS_ASI(asi)) { \ 650 _hi = (uint64_t)(loc) >> 32; \ 651 SPARC64_LD_PHYS_NONCONST64(ld); \ 652 } else \ 653 SPARC64_LD_NONCONST64(ld); \ 654 return ((uint64_t)_vhi << 32) | _vlo; \ 655 } 656 #endif 657 658 #endif /* __arch64__ */ 659 660 /* load byte from alternate address space */ 661 SPARC64_LD_DEF(lduba, uint8_t, uint32_t) 662 /* load half-word from alternate address space */ 663 SPARC64_LD_DEF(lduha, uint16_t, uint32_t) 664 /* load unsigned int from alternate address space */ 665 SPARC64_LD_DEF(lda, uint32_t, uint32_t) 666 /* load unsigned word from alternate address space */ 667 SPARC64_LD_DEF(lduwa, uint32_t, uint32_t) 668 /* load signed int from alternate address space */ 669 SPARC64_LD_DEF(ldswa, int, int) 670 /* load 64-bit unsigned int from alternate address space */ 671 SPARC64_LD_DEF64(ldxa, uint64_t) 672 673 674 #ifdef __arch64__ 675 676 /* 64-bit kernel, non-constant */ 677 #define SPARC64_ST_NONCONST(st) \ 678 __asm volatile( \ 679 "wr %2,%%g0,%%asi; " \ 680 #st " %0,[%1]%%asi " \ 681 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 682 "r" (asi)) 683 684 #if defined(__GNUC__) && defined(__OPTIMIZE__) 685 #define SPARC64_ST_DEF(st, type) \ 686 static __inline void st(paddr_t loc, int asi, type value) \ 687 { \ 688 if (__builtin_constant_p(asi)) \ 689 __asm volatile( \ 690 #st " %0,[%1]%2 " \ 691 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 692 "n" (asi)); \ 693 else \ 694 SPARC64_ST_NONCONST(st); \ 695 } 696 #else 697 #define SPARC64_ST_DEF(st, type) \ 698 static __inline void st(paddr_t loc, int asi, type value) \ 699 { \ 700 SPARC64_ST_NONCONST(st); \ 701 } 702 #endif 703 #define SPARC64_ST_DEF64(st, type) SPARC64_ST_DEF(st, type) 704 705 #else /* __arch64__ */ 706 707 /* 32-bit kernel, MMU bypass, non-constant */ 708 #define SPARC64_ST_PHYS_NONCONST(st) \ 709 __asm volatile( \ 710 "clruw %3; " \ 711 "rdpr %%pstate,%1; " \ 712 "sllx %4,32,%0; " \ 713 "wrpr %1,8,%%pstate; " \ 714 "or %0,%3,%0; " \ 715 "wr %5,%%g0,%%asi; " \ 716 #st " %2,[%0]%%asi; " \ 717 "wrpr %1,0,%%pstate " \ 718 : "=&r" (_hi), "=&r" (_pstate) \ 719 : "r" (value), "r" ((uint32_t)(loc)), \ 720 "r" (_hi), "r" (asi)) 721 /* 32-bit kernel, non-constant */ 722 #define SPARC64_ST_NONCONST(st) \ 723 __asm volatile( \ 724 "wr %2,%%g0,%%asi; " \ 725 #st " %0,[%1]%%asi " \ 726 : : "r" (value), "r" ((uint32_t)(loc)), "r" (asi)) 727 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 728 #define SPARC64_ST_PHYS_NONCONST64(st) \ 729 __asm volatile( \ 730 "clruw %3; " \ 731 "clruw %5; " \ 732 "sllx %4,32,%1; " \ 733 "sllx %6,32,%0; " \ 734 "rdpr %%pstate,%2; " \ 735 "or %1,%3,%1; " \ 736 "wrpr %2,8,%%pstate; " \ 737 "or %0,%5,%0; " \ 738 "wr %7,%%g0,%%asi; " \ 739 #st " %1,[%0]%%asi; " \ 740 "wrpr %2,0,%%pstate " \ 741 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 742 : "r" (_vlo), "r" (_vhi), \ 743 "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 744 /* 32-bit kernel, non-constant, 64-bit value */ 745 #define SPARC64_ST_NONCONST64(st) \ 746 __asm volatile( \ 747 "clruw %1; " \ 748 "sllx %2,32,%0; " \ 749 "or %0,%1,%0; " \ 750 "wr %4,%%g0,%%asi; " \ 751 #st " %0,[%3]%%asi " \ 752 : "=&r" (_vhi) \ 753 : "r" (_vlo), "r" (_vhi), \ 754 "r" ((uint32_t)(loc)), "r" (asi)) 755 756 #if defined(__GNUC__) && defined(__OPTIMIZE__) 757 #define SPARC64_ST_DEF(st, type) \ 758 static __inline void st(paddr_t loc, int asi, type value) \ 759 { \ 760 uint32_t _hi, _pstate; \ 761 if (PHYS_ASI(asi)) { \ 762 _hi = (uint64_t)(loc) >> 32; \ 763 if (__builtin_constant_p(asi)) \ 764 __asm volatile( \ 765 "clruw %3; " \ 766 "sllx %4,32,%0; " \ 767 "rdpr %%pstate,%1; " \ 768 "or %0,%3,%0; " \ 769 "wrpr %1,8,%%pstate; " \ 770 #st " %2,[%0]%5; " \ 771 "wrpr %1,0,%%pstate " \ 772 : "=&r" (_hi), "=&r" (_pstate) \ 773 : "r" (value), "r" ((uint32_t)(loc)), \ 774 "r" (_hi), "n" (asi)); \ 775 else \ 776 SPARC64_ST_PHYS_NONCONST(st); \ 777 } else { \ 778 if (__builtin_constant_p(asi)) \ 779 __asm volatile( \ 780 #st " %0,[%1]%2 " \ 781 : : "r" (value), "r" ((uint32_t)(loc)), \ 782 "n" (asi)); \ 783 else \ 784 SPARC64_ST_NONCONST(st); \ 785 } \ 786 } 787 #define SPARC64_ST_DEF64(st, type) \ 788 static __inline void st(paddr_t loc, int asi, type value) \ 789 { \ 790 uint32_t _vlo, _vhi, _hi; \ 791 _vlo = value; \ 792 _vhi = (uint64_t)(value) >> 32; \ 793 if (PHYS_ASI(asi)) { \ 794 _hi = (uint64_t)(loc) >> 32; \ 795 if (__builtin_constant_p(asi)) \ 796 __asm volatile( \ 797 "clruw %3; " \ 798 "clruw %5; " \ 799 "sllx %4,32,%1; " \ 800 "sllx %6,32,%0; " \ 801 "rdpr %%pstate,%2; " \ 802 "or %1,%3,%1; " \ 803 "or %0,%5,%0; " \ 804 "wrpr %2,8,%%pstate; " \ 805 #st " %1,[%0]%7; " \ 806 "wrpr %2,0,%%pstate " \ 807 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 808 : "r" (_vlo), "r" (_vhi), \ 809 "r" ((uint32_t)(loc)), "r" (_hi), \ 810 "n" (asi)); \ 811 else \ 812 SPARC64_ST_PHYS_NONCONST64(st); \ 813 } else { \ 814 if (__builtin_constant_p(asi)) \ 815 __asm volatile( \ 816 "clruw %1; " \ 817 "sllx %2,32,%0; " \ 818 "or %0,%1,%0; " \ 819 #st " %0,[%3]%4 " \ 820 : "=&r" (_vhi) \ 821 : "r" (_vlo), "r" (_vhi), \ 822 "r" ((uint32_t)(loc)), "n" (asi)); \ 823 else \ 824 SPARC64_ST_NONCONST64(st); \ 825 } \ 826 } 827 #else 828 #define SPARC64_ST_DEF(st, type) \ 829 static __inline void st(paddr_t loc, int asi, type value) \ 830 { \ 831 uint32_t _hi, _pstate; \ 832 if (PHYS_ASI(asi)) { \ 833 _hi = (uint64_t)(loc) >> 32; \ 834 SPARC64_ST_PHYS_NONCONST(st); \ 835 } else \ 836 SPARC64_ST_NONCONST(st); \ 837 } 838 #define SPARC64_ST_DEF64(st, type) \ 839 static __inline void st(paddr_t loc, int asi, type value) \ 840 { \ 841 uint32_t _vlo, _vhi, _hi; \ 842 _vlo = value; \ 843 _vhi = (uint64_t)(value) >> 32; \ 844 if (PHYS_ASI(asi)) { \ 845 _hi = (uint64_t)(loc) >> 32; \ 846 SPARC64_ST_PHYS_NONCONST64(st); \ 847 } else \ 848 SPARC64_ST_NONCONST64(st); \ 849 } 850 #endif 851 852 #endif /* __arch64__ */ 853 854 /* store byte to alternate address space */ 855 SPARC64_ST_DEF(stba, uint8_t) 856 /* store half-word to alternate address space */ 857 SPARC64_ST_DEF(stha, uint16_t) 858 /* store unsigned int to alternate address space */ 859 SPARC64_ST_DEF(sta, uint32_t) 860 /* store 64-bit unsigned int to alternate address space */ 861 SPARC64_ST_DEF64(stxa, uint64_t) 862 863 864 /* set dmmu secondary context */ 865 static __inline void 866 dmmu_set_secondary_context(uint ctx) 867 { 868 __asm volatile( 869 "stxa %0,[%1]%2; " 870 "membar #Sync " 871 : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU) 872 : "memory"); 873 } 874 875 /* flush address from data cache */ 876 #define flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc))) 877 878 /* 879 * SPARC V9 memory barrier instructions. 880 */ 881 /* Make all stores complete before next store */ 882 #define membar_StoreStore() __asm volatile("membar #StoreStore" : :) 883 /* Make all loads complete before next store */ 884 #define membar_LoadStore() __asm volatile("membar #LoadStore" : :) 885 /* Make all stores complete before next load */ 886 #define membar_StoreLoad() __asm volatile("membar #StoreLoad" : :) 887 /* Make all loads complete before next load */ 888 #define membar_LoadLoad() __asm volatile("membar #LoadLoad" : :) 889 /* Complete all outstanding memory operations and exceptions */ 890 #define membar_Sync() __asm volatile("membar #Sync" : :) 891 /* Complete all outstanding memory operations */ 892 #define membar_MemIssue() __asm volatile("membar #MemIssue" : :) 893 /* Complete all outstanding stores before any new loads */ 894 #define membar_Lookaside() __asm volatile("membar #Lookaside" : :) 895 896 #define membar_Load() __asm volatile("membar #LoadLoad | #LoadStore" : :) 897 #define membar_Store() __asm volatile("membar #LoadStore | #StoreStore" : :) 898 899 #endif 900 901 #endif /* _SPARC_CTLREG_H_ */ 902
Indexes created Mon Sep 29 21:09:56 GMT 2025