ctlreg.h revision 1.61
1 /* $NetBSD: ctlreg.h,v 1.61 2014/07/16 19:53:18 palle Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _SPARC_CTLREG_H_ 27 #define _SPARC_CTLREG_H_ 28 29 /* 30 * Sun 4u control registers. (includes address space definitions 31 * and some registers in control space). 32 */ 33 34 /* 35 * The Alternate address spaces. 36 * 37 * 0x00-0x7f are privileged 38 * 0x80-0xff can be used by users 39 */ 40 41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 42 43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 45 46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 48 49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 51 52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */ 54 55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 57 58 #define ASI_MMU 0x21 /* [4v] MMU context control - both IMMU and DMMU */ 59 60 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 61 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 62 63 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 64 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 65 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 66 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 67 68 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */ 69 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */ 70 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */ 71 72 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 73 74 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 75 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 76 77 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 78 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 79 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 80 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 81 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 82 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 83 84 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to I-cache data RAM */ 85 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to I-cache tag RAM */ 86 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush I-cache page using primary context */ 87 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush I-cache page using secondary context */ 88 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush I-cache context using primary context */ 89 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush I-cache context using secondary context */ 90 91 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 92 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 93 94 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 95 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 96 97 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 98 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 99 100 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 101 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 102 103 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 104 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 105 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 106 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 107 108 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 109 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 110 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 111 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 112 113 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 114 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 115 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 116 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 117 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 118 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 119 120 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 121 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 122 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 123 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 124 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 125 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 126 127 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 128 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 129 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 130 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 131 132 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 133 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 134 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 135 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 136 137 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 138 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 139 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 140 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 141 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 142 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 143 144 145 /* 146 * These are the shorter names used by Solaris 147 */ 148 149 #define ASI_N ASI_NUCLEUS 150 #define ASI_NL ASI_NUCLEUS_LITTLE 151 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 152 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 153 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 154 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 155 #define ASI_P ASI_PRIMARY 156 #define ASI_S ASI_SECONDARY 157 #define ASI_PNF ASI_PRIMARY_NOFAULT 158 #define ASI_SNF ASI_SECONDARY_NOFAULT 159 #define ASI_PL ASI_PRIMARY_LITTLE 160 #define ASI_SL ASI_SECONDARY_LITTLE 161 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 162 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 163 #define ASI_FL8_P ASI_FL8_PRIMARY 164 #define ASI_FL8_S ASI_FL8_SECONDARY 165 #define ASI_FL16_P ASI_FL16_PRIMARY 166 #define ASI_FL16_S ASI_FL16_SECONDARY 167 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 168 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 169 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 170 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 171 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 172 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 173 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 174 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 175 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 176 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 177 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 178 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 179 #define ASI_BLK_P ASI_BLOCK_PRIMARY 180 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 181 #define ASI_BLK_S ASI_BLOCK_SECONDARY 182 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 183 184 /* Alternative spellings */ 185 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 186 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 187 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 188 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 189 190 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 191 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 192 193 /* 194 * The following are 4u control registers 195 */ 196 197 /* Get the CPU's UPAID */ 198 #define UPA_CR_MID_SHIFT (17) 199 #define UPA_CR_MID_SIZE (5) 200 #define UPA_CR_MID_MASK \ 201 (((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT) 202 203 #define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1)) 204 205 #ifdef _LOCORE 206 207 #define UPA_GET_MID(r1) \ 208 ldxa [%g0] ASI_MID_REG, r1 ; \ 209 srlx r1, UPA_CR_MID_SHIFT, r1 ; \ 210 and r1, (1 << UPA_CR_MID_SIZE) - 1, r1 211 212 #else 213 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 214 #endif 215 216 /* Get the CPU's Fireplane agent ID */ 217 #define FIREPLANE_CR_AID(x) (((x) >> 17) & 0x3ff) 218 #define CPU_FIREPLANEID FIREPLANE_CR_AID(ldxa(0, ASI_MID_REG)) 219 220 /* Get the CPU's Jupiter Bus interrupt target ID */ 221 #define JUPITER_CR_ITID(x) ((x) & 0x3ff) 222 #define CPU_JUPITERID JUPITER_CR_ITID(ldxa(0, ASI_MID_REG)) 223 224 /* 225 * [4u] MMU and Cache Control Register (MCCR) 226 * use ASI = 0x45 227 */ 228 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 229 #define MCCR 0x00 230 231 /* MCCR Bits and their meanings */ 232 #define MCCR_DMMU_EN 0x08 233 #define MCCR_IMMU_EN 0x04 234 #define MCCR_DCACHE_EN 0x02 235 #define MCCR_ICACHE_EN 0x01 236 #define MCCR_RAW_EN 0x400000000000 237 238 239 /* 240 * MMU control registers 241 */ 242 243 /* Choose an MMU */ 244 #define ASI_DMMU 0x58 245 #define ASI_IMMU 0x50 246 247 /* Other assorted MMU ASIs */ 248 #define ASI_IMMU_8KPTR 0x51 249 #define ASI_IMMU_64KPTR 0x52 250 #define ASI_IMMU_DATA_IN 0x54 251 #define ASI_IMMU_TLB_DATA 0x55 252 #define ASI_IMMU_TLB_TAG 0x56 253 #define ASI_DMMU_8KPTR 0x59 254 #define ASI_DMMU_64KPTR 0x5a 255 #define ASI_DMMU_DATA_IN 0x5c 256 #define ASI_DMMU_TLB_DATA 0x5d 257 #define ASI_DMMU_TLB_TAG 0x5e 258 259 /* 260 * The following are the control registers 261 * They work on both MMUs unless noted. 262 * III = cheetah only 263 * 264 * Register contents are defined later on individual registers. 265 */ 266 #define TSB_TAG_TARGET 0x0 267 #define TLB_DATA_IN 0x0 268 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 269 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 270 #define SFSR 0x18 271 #define SFAR 0x20 /* fault address -- DMMU only */ 272 #define TSB 0x28 273 #define TLB_TAG_ACCESS 0x30 274 #define VIRTUAL_WATCHPOINT 0x38 275 #define PHYSICAL_WATCHPOINT 0x40 276 #define TSB_PEXT 0x48 /* III primary ext */ 277 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */ 278 #define TSB_NEXT 0x58 /* III nucleus ext */ 279 280 /* Tag Target bits */ 281 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 282 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 283 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 284 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 285 286 /* SFSR bits for both D_SFSR and I_SFSR */ 287 #define SFSR_ASI(x) ((x)>>16) 288 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 289 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 290 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 291 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 292 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 293 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 294 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 295 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 296 #define SFSR_CTXT(x) (((x)>>4)&0x3) 297 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 298 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 299 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 300 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 301 #define SFSR_W 0x00004 /* DMMU: attempted write */ 302 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 303 #define SFSR_FV 0x00001 /* Fault is valid */ 304 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \ 305 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 306 307 #define SFSR_BITS "\177\20" \ 308 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \ 309 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \ 310 "b\3W\0" "b\2OW\0" "b\1FV\0" 311 312 /* ASFR bits */ 313 #define ASFR_ME 0x100000000LL 314 #define ASFR_PRIV 0x080000000LL 315 #define ASFR_ISAP 0x040000000LL 316 #define ASFR_ETP 0x020000000LL 317 #define ASFR_IVUE 0x010000000LL 318 #define ASFR_TO 0x008000000LL 319 #define ASFR_BERR 0x004000000LL 320 #define ASFR_LDP 0x002000000LL 321 #define ASFR_CP 0x001000000LL 322 #define ASFR_WP 0x000800000LL 323 #define ASFR_EDP 0x000400000LL 324 #define ASFR_UE 0x000200000LL 325 #define ASFR_CE 0x000100000LL 326 #define ASFR_ETS 0x0000f0000LL 327 #define ASFT_P_SYND 0x00000ffffLL 328 329 #define AFSR_BITS "\177\20" \ 330 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 331 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 332 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 333 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 334 335 /* 336 * Here's the spitfire TSB control register bits. 337 * 338 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 339 */ 340 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 341 #define TSB_SIZE_1K 0x01 342 #define TSB_SIZE_2K 0x02 343 #define TSB_SIZE_4K 0x03 344 #define TSB_SIZE_8K 0x04 345 #define TSB_SIZE_16K 0x05 346 #define TSB_SIZE_32K 0x06 347 #define TSB_SIZE_64K 0x07 348 #define TSB_SPLIT 0x1000 349 #define TSB_BASE 0xffffffffffffe000 350 351 /* TLB Tag Access bits */ 352 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 353 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 354 355 /* 356 * TLB demap registers. TTEs are defined in v9pte.h 357 * 358 * Use the address space to select between IMMU and DMMU. 359 * The address of the register selects which context register 360 * to read the ASI from. 361 * 362 * The data stored in the register is interpreted as the VA to 363 * use. The DEMAP_CTX_<> registers ignore the address and demap the 364 * entire ASI. 365 * 366 */ 367 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 368 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 369 370 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 371 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 372 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 373 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 374 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 375 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 376 #define DEMAP_ALL ((0x08)<<4) /* Demap all non-locked TLB entries [USIII] */ 377 378 /* 379 * These define the sizes of the TLB in various CPUs. 380 * They're mostly not necessary except for diagnostic code. 381 */ 382 #define TLB_SIZE_SPITFIRE 64 383 #define TLB_SIZE_CHEETAH_I16 16 384 #define TLB_SIZE_CHEETAH_I128 128 385 #define TLB_SIZE_CHEETAH_D16 16 386 #define TLB_SIZE_CHEETAH_D512_0 512 387 #define TLB_SIZE_CHEETAH_D512_1 512 388 #define TLB_CHEETAH_I16 (0 << 16) 389 #define TLB_CHEETAH_I128 (2 << 16) 390 #define TLB_CHEETAH_D16 (0 << 16) 391 #define TLB_CHEETAH_D512_0 (2 << 16) 392 #define TLB_CHEETAH_D512_1 (3 << 16) 393 394 /* 395 * Interrupt registers. This really gets hairy. 396 */ 397 398 /* IRSR -- Interrupt Receive Status Ragister */ 399 #define ASI_IRSR 0x49 400 #define IRSR 0x00 401 #define IRSR_BUSY 0x020 402 #define IRSR_MID(x) (x&0x1f) 403 404 /* IRDR -- Interrupt Receive Data Registers */ 405 #define ASI_IRDR 0x7f 406 #define IRDR_0H 0x40 407 #define IRDR_0L 0x48 /* unimplemented */ 408 #define IRDR_1H 0x50 409 #define IRDR_1L 0x58 /* unimplemented */ 410 #define IRDR_2H 0x60 411 #define IRDR_2L 0x68 /* unimplemented */ 412 #define IRDR_3H 0x70 /* unimplemented */ 413 #define IRDR_3L 0x78 /* unimplemented */ 414 415 /* Interrupt Dispatch -- usually reserved for cross-calls */ 416 #define ASI_IDSR 0x48 /* Interrupt dispatch status reg */ 417 #define IDSR 0x00 418 #define IDSR_NACK 0x02 419 #define IDSR_BUSY 0x01 420 421 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 422 423 /* Interrupt delivery initiation */ 424 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 425 426 #define IDDR_0H 0x40 /* Store data to send in these regs */ 427 #define IDDR_0L 0x48 /* unimplemented */ 428 #define IDDR_1H 0x50 429 #define IDDR_1L 0x58 /* unimplemented */ 430 #define IDDR_2H 0x60 431 #define IDDR_2L 0x68 /* unimplemented */ 432 #define IDDR_3H 0x70 /* unimplemented */ 433 #define IDDR_3L 0x78 /* unimplemented */ 434 435 /* 436 * Error registers 437 */ 438 439 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 440 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 441 #define AFAR 0x00 442 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 443 #define AFSR 0x00 444 445 #define ASI_P_EER 0x4b /* Error enable register */ 446 #define P_EER 0x00 447 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 448 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 449 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 450 451 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 452 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 453 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 454 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 455 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 456 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 457 458 459 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 460 461 #ifndef _LOCORE 462 /* 463 * GCC __asm constructs for doing assembly stuff. 464 */ 465 466 /* 467 * ``Routines'' to load and store from/to alternate address space. 468 * The location can be a variable, the asi value (address space indicator) 469 * must be a constant. 470 * 471 * N.B.: You can put as many special functions here as you like, since 472 * they cost no kernel space or time if they are not used. 473 * 474 * These were static inline functions, but gcc screws up the constraints 475 * on the address space identifiers (the "n"umeric value part) because 476 * it inlines too late, so we have to use the funny valued-macro syntax. 477 */ 478 479 /* 480 * Apparently the definition of bypass ASIs is that they all use the 481 * D$ so we need to flush the D$ to make sure we don't get data pollution. 482 */ 483 484 #ifdef __arch64__ 485 486 /* 64-bit kernel, non-constant */ 487 #define SPARC64_LD_NONCONST(ld) \ 488 __asm volatile( \ 489 "wr %2,%%g0,%%asi; " \ 490 #ld " [%1]%%asi,%0 " \ 491 : "=r" (_v) \ 492 : "r" ((__uintptr_t)(loc)), "r" (asi)) 493 494 #if defined(__GNUC__) && defined(__OPTIMIZE__) 495 #define SPARC64_LD_DEF(ld, type, vtype) \ 496 static __inline type ld(paddr_t loc, int asi) \ 497 { \ 498 vtype _v; \ 499 if (__builtin_constant_p(asi)) \ 500 __asm volatile( \ 501 #ld " [%1]%2,%0 " \ 502 : "=r" (_v) \ 503 : "r" ((__uintptr_t)(loc)), "n" (asi)); \ 504 else \ 505 SPARC64_LD_NONCONST(ld); \ 506 return _v; \ 507 } 508 #else 509 #define SPARC64_LD_DEF(ld, type, vtype) \ 510 static __inline type ld(paddr_t loc, int asi) \ 511 { \ 512 vtype _v; \ 513 SPARC64_LD_NONCONST(ld); \ 514 return _v; \ 515 } 516 #endif 517 #define SPARC64_LD_DEF64(ld, type) SPARC64_LD_DEF(ld, type, uint64_t) 518 519 #else /* __arch64__ */ 520 521 /* 32-bit kernel, MMU bypass, non-constant */ 522 #define SPARC64_LD_PHYS_NONCONST(ld) \ 523 __asm volatile( \ 524 "clruw %2; " \ 525 "rdpr %%pstate,%1; " \ 526 "sllx %3,32,%0; " \ 527 "wrpr %1,8,%%pstate; " \ 528 "or %0,%2,%0; " \ 529 "wr %4,%%g0,%%asi; " \ 530 #ld " [%0]%%asi,%0; " \ 531 "wrpr %1,0,%%pstate " \ 532 : "=&r" (_v), "=&r" (_pstate) \ 533 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 534 /* 32-bit kernel, non-constant */ 535 #define SPARC64_LD_NONCONST(ld) \ 536 __asm volatile( \ 537 "wr %2,%%g0,%%asi; " \ 538 #ld " [%1]%%asi,%0 " \ 539 : "=&r" (_v) \ 540 : "r" ((uint32_t)(loc)), "r" (asi)) 541 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 542 #define SPARC64_LD_PHYS_NONCONST64(ld) \ 543 __asm volatile( \ 544 "clruw %2; " \ 545 "rdpr %%pstate,%1; " \ 546 "sllx %3,32,%0; " \ 547 "wrpr %1,8,%%pstate; " \ 548 "or %0,%2,%0; " \ 549 "wr %4,%%g0,%%asi; " \ 550 #ld " [%0]%%asi,%0; " \ 551 "wrpr %1,0,%%pstate; " \ 552 "srlx %0,32,%1; " \ 553 "srl %0,0,%0 " \ 554 : "=&r" (_vlo), "=&r" (_vhi) \ 555 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 556 /* 32-bit kernel, non-constant, 64-bit value */ 557 #define SPARC64_LD_NONCONST64(ld) \ 558 __asm volatile( \ 559 "wr %3,%%g0,%%asi; " \ 560 #ld " [%2]%%asi,%0; " \ 561 "srlx %0,32,%1; " \ 562 "srl %0,0,%0 " \ 563 : "=&r" (_vlo), "=&r" (_vhi) \ 564 : "r" ((uint32_t)(loc)), "r" (asi)) 565 566 #if defined(__GNUC__) && defined(__OPTIMIZE__) 567 #define SPARC64_LD_DEF(ld, type, vtype) \ 568 static __inline type ld(paddr_t loc, int asi) \ 569 { \ 570 vtype _v; \ 571 uint32_t _hi, _pstate; \ 572 if (PHYS_ASI(asi)) { \ 573 _hi = (uint64_t)(loc) >> 32; \ 574 if (__builtin_constant_p(asi)) \ 575 __asm volatile( \ 576 "clruw %2; " \ 577 "rdpr %%pstate,%1; " \ 578 "sllx %3,32,%0; " \ 579 "wrpr %1,8,%%pstate; " \ 580 "or %0,%2,%0; " \ 581 #ld " [%0]%4,%0; " \ 582 "wrpr %1,0,%%pstate; " \ 583 : "=&r" (_v), "=&r" (_pstate) \ 584 : "r" ((uint32_t)(loc)), "r" (_hi), \ 585 "n" (asi)); \ 586 else \ 587 SPARC64_LD_PHYS_NONCONST(ld); \ 588 } else { \ 589 if (__builtin_constant_p(asi)) \ 590 __asm volatile( \ 591 #ld " [%1]%2,%0 " \ 592 : "=&r" (_v) \ 593 : "r" ((uint32_t)(loc)), "n" (asi)); \ 594 else \ 595 SPARC64_LD_NONCONST(ld); \ 596 } \ 597 return _v; \ 598 } 599 #define SPARC64_LD_DEF64(ld, type) \ 600 static __inline type ld(paddr_t loc, int asi) \ 601 { \ 602 uint32_t _vlo, _vhi, _hi; \ 603 if (PHYS_ASI(asi)) { \ 604 _hi = (uint64_t)(loc) >> 32; \ 605 if (__builtin_constant_p(asi)) \ 606 __asm volatile( \ 607 "clruw %2; " \ 608 "rdpr %%pstate,%1; " \ 609 "sllx %3,32,%0; " \ 610 "wrpr %1,8,%%pstate; " \ 611 "or %0,%2,%0; " \ 612 #ld " [%0]%4,%0; " \ 613 "wrpr %1,0,%%pstate; " \ 614 "srlx %0,32,%1; " \ 615 "srl %0,0,%0 " \ 616 : "=&r" (_vlo), "=&r" (_vhi) \ 617 : "r" ((uint32_t)(loc)), "r" (_hi), \ 618 "n" (asi)); \ 619 else \ 620 SPARC64_LD_PHYS_NONCONST64(ld); \ 621 } else { \ 622 if (__builtin_constant_p(asi)) \ 623 __asm volatile( \ 624 #ld " [%2]%3,%0; " \ 625 "srlx %0,32,%1; " \ 626 "srl %0,0,%0 " \ 627 : "=&r" (_vlo), "=&r" (_vhi) \ 628 : "r" ((uint32_t)(loc)), "n" (asi)); \ 629 else \ 630 SPARC64_LD_NONCONST64(ld); \ 631 } \ 632 return ((uint64_t)_vhi << 32) | _vlo; \ 633 } 634 #else 635 #define SPARC64_LD_DEF(ld, type, vtype) \ 636 static __inline type ld(paddr_t loc, int asi) \ 637 { \ 638 vtype _v; \ 639 uint32_t _hi, _pstate; \ 640 if (PHYS_ASI(asi)) { \ 641 _hi = (uint64_t)(loc) >> 32; \ 642 SPARC64_LD_PHYS_NONCONST(ld); \ 643 } else \ 644 SPARC64_LD_NONCONST(ld); \ 645 return _v; \ 646 } 647 #define SPARC64_LD_DEF64(ld, type) \ 648 static __inline type ld(paddr_t loc, int asi) \ 649 { \ 650 uint32_t _vlo, _vhi, _hi; \ 651 if (PHYS_ASI(asi)) { \ 652 _hi = (uint64_t)(loc) >> 32; \ 653 SPARC64_LD_PHYS_NONCONST64(ld); \ 654 } else \ 655 SPARC64_LD_NONCONST64(ld); \ 656 return ((uint64_t)_vhi << 32) | _vlo; \ 657 } 658 #endif 659 660 #endif /* __arch64__ */ 661 662 /* load byte from alternate address space */ 663 SPARC64_LD_DEF(lduba, uint8_t, uint32_t) 664 /* load half-word from alternate address space */ 665 SPARC64_LD_DEF(lduha, uint16_t, uint32_t) 666 /* load unsigned int from alternate address space */ 667 SPARC64_LD_DEF(lda, uint32_t, uint32_t) 668 /* load unsigned word from alternate address space */ 669 SPARC64_LD_DEF(lduwa, uint32_t, uint32_t) 670 /* load signed int from alternate address space */ 671 SPARC64_LD_DEF(ldswa, int, int) 672 /* load 64-bit unsigned int from alternate address space */ 673 SPARC64_LD_DEF64(ldxa, uint64_t) 674 675 676 #ifdef __arch64__ 677 678 /* 64-bit kernel, non-constant */ 679 #define SPARC64_ST_NONCONST(st) \ 680 __asm volatile( \ 681 "wr %2,%%g0,%%asi; " \ 682 #st " %0,[%1]%%asi " \ 683 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 684 "r" (asi)) 685 686 #if defined(__GNUC__) && defined(__OPTIMIZE__) 687 #define SPARC64_ST_DEF(st, type) \ 688 static __inline void st(paddr_t loc, int asi, type value) \ 689 { \ 690 if (__builtin_constant_p(asi)) \ 691 __asm volatile( \ 692 #st " %0,[%1]%2 " \ 693 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 694 "n" (asi)); \ 695 else \ 696 SPARC64_ST_NONCONST(st); \ 697 } 698 #else 699 #define SPARC64_ST_DEF(st, type) \ 700 static __inline void st(paddr_t loc, int asi, type value) \ 701 { \ 702 SPARC64_ST_NONCONST(st); \ 703 } 704 #endif 705 #define SPARC64_ST_DEF64(st, type) SPARC64_ST_DEF(st, type) 706 707 #else /* __arch64__ */ 708 709 /* 32-bit kernel, MMU bypass, non-constant */ 710 #define SPARC64_ST_PHYS_NONCONST(st) \ 711 __asm volatile( \ 712 "clruw %3; " \ 713 "rdpr %%pstate,%1; " \ 714 "sllx %4,32,%0; " \ 715 "wrpr %1,8,%%pstate; " \ 716 "or %0,%3,%0; " \ 717 "wr %5,%%g0,%%asi; " \ 718 #st " %2,[%0]%%asi; " \ 719 "wrpr %1,0,%%pstate " \ 720 : "=&r" (_hi), "=&r" (_pstate) \ 721 : "r" (value), "r" ((uint32_t)(loc)), \ 722 "r" (_hi), "r" (asi)) 723 /* 32-bit kernel, non-constant */ 724 #define SPARC64_ST_NONCONST(st) \ 725 __asm volatile( \ 726 "wr %2,%%g0,%%asi; " \ 727 #st " %0,[%1]%%asi " \ 728 : : "r" (value), "r" ((uint32_t)(loc)), "r" (asi)) 729 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 730 #define SPARC64_ST_PHYS_NONCONST64(st) \ 731 __asm volatile( \ 732 "clruw %3; " \ 733 "clruw %5; " \ 734 "sllx %4,32,%1; " \ 735 "sllx %6,32,%0; " \ 736 "rdpr %%pstate,%2; " \ 737 "or %1,%3,%1; " \ 738 "wrpr %2,8,%%pstate; " \ 739 "or %0,%5,%0; " \ 740 "wr %7,%%g0,%%asi; " \ 741 #st " %1,[%0]%%asi; " \ 742 "wrpr %2,0,%%pstate " \ 743 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 744 : "r" (_vlo), "r" (_vhi), \ 745 "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 746 /* 32-bit kernel, non-constant, 64-bit value */ 747 #define SPARC64_ST_NONCONST64(st) \ 748 __asm volatile( \ 749 "clruw %1; " \ 750 "sllx %2,32,%0; " \ 751 "or %0,%1,%0; " \ 752 "wr %4,%%g0,%%asi; " \ 753 #st " %0,[%3]%%asi " \ 754 : "=&r" (_vhi) \ 755 : "r" (_vlo), "r" (_vhi), \ 756 "r" ((uint32_t)(loc)), "r" (asi)) 757 758 #if defined(__GNUC__) && defined(__OPTIMIZE__) 759 #define SPARC64_ST_DEF(st, type) \ 760 static __inline void st(paddr_t loc, int asi, type value) \ 761 { \ 762 uint32_t _hi, _pstate; \ 763 if (PHYS_ASI(asi)) { \ 764 _hi = (uint64_t)(loc) >> 32; \ 765 if (__builtin_constant_p(asi)) \ 766 __asm volatile( \ 767 "clruw %3; " \ 768 "sllx %4,32,%0; " \ 769 "rdpr %%pstate,%1; " \ 770 "or %0,%3,%0; " \ 771 "wrpr %1,8,%%pstate; " \ 772 #st " %2,[%0]%5; " \ 773 "wrpr %1,0,%%pstate " \ 774 : "=&r" (_hi), "=&r" (_pstate) \ 775 : "r" (value), "r" ((uint32_t)(loc)), \ 776 "r" (_hi), "n" (asi)); \ 777 else \ 778 SPARC64_ST_PHYS_NONCONST(st); \ 779 } else { \ 780 if (__builtin_constant_p(asi)) \ 781 __asm volatile( \ 782 #st " %0,[%1]%2 " \ 783 : : "r" (value), "r" ((uint32_t)(loc)), \ 784 "n" (asi)); \ 785 else \ 786 SPARC64_ST_NONCONST(st); \ 787 } \ 788 } 789 #define SPARC64_ST_DEF64(st, type) \ 790 static __inline void st(paddr_t loc, int asi, type value) \ 791 { \ 792 uint32_t _vlo, _vhi, _hi; \ 793 _vlo = value; \ 794 _vhi = (uint64_t)(value) >> 32; \ 795 if (PHYS_ASI(asi)) { \ 796 _hi = (uint64_t)(loc) >> 32; \ 797 if (__builtin_constant_p(asi)) \ 798 __asm volatile( \ 799 "clruw %3; " \ 800 "clruw %5; " \ 801 "sllx %4,32,%1; " \ 802 "sllx %6,32,%0; " \ 803 "rdpr %%pstate,%2; " \ 804 "or %1,%3,%1; " \ 805 "or %0,%5,%0; " \ 806 "wrpr %2,8,%%pstate; " \ 807 #st " %1,[%0]%7; " \ 808 "wrpr %2,0,%%pstate " \ 809 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 810 : "r" (_vlo), "r" (_vhi), \ 811 "r" ((uint32_t)(loc)), "r" (_hi), \ 812 "n" (asi)); \ 813 else \ 814 SPARC64_ST_PHYS_NONCONST64(st); \ 815 } else { \ 816 if (__builtin_constant_p(asi)) \ 817 __asm volatile( \ 818 "clruw %1; " \ 819 "sllx %2,32,%0; " \ 820 "or %0,%1,%0; " \ 821 #st " %0,[%3]%4 " \ 822 : "=&r" (_vhi) \ 823 : "r" (_vlo), "r" (_vhi), \ 824 "r" ((uint32_t)(loc)), "n" (asi)); \ 825 else \ 826 SPARC64_ST_NONCONST64(st); \ 827 } \ 828 } 829 #else 830 #define SPARC64_ST_DEF(st, type) \ 831 static __inline void st(paddr_t loc, int asi, type value) \ 832 { \ 833 uint32_t _hi, _pstate; \ 834 if (PHYS_ASI(asi)) { \ 835 _hi = (uint64_t)(loc) >> 32; \ 836 SPARC64_ST_PHYS_NONCONST(st); \ 837 } else \ 838 SPARC64_ST_NONCONST(st); \ 839 } 840 #define SPARC64_ST_DEF64(st, type) \ 841 static __inline void st(paddr_t loc, int asi, type value) \ 842 { \ 843 uint32_t _vlo, _vhi, _hi; \ 844 _vlo = value; \ 845 _vhi = (uint64_t)(value) >> 32; \ 846 if (PHYS_ASI(asi)) { \ 847 _hi = (uint64_t)(loc) >> 32; \ 848 SPARC64_ST_PHYS_NONCONST64(st); \ 849 } else \ 850 SPARC64_ST_NONCONST64(st); \ 851 } 852 #endif 853 854 #endif /* __arch64__ */ 855 856 /* store byte to alternate address space */ 857 SPARC64_ST_DEF(stba, uint8_t) 858 /* store half-word to alternate address space */ 859 SPARC64_ST_DEF(stha, uint16_t) 860 /* store unsigned int to alternate address space */ 861 SPARC64_ST_DEF(sta, uint32_t) 862 /* store 64-bit unsigned int to alternate address space */ 863 SPARC64_ST_DEF64(stxa, uint64_t) 864 865 866 /* set dmmu secondary context */ 867 static __inline void 868 dmmu_set_secondary_context(uint ctx) 869 { 870 __asm volatile( 871 "stxa %0,[%1]%2; " 872 "membar #Sync " 873 : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU) 874 : "memory"); 875 } 876 877 /* flush address from data cache */ 878 #define flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc))) 879 880 /* 881 * SPARC V9 memory barrier instructions. 882 */ 883 /* Make all stores complete before next store */ 884 #define membar_StoreStore() __asm volatile("membar #StoreStore" : :) 885 /* Make all loads complete before next store */ 886 #define membar_LoadStore() __asm volatile("membar #LoadStore" : :) 887 /* Make all stores complete before next load */ 888 #define membar_StoreLoad() __asm volatile("membar #StoreLoad" : :) 889 /* Make all loads complete before next load */ 890 #define membar_LoadLoad() __asm volatile("membar #LoadLoad" : :) 891 /* Complete all outstanding memory operations and exceptions */ 892 #define membar_Sync() __asm volatile("membar #Sync" : :) 893 /* Complete all outstanding memory operations */ 894 #define membar_MemIssue() __asm volatile("membar #MemIssue" : :) 895 /* Complete all outstanding stores before any new loads */ 896 #define membar_Lookaside() __asm volatile("membar #Lookaside" : :) 897 898 #define membar_Load() __asm volatile("membar #LoadLoad | #LoadStore" : :) 899 #define membar_Store() __asm volatile("membar #LoadStore | #StoreStore" : :) 900 901 #endif 902 903 #endif /* _SPARC_CTLREG_H_ */ 904
Indexes created Tue Sep 30 20:09:53 GMT 2025