ctlreg.h revision 1.62
1 /* $NetBSD: ctlreg.h,v 1.62 2015/04/01 18:38:30 palle Exp $ */ 2 3 /* 4 * Copyright (c) 1996-2002 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _SPARC_CTLREG_H_ 27 #define _SPARC_CTLREG_H_ 28 29 /* 30 * Sun 4u control registers. (includes address space definitions 31 * and some registers in control space). 32 */ 33 34 /* 35 * The Alternate address spaces. 36 * 37 * 0x00-0x7f are privileged 38 * 0x80-0xff can be used by users 39 */ 40 41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 42 43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 45 46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 48 49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 51 52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */ 54 55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 57 58 #define ASI_MMU 0x21 /* [4v] MMU context control - both IMMU and DMMU */ 59 60 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 61 #define ASI_QUEUE 0x25 /* [4v] interrupt queue registers */ 62 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 63 64 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 65 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 66 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 67 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 68 69 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */ 70 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */ 71 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */ 72 73 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 74 75 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 76 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 77 78 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 79 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 80 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 81 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 82 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 83 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 84 85 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to I-cache data RAM */ 86 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to I-cache tag RAM */ 87 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush I-cache page using primary context */ 88 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush I-cache page using secondary context */ 89 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush I-cache context using primary context */ 90 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush I-cache context using secondary context */ 91 92 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 93 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 94 95 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 96 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 97 98 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 99 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 100 101 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 102 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 103 104 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 105 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 106 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */ 107 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */ 108 109 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 110 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 111 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 112 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 113 114 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 115 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 116 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 117 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 118 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 119 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 120 121 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 122 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 123 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 124 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 125 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 126 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 127 128 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 129 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 130 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 131 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 132 133 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 134 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 135 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 136 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 137 138 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 139 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 140 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 141 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 142 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 143 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 144 145 146 /* 147 * These are the shorter names used by Solaris 148 */ 149 150 #define ASI_N ASI_NUCLEUS 151 #define ASI_NL ASI_NUCLEUS_LITTLE 152 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 153 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 154 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 155 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 156 #define ASI_P ASI_PRIMARY 157 #define ASI_S ASI_SECONDARY 158 #define ASI_PNF ASI_PRIMARY_NOFAULT 159 #define ASI_SNF ASI_SECONDARY_NOFAULT 160 #define ASI_PL ASI_PRIMARY_LITTLE 161 #define ASI_SL ASI_SECONDARY_LITTLE 162 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE 163 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE 164 #define ASI_FL8_P ASI_FL8_PRIMARY 165 #define ASI_FL8_S ASI_FL8_SECONDARY 166 #define ASI_FL16_P ASI_FL16_PRIMARY 167 #define ASI_FL16_S ASI_FL16_SECONDARY 168 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE 169 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE 170 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE 171 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE 172 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 173 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 174 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 175 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 176 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 177 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 178 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 179 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 180 #define ASI_BLK_P ASI_BLOCK_PRIMARY 181 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 182 #define ASI_BLK_S ASI_BLOCK_SECONDARY 183 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 184 185 /* Alternative spellings */ 186 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT 187 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE 188 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT 189 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE 190 191 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d) 192 #define LITTLE_ASI(x) ((x) & ASI_LITTLE) 193 194 /* 195 * The following are 4u control registers 196 */ 197 198 /* Get the CPU's UPAID */ 199 #define UPA_CR_MID_SHIFT (17) 200 #define UPA_CR_MID_SIZE (5) 201 #define UPA_CR_MID_MASK \ 202 (((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT) 203 204 #define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1)) 205 206 #ifdef _LOCORE 207 208 #define UPA_GET_MID(r1) \ 209 ldxa [%g0] ASI_MID_REG, r1 ; \ 210 srlx r1, UPA_CR_MID_SHIFT, r1 ; \ 211 and r1, (1 << UPA_CR_MID_SIZE) - 1, r1 212 213 #else 214 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG)) 215 #endif 216 217 /* Get the CPU's Fireplane agent ID */ 218 #define FIREPLANE_CR_AID(x) (((x) >> 17) & 0x3ff) 219 #define CPU_FIREPLANEID FIREPLANE_CR_AID(ldxa(0, ASI_MID_REG)) 220 221 /* Get the CPU's Jupiter Bus interrupt target ID */ 222 #define JUPITER_CR_ITID(x) ((x) & 0x3ff) 223 #define CPU_JUPITERID JUPITER_CR_ITID(ldxa(0, ASI_MID_REG)) 224 225 /* 226 * [4u] MMU and Cache Control Register (MCCR) 227 * use ASI = 0x45 228 */ 229 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 230 #define MCCR 0x00 231 232 /* MCCR Bits and their meanings */ 233 #define MCCR_DMMU_EN 0x08 234 #define MCCR_IMMU_EN 0x04 235 #define MCCR_DCACHE_EN 0x02 236 #define MCCR_ICACHE_EN 0x01 237 #define MCCR_RAW_EN 0x400000000000 238 239 240 /* 241 * MMU control registers 242 */ 243 244 /* Choose an MMU */ 245 #define ASI_DMMU 0x58 246 #define ASI_IMMU 0x50 247 248 /* Other assorted MMU ASIs */ 249 #define ASI_IMMU_8KPTR 0x51 250 #define ASI_IMMU_64KPTR 0x52 251 #define ASI_IMMU_DATA_IN 0x54 252 #define ASI_IMMU_TLB_DATA 0x55 253 #define ASI_IMMU_TLB_TAG 0x56 254 #define ASI_DMMU_8KPTR 0x59 255 #define ASI_DMMU_64KPTR 0x5a 256 #define ASI_DMMU_DATA_IN 0x5c 257 #define ASI_DMMU_TLB_DATA 0x5d 258 #define ASI_DMMU_TLB_TAG 0x5e 259 260 /* 261 * The following are the control registers 262 * They work on both MMUs unless noted. 263 * III = cheetah only 264 * 265 * Register contents are defined later on individual registers. 266 */ 267 #define TSB_TAG_TARGET 0x0 268 #define TLB_DATA_IN 0x0 269 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 270 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 271 #define SFSR 0x18 272 #define SFAR 0x20 /* fault address -- DMMU only */ 273 #define TSB 0x28 274 #define TLB_TAG_ACCESS 0x30 275 #define VIRTUAL_WATCHPOINT 0x38 276 #define PHYSICAL_WATCHPOINT 0x40 277 #define TSB_PEXT 0x48 /* III primary ext */ 278 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */ 279 #define TSB_NEXT 0x58 /* III nucleus ext */ 280 281 /* Tag Target bits */ 282 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 283 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 284 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 285 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 286 287 /* SFSR bits for both D_SFSR and I_SFSR */ 288 #define SFSR_ASI(x) ((x)>>16) 289 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 290 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 291 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 292 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 293 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 294 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 295 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 296 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 297 #define SFSR_CTXT(x) (((x)>>4)&0x3) 298 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 299 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 300 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 301 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 302 #define SFSR_W 0x00004 /* DMMU: attempted write */ 303 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 304 #define SFSR_FV 0x00001 /* Fault is valid */ 305 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \ 306 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 307 308 #define SFSR_BITS "\177\20" \ 309 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \ 310 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \ 311 "b\3W\0" "b\2OW\0" "b\1FV\0" 312 313 /* ASFR bits */ 314 #define ASFR_ME 0x100000000LL 315 #define ASFR_PRIV 0x080000000LL 316 #define ASFR_ISAP 0x040000000LL 317 #define ASFR_ETP 0x020000000LL 318 #define ASFR_IVUE 0x010000000LL 319 #define ASFR_TO 0x008000000LL 320 #define ASFR_BERR 0x004000000LL 321 #define ASFR_LDP 0x002000000LL 322 #define ASFR_CP 0x001000000LL 323 #define ASFR_WP 0x000800000LL 324 #define ASFR_EDP 0x000400000LL 325 #define ASFR_UE 0x000200000LL 326 #define ASFR_CE 0x000100000LL 327 #define ASFR_ETS 0x0000f0000LL 328 #define ASFT_P_SYND 0x00000ffffLL 329 330 #define AFSR_BITS "\177\20" \ 331 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 332 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 333 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 334 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 335 336 /* 337 * Here's the spitfire TSB control register bits. 338 * 339 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 340 */ 341 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 342 #define TSB_SIZE_1K 0x01 343 #define TSB_SIZE_2K 0x02 344 #define TSB_SIZE_4K 0x03 345 #define TSB_SIZE_8K 0x04 346 #define TSB_SIZE_16K 0x05 347 #define TSB_SIZE_32K 0x06 348 #define TSB_SIZE_64K 0x07 349 #define TSB_SPLIT 0x1000 350 #define TSB_BASE 0xffffffffffffe000 351 352 /* TLB Tag Access bits */ 353 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 354 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 355 356 /* 357 * TLB demap registers. TTEs are defined in v9pte.h 358 * 359 * Use the address space to select between IMMU and DMMU. 360 * The address of the register selects which context register 361 * to read the ASI from. 362 * 363 * The data stored in the register is interpreted as the VA to 364 * use. The DEMAP_CTX_<> registers ignore the address and demap the 365 * entire ASI. 366 * 367 */ 368 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 369 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 370 371 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 372 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 373 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 374 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 375 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 376 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 377 #define DEMAP_ALL ((0x08)<<4) /* Demap all non-locked TLB entries [USIII] */ 378 379 /* 380 * These define the sizes of the TLB in various CPUs. 381 * They're mostly not necessary except for diagnostic code. 382 */ 383 #define TLB_SIZE_SPITFIRE 64 384 #define TLB_SIZE_CHEETAH_I16 16 385 #define TLB_SIZE_CHEETAH_I128 128 386 #define TLB_SIZE_CHEETAH_D16 16 387 #define TLB_SIZE_CHEETAH_D512_0 512 388 #define TLB_SIZE_CHEETAH_D512_1 512 389 #define TLB_CHEETAH_I16 (0 << 16) 390 #define TLB_CHEETAH_I128 (2 << 16) 391 #define TLB_CHEETAH_D16 (0 << 16) 392 #define TLB_CHEETAH_D512_0 (2 << 16) 393 #define TLB_CHEETAH_D512_1 (3 << 16) 394 395 /* 396 * Interrupt registers. This really gets hairy. 397 */ 398 399 /* IRSR -- Interrupt Receive Status Ragister */ 400 #define ASI_IRSR 0x49 401 #define IRSR 0x00 402 #define IRSR_BUSY 0x020 403 #define IRSR_MID(x) (x&0x1f) 404 405 /* IRDR -- Interrupt Receive Data Registers */ 406 #define ASI_IRDR 0x7f 407 #define IRDR_0H 0x40 408 #define IRDR_0L 0x48 /* unimplemented */ 409 #define IRDR_1H 0x50 410 #define IRDR_1L 0x58 /* unimplemented */ 411 #define IRDR_2H 0x60 412 #define IRDR_2L 0x68 /* unimplemented */ 413 #define IRDR_3H 0x70 /* unimplemented */ 414 #define IRDR_3L 0x78 /* unimplemented */ 415 416 /* Interrupt Dispatch -- usually reserved for cross-calls */ 417 #define ASI_IDSR 0x48 /* Interrupt dispatch status reg */ 418 #define IDSR 0x00 419 #define IDSR_NACK 0x02 420 #define IDSR_BUSY 0x01 421 422 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 423 424 /* Interrupt delivery initiation */ 425 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70) 426 427 #define IDDR_0H 0x40 /* Store data to send in these regs */ 428 #define IDDR_0L 0x48 /* unimplemented */ 429 #define IDDR_1H 0x50 430 #define IDDR_1L 0x58 /* unimplemented */ 431 #define IDDR_2H 0x60 432 #define IDDR_2L 0x68 /* unimplemented */ 433 #define IDDR_3H 0x70 /* unimplemented */ 434 #define IDDR_3L 0x78 /* unimplemented */ 435 436 /* 437 * Error registers 438 */ 439 440 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 441 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 442 #define AFAR 0x00 443 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 444 #define AFSR 0x00 445 446 #define ASI_P_EER 0x4b /* Error enable register */ 447 #define P_EER 0x00 448 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 449 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 450 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 451 452 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 453 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 454 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 455 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 456 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 457 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 458 459 460 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 461 462 #ifndef _LOCORE 463 /* 464 * GCC __asm constructs for doing assembly stuff. 465 */ 466 467 /* 468 * ``Routines'' to load and store from/to alternate address space. 469 * The location can be a variable, the asi value (address space indicator) 470 * must be a constant. 471 * 472 * N.B.: You can put as many special functions here as you like, since 473 * they cost no kernel space or time if they are not used. 474 * 475 * These were static inline functions, but gcc screws up the constraints 476 * on the address space identifiers (the "n"umeric value part) because 477 * it inlines too late, so we have to use the funny valued-macro syntax. 478 */ 479 480 /* 481 * Apparently the definition of bypass ASIs is that they all use the 482 * D$ so we need to flush the D$ to make sure we don't get data pollution. 483 */ 484 485 #ifdef __arch64__ 486 487 /* 64-bit kernel, non-constant */ 488 #define SPARC64_LD_NONCONST(ld) \ 489 __asm volatile( \ 490 "wr %2,%%g0,%%asi; " \ 491 #ld " [%1]%%asi,%0 " \ 492 : "=r" (_v) \ 493 : "r" ((__uintptr_t)(loc)), "r" (asi)) 494 495 #if defined(__GNUC__) && defined(__OPTIMIZE__) 496 #define SPARC64_LD_DEF(ld, type, vtype) \ 497 static __inline type ld(paddr_t loc, int asi) \ 498 { \ 499 vtype _v; \ 500 if (__builtin_constant_p(asi)) \ 501 __asm volatile( \ 502 #ld " [%1]%2,%0 " \ 503 : "=r" (_v) \ 504 : "r" ((__uintptr_t)(loc)), "n" (asi)); \ 505 else \ 506 SPARC64_LD_NONCONST(ld); \ 507 return _v; \ 508 } 509 #else 510 #define SPARC64_LD_DEF(ld, type, vtype) \ 511 static __inline type ld(paddr_t loc, int asi) \ 512 { \ 513 vtype _v; \ 514 SPARC64_LD_NONCONST(ld); \ 515 return _v; \ 516 } 517 #endif 518 #define SPARC64_LD_DEF64(ld, type) SPARC64_LD_DEF(ld, type, uint64_t) 519 520 #else /* __arch64__ */ 521 522 /* 32-bit kernel, MMU bypass, non-constant */ 523 #define SPARC64_LD_PHYS_NONCONST(ld) \ 524 __asm volatile( \ 525 "clruw %2; " \ 526 "rdpr %%pstate,%1; " \ 527 "sllx %3,32,%0; " \ 528 "wrpr %1,8,%%pstate; " \ 529 "or %0,%2,%0; " \ 530 "wr %4,%%g0,%%asi; " \ 531 #ld " [%0]%%asi,%0; " \ 532 "wrpr %1,0,%%pstate " \ 533 : "=&r" (_v), "=&r" (_pstate) \ 534 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 535 /* 32-bit kernel, non-constant */ 536 #define SPARC64_LD_NONCONST(ld) \ 537 __asm volatile( \ 538 "wr %2,%%g0,%%asi; " \ 539 #ld " [%1]%%asi,%0 " \ 540 : "=&r" (_v) \ 541 : "r" ((uint32_t)(loc)), "r" (asi)) 542 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 543 #define SPARC64_LD_PHYS_NONCONST64(ld) \ 544 __asm volatile( \ 545 "clruw %2; " \ 546 "rdpr %%pstate,%1; " \ 547 "sllx %3,32,%0; " \ 548 "wrpr %1,8,%%pstate; " \ 549 "or %0,%2,%0; " \ 550 "wr %4,%%g0,%%asi; " \ 551 #ld " [%0]%%asi,%0; " \ 552 "wrpr %1,0,%%pstate; " \ 553 "srlx %0,32,%1; " \ 554 "srl %0,0,%0 " \ 555 : "=&r" (_vlo), "=&r" (_vhi) \ 556 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 557 /* 32-bit kernel, non-constant, 64-bit value */ 558 #define SPARC64_LD_NONCONST64(ld) \ 559 __asm volatile( \ 560 "wr %3,%%g0,%%asi; " \ 561 #ld " [%2]%%asi,%0; " \ 562 "srlx %0,32,%1; " \ 563 "srl %0,0,%0 " \ 564 : "=&r" (_vlo), "=&r" (_vhi) \ 565 : "r" ((uint32_t)(loc)), "r" (asi)) 566 567 #if defined(__GNUC__) && defined(__OPTIMIZE__) 568 #define SPARC64_LD_DEF(ld, type, vtype) \ 569 static __inline type ld(paddr_t loc, int asi) \ 570 { \ 571 vtype _v; \ 572 uint32_t _hi, _pstate; \ 573 if (PHYS_ASI(asi)) { \ 574 _hi = (uint64_t)(loc) >> 32; \ 575 if (__builtin_constant_p(asi)) \ 576 __asm volatile( \ 577 "clruw %2; " \ 578 "rdpr %%pstate,%1; " \ 579 "sllx %3,32,%0; " \ 580 "wrpr %1,8,%%pstate; " \ 581 "or %0,%2,%0; " \ 582 #ld " [%0]%4,%0; " \ 583 "wrpr %1,0,%%pstate; " \ 584 : "=&r" (_v), "=&r" (_pstate) \ 585 : "r" ((uint32_t)(loc)), "r" (_hi), \ 586 "n" (asi)); \ 587 else \ 588 SPARC64_LD_PHYS_NONCONST(ld); \ 589 } else { \ 590 if (__builtin_constant_p(asi)) \ 591 __asm volatile( \ 592 #ld " [%1]%2,%0 " \ 593 : "=&r" (_v) \ 594 : "r" ((uint32_t)(loc)), "n" (asi)); \ 595 else \ 596 SPARC64_LD_NONCONST(ld); \ 597 } \ 598 return _v; \ 599 } 600 #define SPARC64_LD_DEF64(ld, type) \ 601 static __inline type ld(paddr_t loc, int asi) \ 602 { \ 603 uint32_t _vlo, _vhi, _hi; \ 604 if (PHYS_ASI(asi)) { \ 605 _hi = (uint64_t)(loc) >> 32; \ 606 if (__builtin_constant_p(asi)) \ 607 __asm volatile( \ 608 "clruw %2; " \ 609 "rdpr %%pstate,%1; " \ 610 "sllx %3,32,%0; " \ 611 "wrpr %1,8,%%pstate; " \ 612 "or %0,%2,%0; " \ 613 #ld " [%0]%4,%0; " \ 614 "wrpr %1,0,%%pstate; " \ 615 "srlx %0,32,%1; " \ 616 "srl %0,0,%0 " \ 617 : "=&r" (_vlo), "=&r" (_vhi) \ 618 : "r" ((uint32_t)(loc)), "r" (_hi), \ 619 "n" (asi)); \ 620 else \ 621 SPARC64_LD_PHYS_NONCONST64(ld); \ 622 } else { \ 623 if (__builtin_constant_p(asi)) \ 624 __asm volatile( \ 625 #ld " [%2]%3,%0; " \ 626 "srlx %0,32,%1; " \ 627 "srl %0,0,%0 " \ 628 : "=&r" (_vlo), "=&r" (_vhi) \ 629 : "r" ((uint32_t)(loc)), "n" (asi)); \ 630 else \ 631 SPARC64_LD_NONCONST64(ld); \ 632 } \ 633 return ((uint64_t)_vhi << 32) | _vlo; \ 634 } 635 #else 636 #define SPARC64_LD_DEF(ld, type, vtype) \ 637 static __inline type ld(paddr_t loc, int asi) \ 638 { \ 639 vtype _v; \ 640 uint32_t _hi, _pstate; \ 641 if (PHYS_ASI(asi)) { \ 642 _hi = (uint64_t)(loc) >> 32; \ 643 SPARC64_LD_PHYS_NONCONST(ld); \ 644 } else \ 645 SPARC64_LD_NONCONST(ld); \ 646 return _v; \ 647 } 648 #define SPARC64_LD_DEF64(ld, type) \ 649 static __inline type ld(paddr_t loc, int asi) \ 650 { \ 651 uint32_t _vlo, _vhi, _hi; \ 652 if (PHYS_ASI(asi)) { \ 653 _hi = (uint64_t)(loc) >> 32; \ 654 SPARC64_LD_PHYS_NONCONST64(ld); \ 655 } else \ 656 SPARC64_LD_NONCONST64(ld); \ 657 return ((uint64_t)_vhi << 32) | _vlo; \ 658 } 659 #endif 660 661 #endif /* __arch64__ */ 662 663 /* load byte from alternate address space */ 664 SPARC64_LD_DEF(lduba, uint8_t, uint32_t) 665 /* load half-word from alternate address space */ 666 SPARC64_LD_DEF(lduha, uint16_t, uint32_t) 667 /* load unsigned int from alternate address space */ 668 SPARC64_LD_DEF(lda, uint32_t, uint32_t) 669 /* load unsigned word from alternate address space */ 670 SPARC64_LD_DEF(lduwa, uint32_t, uint32_t) 671 /* load signed int from alternate address space */ 672 SPARC64_LD_DEF(ldswa, int, int) 673 /* load 64-bit unsigned int from alternate address space */ 674 SPARC64_LD_DEF64(ldxa, uint64_t) 675 676 677 #ifdef __arch64__ 678 679 /* 64-bit kernel, non-constant */ 680 #define SPARC64_ST_NONCONST(st) \ 681 __asm volatile( \ 682 "wr %2,%%g0,%%asi; " \ 683 #st " %0,[%1]%%asi " \ 684 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 685 "r" (asi)) 686 687 #if defined(__GNUC__) && defined(__OPTIMIZE__) 688 #define SPARC64_ST_DEF(st, type) \ 689 static __inline void st(paddr_t loc, int asi, type value) \ 690 { \ 691 if (__builtin_constant_p(asi)) \ 692 __asm volatile( \ 693 #st " %0,[%1]%2 " \ 694 : : "r" (value), "r" ((__uintptr_t)(loc)), \ 695 "n" (asi)); \ 696 else \ 697 SPARC64_ST_NONCONST(st); \ 698 } 699 #else 700 #define SPARC64_ST_DEF(st, type) \ 701 static __inline void st(paddr_t loc, int asi, type value) \ 702 { \ 703 SPARC64_ST_NONCONST(st); \ 704 } 705 #endif 706 #define SPARC64_ST_DEF64(st, type) SPARC64_ST_DEF(st, type) 707 708 #else /* __arch64__ */ 709 710 /* 32-bit kernel, MMU bypass, non-constant */ 711 #define SPARC64_ST_PHYS_NONCONST(st) \ 712 __asm volatile( \ 713 "clruw %3; " \ 714 "rdpr %%pstate,%1; " \ 715 "sllx %4,32,%0; " \ 716 "wrpr %1,8,%%pstate; " \ 717 "or %0,%3,%0; " \ 718 "wr %5,%%g0,%%asi; " \ 719 #st " %2,[%0]%%asi; " \ 720 "wrpr %1,0,%%pstate " \ 721 : "=&r" (_hi), "=&r" (_pstate) \ 722 : "r" (value), "r" ((uint32_t)(loc)), \ 723 "r" (_hi), "r" (asi)) 724 /* 32-bit kernel, non-constant */ 725 #define SPARC64_ST_NONCONST(st) \ 726 __asm volatile( \ 727 "wr %2,%%g0,%%asi; " \ 728 #st " %0,[%1]%%asi " \ 729 : : "r" (value), "r" ((uint32_t)(loc)), "r" (asi)) 730 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */ 731 #define SPARC64_ST_PHYS_NONCONST64(st) \ 732 __asm volatile( \ 733 "clruw %3; " \ 734 "clruw %5; " \ 735 "sllx %4,32,%1; " \ 736 "sllx %6,32,%0; " \ 737 "rdpr %%pstate,%2; " \ 738 "or %1,%3,%1; " \ 739 "wrpr %2,8,%%pstate; " \ 740 "or %0,%5,%0; " \ 741 "wr %7,%%g0,%%asi; " \ 742 #st " %1,[%0]%%asi; " \ 743 "wrpr %2,0,%%pstate " \ 744 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 745 : "r" (_vlo), "r" (_vhi), \ 746 "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi)) 747 /* 32-bit kernel, non-constant, 64-bit value */ 748 #define SPARC64_ST_NONCONST64(st) \ 749 __asm volatile( \ 750 "clruw %1; " \ 751 "sllx %2,32,%0; " \ 752 "or %0,%1,%0; " \ 753 "wr %4,%%g0,%%asi; " \ 754 #st " %0,[%3]%%asi " \ 755 : "=&r" (_vhi) \ 756 : "r" (_vlo), "r" (_vhi), \ 757 "r" ((uint32_t)(loc)), "r" (asi)) 758 759 #if defined(__GNUC__) && defined(__OPTIMIZE__) 760 #define SPARC64_ST_DEF(st, type) \ 761 static __inline void st(paddr_t loc, int asi, type value) \ 762 { \ 763 uint32_t _hi, _pstate; \ 764 if (PHYS_ASI(asi)) { \ 765 _hi = (uint64_t)(loc) >> 32; \ 766 if (__builtin_constant_p(asi)) \ 767 __asm volatile( \ 768 "clruw %3; " \ 769 "sllx %4,32,%0; " \ 770 "rdpr %%pstate,%1; " \ 771 "or %0,%3,%0; " \ 772 "wrpr %1,8,%%pstate; " \ 773 #st " %2,[%0]%5; " \ 774 "wrpr %1,0,%%pstate " \ 775 : "=&r" (_hi), "=&r" (_pstate) \ 776 : "r" (value), "r" ((uint32_t)(loc)), \ 777 "r" (_hi), "n" (asi)); \ 778 else \ 779 SPARC64_ST_PHYS_NONCONST(st); \ 780 } else { \ 781 if (__builtin_constant_p(asi)) \ 782 __asm volatile( \ 783 #st " %0,[%1]%2 " \ 784 : : "r" (value), "r" ((uint32_t)(loc)), \ 785 "n" (asi)); \ 786 else \ 787 SPARC64_ST_NONCONST(st); \ 788 } \ 789 } 790 #define SPARC64_ST_DEF64(st, type) \ 791 static __inline void st(paddr_t loc, int asi, type value) \ 792 { \ 793 uint32_t _vlo, _vhi, _hi; \ 794 _vlo = value; \ 795 _vhi = (uint64_t)(value) >> 32; \ 796 if (PHYS_ASI(asi)) { \ 797 _hi = (uint64_t)(loc) >> 32; \ 798 if (__builtin_constant_p(asi)) \ 799 __asm volatile( \ 800 "clruw %3; " \ 801 "clruw %5; " \ 802 "sllx %4,32,%1; " \ 803 "sllx %6,32,%0; " \ 804 "rdpr %%pstate,%2; " \ 805 "or %1,%3,%1; " \ 806 "or %0,%5,%0; " \ 807 "wrpr %2,8,%%pstate; " \ 808 #st " %1,[%0]%7; " \ 809 "wrpr %2,0,%%pstate " \ 810 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \ 811 : "r" (_vlo), "r" (_vhi), \ 812 "r" ((uint32_t)(loc)), "r" (_hi), \ 813 "n" (asi)); \ 814 else \ 815 SPARC64_ST_PHYS_NONCONST64(st); \ 816 } else { \ 817 if (__builtin_constant_p(asi)) \ 818 __asm volatile( \ 819 "clruw %1; " \ 820 "sllx %2,32,%0; " \ 821 "or %0,%1,%0; " \ 822 #st " %0,[%3]%4 " \ 823 : "=&r" (_vhi) \ 824 : "r" (_vlo), "r" (_vhi), \ 825 "r" ((uint32_t)(loc)), "n" (asi)); \ 826 else \ 827 SPARC64_ST_NONCONST64(st); \ 828 } \ 829 } 830 #else 831 #define SPARC64_ST_DEF(st, type) \ 832 static __inline void st(paddr_t loc, int asi, type value) \ 833 { \ 834 uint32_t _hi, _pstate; \ 835 if (PHYS_ASI(asi)) { \ 836 _hi = (uint64_t)(loc) >> 32; \ 837 SPARC64_ST_PHYS_NONCONST(st); \ 838 } else \ 839 SPARC64_ST_NONCONST(st); \ 840 } 841 #define SPARC64_ST_DEF64(st, type) \ 842 static __inline void st(paddr_t loc, int asi, type value) \ 843 { \ 844 uint32_t _vlo, _vhi, _hi; \ 845 _vlo = value; \ 846 _vhi = (uint64_t)(value) >> 32; \ 847 if (PHYS_ASI(asi)) { \ 848 _hi = (uint64_t)(loc) >> 32; \ 849 SPARC64_ST_PHYS_NONCONST64(st); \ 850 } else \ 851 SPARC64_ST_NONCONST64(st); \ 852 } 853 #endif 854 855 #endif /* __arch64__ */ 856 857 /* store byte to alternate address space */ 858 SPARC64_ST_DEF(stba, uint8_t) 859 /* store half-word to alternate address space */ 860 SPARC64_ST_DEF(stha, uint16_t) 861 /* store unsigned int to alternate address space */ 862 SPARC64_ST_DEF(sta, uint32_t) 863 /* store 64-bit unsigned int to alternate address space */ 864 SPARC64_ST_DEF64(stxa, uint64_t) 865 866 867 /* set dmmu secondary context */ 868 static __inline void 869 dmmu_set_secondary_context(uint ctx) 870 { 871 __asm volatile( 872 "stxa %0,[%1]%2; " 873 "membar #Sync " 874 : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU) 875 : "memory"); 876 } 877 878 /* flush address from data cache */ 879 #define flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc))) 880 881 /* 882 * SPARC V9 memory barrier instructions. 883 */ 884 /* Make all stores complete before next store */ 885 #define membar_StoreStore() __asm volatile("membar #StoreStore" : :) 886 /* Make all loads complete before next store */ 887 #define membar_LoadStore() __asm volatile("membar #LoadStore" : :) 888 /* Make all stores complete before next load */ 889 #define membar_StoreLoad() __asm volatile("membar #StoreLoad" : :) 890 /* Make all loads complete before next load */ 891 #define membar_LoadLoad() __asm volatile("membar #LoadLoad" : :) 892 /* Complete all outstanding memory operations and exceptions */ 893 #define membar_Sync() __asm volatile("membar #Sync" : :) 894 /* Complete all outstanding memory operations */ 895 #define membar_MemIssue() __asm volatile("membar #MemIssue" : :) 896 /* Complete all outstanding stores before any new loads */ 897 #define membar_Lookaside() __asm volatile("membar #Lookaside" : :) 898 899 #define membar_Load() __asm volatile("membar #LoadLoad | #LoadStore" : :) 900 #define membar_Store() __asm volatile("membar #LoadStore | #StoreStore" : :) 901 902 #endif 903 904 #endif /* _SPARC_CTLREG_H_ */ 905
Indexes created Mon Sep 29 21:09:56 GMT 2025