ctlreg.h revision 1.8
1 /* $NetBSD: ctlreg.h,v 1.8 1999/05/22 20:25:49 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the University of 30 * California, Berkeley and its contributors. 31 * 4. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 48 */ 49 50 /* 51 * Sun4u support by Eduardo Horvath 52 * Changes Copyright (c) 1996 Eduardo Horvath 53 * All rights reserved. 54 */ 55 56 /* 57 * Sun 4u control registers. (includes address space definitions 58 * and some registers in control space). 59 */ 60 61 /* 62 * The Alternate address spaces. 63 * 64 * 0x00-0x7f are privileged 65 * 0x80-0xff can be used by users 66 */ 67 68 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 69 70 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 71 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 72 73 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 74 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 75 76 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 77 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 78 79 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 80 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 81 82 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 83 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 84 85 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 86 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 87 88 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 89 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 90 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 91 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 92 93 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 94 95 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 96 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 97 98 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 99 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 100 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 101 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 102 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 103 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 104 105 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 106 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 107 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 108 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 109 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 110 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 111 112 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 113 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 114 115 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 116 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 117 118 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 119 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 120 121 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 122 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 123 124 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 125 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 126 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 127 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 128 129 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 130 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 131 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 132 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 133 134 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 135 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 136 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 137 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 138 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 139 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 140 141 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 142 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 143 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 144 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 145 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 146 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 147 148 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 149 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 150 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 151 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 152 153 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 154 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 155 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 156 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 157 158 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 159 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 160 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 161 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 162 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 163 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 164 165 166 /* 167 * These are the shorter names used by Solaris 168 */ 169 170 #define ASI_N ASI_NUCLEUS 171 #define ASI_NL ASI_NUCLEUS_LITTLE 172 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 173 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 174 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 175 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 176 #define ASI_P ASI_PRIMARY 177 #define ASI_S ASI_SECONDARY 178 #define ASI_PNF ASI_PRIMARY_NO_FAULT 179 #define ASI_SNF ASI_SECONDARY_NO_FAULT 180 #define ASI_PL ASI_PRIMARY_LITTLE 181 #define ASI_SL ASI_SECONDARY_LITTLE 182 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 183 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 184 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 185 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 186 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 187 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 188 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 189 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 190 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 191 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 192 #define ASI_BLK_P ASI_BLOCK_PRIMARY 193 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 194 #define ASI_BLK_S ASI_BLOCK_SECONDARY 195 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 196 197 /* 198 * The following are 4u control registers 199 */ 200 201 /* 202 * [4u] MMU and Cache Control Register (MCCR) 203 * use ASI = 0x45 204 */ 205 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 206 #define MCCR 0x00 207 208 /* MCCR Bits and their meanings */ 209 #define MCCR_DMMU_EN 0x08 210 #define MCCR_IMMU_EN 0x04 211 #define MCCR_DCACHE_EN 0x02 212 #define MCCR_ICACHE_EN 0x01 213 214 215 /* 216 * MMU control registers 217 */ 218 219 /* Choose an MMU */ 220 #define ASI_DMMU 0x58 221 #define ASI_IMMU 0x50 222 223 /* Other assorted MMU ASIs */ 224 #define ASI_IMMU_8KPTR 0x51 225 #define ASI_IMMU_64KPTR 0x52 226 #define ASI_IMMU_DATA_IN 0x54 227 #define ASI_IMMU_TLB_DATA 0x55 228 #define ASI_IMMU_TLB_TAG 0x56 229 #define ASI_DMMU_8KPTR 0x59 230 #define ASI_DMMU_64KPTR 0x5a 231 #define ASI_DMMU_DATA_IN 0x5c 232 #define ASI_DMMU_TLB_DATA 0x5d 233 #define ASI_DMMU_TLB_TAG 0x5e 234 235 /* 236 * The following are the control registers 237 * They work on both MMUs unless noted. 238 * 239 * Register contents are defined later on individual registers. 240 */ 241 #define TSB_TAG_TARGET 0x0 242 #define TLB_DATA_IN 0x0 243 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 244 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 245 #define SFSR 0x18 246 #define SFAR 0x20 /* fault address -- DMMU only */ 247 #define TSB 0x28 248 #define TLB_TAG_ACCESS 0x30 249 #define VIRTUAL_WATCHPOINT 0x38 250 #define PHYSICAL_WATCHPOINT 0x40 251 252 /* Tag Target bits */ 253 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 254 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 255 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 256 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 257 258 /* SFSR bits for both D_SFSR and I_SFSR */ 259 #define SFSR_ASI(x) ((x)>>16) 260 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 261 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 262 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 263 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 264 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 265 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 266 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 267 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 268 #define SFSR_CTXT(x) (((x)>>4)&0x3) 269 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 270 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 271 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 272 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 273 #define SFSR_W 0x00004 /* DMMU: attempted write */ 274 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 275 #define SFSR_FV 0x00001 /* Fault is valid */ 276 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 277 278 #if 0 279 /* Old bits */ 280 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 281 #else 282 /* New bits */ 283 #define SFSR_BITS "\177\20" \ 284 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 285 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 286 #endif 287 288 /* ASFR bits */ 289 #define ASFR_ME 0x100000000LL 290 #define ASFR_PRIV 0x080000000LL 291 #define ASFR_ISAP 0x040000000LL 292 #define ASFR_ETP 0x020000000LL 293 #define ASFR_IVUE 0x010000000LL 294 #define ASFR_TO 0x008000000LL 295 #define ASFR_BERR 0x004000000LL 296 #define ASFR_LDP 0x002000000LL 297 #define ASFR_CP 0x001000000LL 298 #define ASFR_WP 0x000800000LL 299 #define ASFR_EDP 0x000400000LL 300 #define ASFR_UE 0x000200000LL 301 #define ASFR_CE 0x000100000LL 302 #define ASFR_ETS 0x0000f0000LL 303 #define ASFT_P_SYND 0x00000ffffLL 304 305 #define AFSR_BITS "\177\20" \ 306 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 307 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 308 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 309 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 310 311 /* 312 * Here's the spitfire TSB control register bits. 313 * 314 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 315 */ 316 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 317 #define TSB_SIZE_1K 0x01 318 #define TSB_SIZE_2K 0x02 319 #define TSB_SIZE_4K 0x03 320 #define TSB_SIZE_8K 0x04 321 #define TSB_SIZE_16K 0x05 322 #define TSB_SIZE_32K 0x06 323 #define TSB_SIZE_64K 0x07 324 #define TSB_SPLIT 0x1000 325 #define TSB_BASE 0xffffffffffffe000 326 327 /* TLB Tag Access bits */ 328 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 329 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 330 331 /* 332 * TLB demap registers. TTEs are defined in v9pte.h 333 * 334 * Use the address space to select between IMMU and DMMU. 335 * The address of the register selects which context register 336 * to read the ASI from. 337 * 338 * The data stored in the register is interpreted as the VA to 339 * use. The DEMAP_CTX_<> registers ignore the address and demap the 340 * entire ASI. 341 * 342 */ 343 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 344 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 345 346 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 347 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 348 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 349 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 350 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 351 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 352 353 /* 354 * Interrupt registers. This really gets hairy. 355 */ 356 357 /* IRSR -- Interrupt Receive Status Ragister */ 358 #define ASI_IRSR 0x49 359 #define IRSR 0x00 360 #define IRSR_BUSY 0x010 361 #define IRSR_MID(x) (x&0xf) 362 363 /* IRDR -- Interrupt Receive Data Registers */ 364 #define ASI_IRDR 0x7f 365 #define IRDR_0H 0x40 366 #define IRDR_0L 0x48 /* unimplemented */ 367 #define IRDR_1H 0x50 368 #define IRDR_1L 0x58 /* unimplemented */ 369 #define IRDR_2H 0x60 370 #define IRDR_2L 0x68 /* unimplemented */ 371 #define IRDR_3H 0x70 /* unimplemented */ 372 #define IRDR_3L 0x78 /* unimplemented */ 373 374 /* SOFTINT ASRs */ 375 #define SET_SOFTINT %asr20 /* Sets these bits */ 376 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 377 #define SOFTINT %asr22 /* Reads the register */ 378 379 #define TICK_INT 0x01 /* level-14 clock tick */ 380 #define SOFTINT1 (0x1<<1) 381 #define SOFTINT2 (0x1<<2) 382 #define SOFTINT3 (0x1<<3) 383 #define SOFTINT4 (0x1<<4) 384 #define SOFTINT5 (0x1<<5) 385 #define SOFTINT6 (0x1<<6) 386 #define SOFTINT7 (0x1<<7) 387 #define SOFTINT8 (0x1<<8) 388 #define SOFTINT9 (0x1<<9) 389 #define SOFTINT10 (0x1<<10) 390 #define SOFTINT11 (0x1<<11) 391 #define SOFTINT12 (0x1<<12) 392 #define SOFTINT13 (0x1<<13) 393 #define SOFTINT14 (0x1<<14) 394 #define SOFTINT15 (0x1<<15) 395 396 /* Interrupt Dispatch -- usually reserved for cross-calls */ 397 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 398 #define IDSR 0x00 399 #define IDSR_NACK 0x02 400 #define IDSR_BUSY 0x01 401 402 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 403 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 404 #define IDDR_0H 0x40 /* Store data to send in these regs */ 405 #define IDDR_0L 0x48 /* unimplemented */ 406 #define IDDR_1H 0x50 407 #define IDDR_1L 0x58 /* unimplemented */ 408 #define IDDR_2H 0x60 409 #define IDDR_2L 0x68 /* unimplemented */ 410 #define IDDR_3H 0x70 /* unimplemented */ 411 #define IDDR_3L 0x78 /* unimplemented */ 412 413 /* 414 * Error registers 415 */ 416 417 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 418 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 419 #define AFAR 0x00 420 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 421 #define AFSR 0x00 422 423 #define ASI_P_EER 0x4b /* Error enable register */ 424 #define P_EER 0x00 425 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 426 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 427 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 428 429 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 430 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 431 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 432 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 433 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 434 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 435 436 437 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 438 439 /* 440 * GCC __asm constructs for doing assembly stuff. 441 */ 442 443 /* 444 * ``Routines'' to load and store from/to alternate address space. 445 * The location can be a variable, the asi value (address space indicator) 446 * must be a constant. 447 * 448 * N.B.: You can put as many special functions here as you like, since 449 * they cost no kernel space or time if they are not used. 450 * 451 * These were static inline functions, but gcc screws up the constraints 452 * on the address space identifiers (the "n"umeric value part) because 453 * it inlines too late, so we have to use the funny valued-macro syntax. 454 */ 455 456 /* DCACHE_BUG forces a flush of the D$ line on every ASI load */ 457 #define DCACHE_BUG 458 459 /* load byte from alternate address space */ 460 #ifdef DCACHE_BUG 461 #define lduba(loc, asi) ({ \ 462 register int _lduba_v; \ 463 if (asi == ASI_PHYS_CACHED) { \ 464 __asm __volatile("wr %2,%%g0,%%asi; " \ 465 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 466 " lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \ 467 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 468 } else { \ 469 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \ 470 "=r" (_lduba_v) : "r" ((long)(loc)), "r" (asi)); \ 471 } \ 472 _lduba_v; \ 473 }) 474 #else 475 #define lduba(loc, asi) ({ \ 476 register int _lduba_v; \ 477 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \ 478 "r" ((long)(loc)), "r" (asi)); \ 479 _lduba_v; \ 480 }) 481 #endif 482 483 /* load half-word from alternate address space */ 484 #ifdef DCACHE_BUG 485 #define lduha(loc, asi) ({ \ 486 register int _lduha_v; \ 487 if (asi == ASI_PHYS_CACHED) { \ 488 __asm __volatile("wr %2,%%g0,%%asi; " \ 489 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 490 " lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 491 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 492 } else { \ 493 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 494 "r" ((long)(loc)), "r" (asi)); \ 495 } \ 496 _lduha_v; \ 497 }) 498 #else 499 #define lduha(loc, asi) ({ \ 500 register int _lduha_v; \ 501 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 502 "r" ((long)(loc)), "r" (asi)); \ 503 _lduha_v; \ 504 }) 505 #endif 506 507 /* load unsigned int from alternate address space */ 508 #ifdef DCACHE_BUG 509 #define lda(loc, asi) ({ \ 510 register int _lda_v; \ 511 if (asi == ASI_PHYS_CACHED) { \ 512 __asm __volatile("wr %2,%%g0,%%asi; " \ 513 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 514 " lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 515 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 516 } else { \ 517 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 518 "r" ((long)(loc)), "r" (asi)); \ 519 } \ 520 _lda_v; \ 521 }) 522 523 /* load signed int from alternate address space */ 524 #define ldswa(loc, asi) ({ \ 525 register int _lda_v; \ 526 if (asi == ASI_PHYS_CACHED) { \ 527 __asm __volatile("wr %2,%%g0,%%asi; " \ 528 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 529 " ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 530 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 531 } else { \ 532 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 533 "r" ((long)(loc)), "r" (asi)); \ 534 } \ 535 _lda_v; \ 536 }) 537 #else 538 #define lda(loc, asi) ({ \ 539 register int _lda_v; \ 540 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 541 "r" ((long)(loc)), "r" (asi)); \ 542 _lda_v; \ 543 }) 544 545 #define ldswa(loc, asi) ({ \ 546 register int _lda_v; \ 547 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 548 "r" ((long)(loc)), "r" (asi)); \ 549 _lda_v; \ 550 }) 551 #endif 552 553 #ifdef DCACHE_BUG 554 555 /* load 64-bit int from alternate address space */ 556 #define ldda(loc, asi) ({ \ 557 register long long _lda_v; \ 558 if (asi == ASI_PHYS_CACHED) { \ 559 __asm __volatile("wr %2,%%g0,%%asi; " \ 560 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 561 " ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 562 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 563 } else { \ 564 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 565 "r" ((long)(loc)), "r" (asi)); \ 566 } \ 567 _lda_v; \ 568 }) 569 570 #ifdef __arch64__ 571 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 572 #define ldxa(loc, asi) ({ \ 573 register long _lda_v; \ 574 if (asi == ASI_PHYS_CACHED) { \ 575 __asm __volatile("wr %2,%%g0,%%asi; "\ 576 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 577 " ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 578 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 579 } else { \ 580 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 581 "r" ((long)(loc)), "r" (asi)); \ 582 } \ 583 _lda_v; \ 584 }) 585 #else 586 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 587 #define ldxa(loc, asi) ({ \ 588 volatile register long _ldxa_lo, _ldxa_hi; \ 589 if (asi == ASI_PHYS_CACHED) { \ 590 __asm __volatile("wr %3,%%g0,%%asi; " \ 591 " andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 592 " ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0" : \ 593 "=r" (_ldxa_lo), "=r" (_ldxa_hi) : \ 594 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 595 } else { \ 596 __asm __volatile("wr %3,%%g0,%%asi; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 597 "=r" (_ldxa_lo), "=r" (_ldxa_hi) : \ 598 "r" ((long)(loc)), "r" (asi)); \ 599 } \ 600 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 601 }) 602 #endif 603 604 #else 605 606 /* load 64-bit int from alternate address space */ 607 #define ldda(loc, asi) ({ \ 608 register long long _lda_v; \ 609 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 610 "r" ((long)(loc)), "r" (asi)); \ 611 _lda_v; \ 612 }) 613 614 #ifdef __arch64__ 615 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 616 #define ldxa(loc, asi) ({ \ 617 register long _lda_v; \ 618 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 619 "r" ((long)(loc)), "r" (asi)); \ 620 _lda_v; \ 621 }) 622 #else 623 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 624 #define ldxa(loc, asi) ({ \ 625 volatile register long _ldxa_lo, _ldxa_hi; \ 626 __asm __volatile("wr %3,%%g0,%%asi; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 627 "=r" (_ldxa_lo), "=r" (_ldxa_hi) : \ 628 "r" ((long)(loc)), "r" (asi)); \ 629 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 630 }) 631 #endif 632 #endif 633 634 635 /* store byte to alternate address space */ 636 #define stba(loc, asi, value) ({ \ 637 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 638 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 639 }) 640 641 /* store half-word to alternate address space */ 642 #define stha(loc, asi, value) ({ \ 643 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 644 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 645 }) 646 647 /* store int to alternate address space */ 648 #define sta(loc, asi, value) ({ \ 649 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 650 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 651 }) 652 653 /* store 64-bit int to alternate address space */ 654 #define stda(loc, asi, value) ({ \ 655 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 656 "r" ((long long)(value)), "r" ((long)(loc)), "r" (asi)); \ 657 }) 658 659 #ifdef __arch64__ 660 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 661 #define stxa(loc, asi, value) ({ \ 662 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 663 "r" ((long)(value)), "r" ((long)(loc)), "r" (asi)); \ 664 }) 665 #else 666 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 667 #define stxa(loc, asi, value) ({ \ 668 int64_t _stxa_v; \ 669 int64_t *_stxa_a = &_stxa_v; \ 670 _stxa_v = value; \ 671 __asm __volatile("wr %2,%%g0,%%asi; ldx [%0],%3; stxa %3,[%1]%%asi" : : \ 672 "r" ((long)(_stxa_a)), "r" ((long)(loc)), "r" (asi), "r" ((long)(_stxa_v))); \ 673 }) 674 #endif 675 676 /* flush address from data cache */ 677 #define flush(loc) ({ \ 678 __asm __volatile("flush %0" : : \ 679 "r" ((long)(loc))); \ 680 }) 681 682 /* Flush a D$ line */ 683 #if 0 684 #define flushline(loc) ({ \ 685 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 686 membar_sync(); \ 687 }) 688 #else 689 #define flushline(loc) 690 #endif 691 692 /* The following two enable or disable the dcache in the LSU control register */ 693 #define dcenable() ({ \ 694 int res; \ 695 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 696 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 697 }) 698 #define dcdisable() ({ \ 699 int res; \ 700 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 701 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 702 }) 703 704 /* 705 * SPARC V9 memory barrier instructions. 706 */ 707 /* Make all stores complete before next store */ 708 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 709 /* Make all loads complete before next store */ 710 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 711 /* Make all stores complete before next load */ 712 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 713 /* Make all loads complete before next load */ 714 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 715 /* Complete all outstanding memory operations and exceptions */ 716 #define membar_sync() __asm __volatile("membar #Sync" : :) 717 /* Complete all outstanding memory operations */ 718 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 719 /* Complete all outstanding stores before any new loads */ 720 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 721 722 #ifdef __arch64__ 723 /* read 64-bit %tick register */ 724 #define tick() ({ \ 725 register u_long _tick_tmp; \ 726 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 727 _tick_tmp; \ 728 }) 729 #else 730 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 731 #define tick() ({ \ 732 volatile register u_long _tick_tmp = 0; \ 733 volatile u_int64_t _tick_v; \ 734 volatile u_int64_t *_tick_a = &_tick_v; \ 735 __asm __volatile("rdpr %%tick, %0; stx %0,[%1]; membar #StoreLoad" : "=r" (_tick_tmp) : \ 736 "r" ((long)(_tick_a))); \ 737 _tick_v; \ 738 }) 739 #endif 740 741
Indexes created Mon Sep 29 21:09:56 GMT 2025