ctlreg.h revision 1.9
1 /* $NetBSD: ctlreg.h,v 1.9 1999/05/30 19:11:33 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the University of 30 * California, Berkeley and its contributors. 31 * 4. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 48 */ 49 50 /* 51 * Sun4u support by Eduardo Horvath 52 * Changes Copyright (c) 1996 Eduardo Horvath 53 * All rights reserved. 54 */ 55 56 /* 57 * Sun 4u control registers. (includes address space definitions 58 * and some registers in control space). 59 */ 60 61 /* 62 * The Alternate address spaces. 63 * 64 * 0x00-0x7f are privileged 65 * 0x80-0xff can be used by users 66 */ 67 68 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */ 69 70 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */ 71 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */ 72 73 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */ 74 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */ 75 76 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */ 77 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */ 78 79 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */ 80 #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */ 81 82 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */ 83 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */ 84 85 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */ 86 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */ 87 88 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */ 89 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */ 90 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */ 91 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */ 92 93 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */ 94 95 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */ 96 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */ 97 98 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */ 99 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */ 100 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */ 101 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */ 102 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ 103 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ 104 105 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ 106 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ 107 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ 108 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */ 109 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */ 110 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */ 111 112 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */ 113 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */ 114 115 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */ 116 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */ 117 118 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */ 119 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */ 120 121 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */ 122 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */ 123 124 #define ASI_PRIMARY 0x80 /* [4u] primary address space */ 125 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */ 126 #define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */ 127 #define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */ 128 129 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */ 130 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */ 131 #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */ 132 #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */ 133 134 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */ 135 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */ 136 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */ 137 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */ 138 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */ 139 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */ 140 141 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */ 142 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */ 143 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */ 144 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */ 145 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */ 146 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */ 147 148 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */ 149 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */ 150 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */ 151 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */ 152 153 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */ 154 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */ 155 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */ 156 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */ 157 158 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */ 159 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */ 160 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */ 161 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */ 162 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */ 163 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */ 164 165 166 /* 167 * These are the shorter names used by Solaris 168 */ 169 170 #define ASI_N ASI_NUCLEUS 171 #define ASI_NL ASI_NUCLEUS_LITTLE 172 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY 173 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY 174 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE 175 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE 176 #define ASI_P ASI_PRIMARY 177 #define ASI_S ASI_SECONDARY 178 #define ASI_PNF ASI_PRIMARY_NO_FAULT 179 #define ASI_SNF ASI_SECONDARY_NO_FAULT 180 #define ASI_PL ASI_PRIMARY_LITTLE 181 #define ASI_SL ASI_SECONDARY_LITTLE 182 #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE 183 #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE 184 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY 185 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 186 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY 187 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 188 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY 189 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY 190 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY 191 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY 192 #define ASI_BLK_P ASI_BLOCK_PRIMARY 193 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE 194 #define ASI_BLK_S ASI_BLOCK_SECONDARY 195 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE 196 197 /* 198 * The following are 4u control registers 199 */ 200 201 /* 202 * [4u] MMU and Cache Control Register (MCCR) 203 * use ASI = 0x45 204 */ 205 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER 206 #define MCCR 0x00 207 208 /* MCCR Bits and their meanings */ 209 #define MCCR_DMMU_EN 0x08 210 #define MCCR_IMMU_EN 0x04 211 #define MCCR_DCACHE_EN 0x02 212 #define MCCR_ICACHE_EN 0x01 213 214 215 /* 216 * MMU control registers 217 */ 218 219 /* Choose an MMU */ 220 #define ASI_DMMU 0x58 221 #define ASI_IMMU 0x50 222 223 /* Other assorted MMU ASIs */ 224 #define ASI_IMMU_8KPTR 0x51 225 #define ASI_IMMU_64KPTR 0x52 226 #define ASI_IMMU_DATA_IN 0x54 227 #define ASI_IMMU_TLB_DATA 0x55 228 #define ASI_IMMU_TLB_TAG 0x56 229 #define ASI_DMMU_8KPTR 0x59 230 #define ASI_DMMU_64KPTR 0x5a 231 #define ASI_DMMU_DATA_IN 0x5c 232 #define ASI_DMMU_TLB_DATA 0x5d 233 #define ASI_DMMU_TLB_TAG 0x5e 234 235 /* 236 * The following are the control registers 237 * They work on both MMUs unless noted. 238 * 239 * Register contents are defined later on individual registers. 240 */ 241 #define TSB_TAG_TARGET 0x0 242 #define TLB_DATA_IN 0x0 243 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */ 244 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */ 245 #define SFSR 0x18 246 #define SFAR 0x20 /* fault address -- DMMU only */ 247 #define TSB 0x28 248 #define TLB_TAG_ACCESS 0x30 249 #define VIRTUAL_WATCHPOINT 0x38 250 #define PHYSICAL_WATCHPOINT 0x40 251 252 /* Tag Target bits */ 253 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL 254 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK) 255 #define TAG_TARGET_CONTEXT(x) ((x)>>48) 256 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK)) 257 258 /* SFSR bits for both D_SFSR and I_SFSR */ 259 #define SFSR_ASI(x) ((x)>>16) 260 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */ 261 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */ 262 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */ 263 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */ 264 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */ 265 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */ 266 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */ 267 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */ 268 #define SFSR_CTXT(x) (((x)>>4)&0x3) 269 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00) 270 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01) 271 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02) 272 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */ 273 #define SFSR_W 0x00004 /* DMMU: attempted write */ 274 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */ 275 #define SFSR_FV 0x00001 /* Fault is valid */ 276 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV) 277 278 #if 0 279 /* Old bits */ 280 #define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV" 281 #else 282 /* New bits */ 283 #define SFSR_BITS "\177\20" \ 284 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \ 285 "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0" 286 #endif 287 288 /* ASFR bits */ 289 #define ASFR_ME 0x100000000LL 290 #define ASFR_PRIV 0x080000000LL 291 #define ASFR_ISAP 0x040000000LL 292 #define ASFR_ETP 0x020000000LL 293 #define ASFR_IVUE 0x010000000LL 294 #define ASFR_TO 0x008000000LL 295 #define ASFR_BERR 0x004000000LL 296 #define ASFR_LDP 0x002000000LL 297 #define ASFR_CP 0x001000000LL 298 #define ASFR_WP 0x000800000LL 299 #define ASFR_EDP 0x000400000LL 300 #define ASFR_UE 0x000200000LL 301 #define ASFR_CE 0x000100000LL 302 #define ASFR_ETS 0x0000f0000LL 303 #define ASFT_P_SYND 0x00000ffffLL 304 305 #define AFSR_BITS "\177\20" \ 306 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \ 307 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \ 308 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \ 309 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0" 310 311 /* 312 * Here's the spitfire TSB control register bits. 313 * 314 * Each TSB entry is 16-bytes wide. The TSB must be size aligned 315 */ 316 #define TSB_SIZE_512 0x0 /* 8kB, etc. */ 317 #define TSB_SIZE_1K 0x01 318 #define TSB_SIZE_2K 0x02 319 #define TSB_SIZE_4K 0x03 320 #define TSB_SIZE_8K 0x04 321 #define TSB_SIZE_16K 0x05 322 #define TSB_SIZE_32K 0x06 323 #define TSB_SIZE_64K 0x07 324 #define TSB_SPLIT 0x1000 325 #define TSB_BASE 0xffffffffffffe000 326 327 /* TLB Tag Access bits */ 328 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000 329 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff 330 331 /* 332 * TLB demap registers. TTEs are defined in v9pte.h 333 * 334 * Use the address space to select between IMMU and DMMU. 335 * The address of the register selects which context register 336 * to read the ASI from. 337 * 338 * The data stored in the register is interpreted as the VA to 339 * use. The DEMAP_CTX_<> registers ignore the address and demap the 340 * entire ASI. 341 * 342 */ 343 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */ 344 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */ 345 346 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */ 347 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */ 348 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */ 349 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */ 350 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */ 351 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */ 352 353 /* 354 * Interrupt registers. This really gets hairy. 355 */ 356 357 /* IRSR -- Interrupt Receive Status Ragister */ 358 #define ASI_IRSR 0x49 359 #define IRSR 0x00 360 #define IRSR_BUSY 0x010 361 #define IRSR_MID(x) (x&0xf) 362 363 /* IRDR -- Interrupt Receive Data Registers */ 364 #define ASI_IRDR 0x7f 365 #define IRDR_0H 0x40 366 #define IRDR_0L 0x48 /* unimplemented */ 367 #define IRDR_1H 0x50 368 #define IRDR_1L 0x58 /* unimplemented */ 369 #define IRDR_2H 0x60 370 #define IRDR_2L 0x68 /* unimplemented */ 371 #define IRDR_3H 0x70 /* unimplemented */ 372 #define IRDR_3L 0x78 /* unimplemented */ 373 374 /* SOFTINT ASRs */ 375 #define SET_SOFTINT %asr20 /* Sets these bits */ 376 #define CLEAR_SOFTINT %asr21 /* Clears these bits */ 377 #define SOFTINT %asr22 /* Reads the register */ 378 #define TICK_CMPR %asr23 379 380 #define TICK_INT 0x01 /* level-14 clock tick */ 381 #define SOFTINT1 (0x1<<1) 382 #define SOFTINT2 (0x1<<2) 383 #define SOFTINT3 (0x1<<3) 384 #define SOFTINT4 (0x1<<4) 385 #define SOFTINT5 (0x1<<5) 386 #define SOFTINT6 (0x1<<6) 387 #define SOFTINT7 (0x1<<7) 388 #define SOFTINT8 (0x1<<8) 389 #define SOFTINT9 (0x1<<9) 390 #define SOFTINT10 (0x1<<10) 391 #define SOFTINT11 (0x1<<11) 392 #define SOFTINT12 (0x1<<12) 393 #define SOFTINT13 (0x1<<13) 394 #define SOFTINT14 (0x1<<14) 395 #define SOFTINT15 (0x1<<15) 396 397 /* Interrupt Dispatch -- usually reserved for cross-calls */ 398 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */ 399 #define IDSR 0x00 400 #define IDSR_NACK 0x02 401 #define IDSR_BUSY 0x01 402 403 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */ 404 #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */ 405 #define IDDR_0H 0x40 /* Store data to send in these regs */ 406 #define IDDR_0L 0x48 /* unimplemented */ 407 #define IDDR_1H 0x50 408 #define IDDR_1L 0x58 /* unimplemented */ 409 #define IDDR_2H 0x60 410 #define IDDR_2L 0x68 /* unimplemented */ 411 #define IDDR_3H 0x70 /* unimplemented */ 412 #define IDDR_3L 0x78 /* unimplemented */ 413 414 /* 415 * Error registers 416 */ 417 418 /* Since we won't try to fix async errs, we don't care about the bits in the regs */ 419 #define ASI_AFAR 0x4d /* Asynchronous fault address register */ 420 #define AFAR 0x00 421 #define ASI_AFSR 0x4c /* Asynchronous fault status register */ 422 #define AFSR 0x00 423 424 #define ASI_P_EER 0x4b /* Error enable register */ 425 #define P_EER 0x00 426 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */ 427 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */ 428 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */ 429 430 #define ASI_DATAPATH_READ 0x7f /* Read the regs */ 431 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */ 432 #define P_DPER_0 0x00 /* Datapath err reg 0 */ 433 #define P_DPER_1 0x18 /* Datapath err reg 1 */ 434 #define P_DCR_0 0x20 /* Datapath control reg 0 */ 435 #define P_DCR_1 0x38 /* Datapath control reg 0 */ 436 437 438 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */ 439 440 /* 441 * GCC __asm constructs for doing assembly stuff. 442 */ 443 444 /* 445 * ``Routines'' to load and store from/to alternate address space. 446 * The location can be a variable, the asi value (address space indicator) 447 * must be a constant. 448 * 449 * N.B.: You can put as many special functions here as you like, since 450 * they cost no kernel space or time if they are not used. 451 * 452 * These were static inline functions, but gcc screws up the constraints 453 * on the address space identifiers (the "n"umeric value part) because 454 * it inlines too late, so we have to use the funny valued-macro syntax. 455 */ 456 457 /* DCACHE_BUG forces a flush of the D$ line on every ASI load */ 458 #define DCACHE_BUG 459 460 #ifdef __arch64__ 461 /* load byte from alternate address space */ 462 #ifdef DCACHE_BUG 463 #define lduba(loc, asi) ({ \ 464 register int _lduba_v; \ 465 if (asi == ASI_PHYS_CACHED) { \ 466 __asm __volatile("wr %2,%%g0,%%asi; " \ 467 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 468 " lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \ 469 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 470 } else { \ 471 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \ 472 "r" ((long)(loc)), "r" (asi)); \ 473 } \ 474 _lduba_v; \ 475 }) 476 #else 477 #define lduba(loc, asi) ({ \ 478 register int _lduba_v; \ 479 __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \ 480 "r" ((long)(loc)), "r" (asi)); \ 481 _lduba_v; \ 482 }) 483 #endif 484 #else 485 /* load byte from alternate address space */ 486 #ifdef DCACHE_BUG 487 #define lduba(loc, asi) ({ \ 488 register int _lduba_v, _loc_hi; \ 489 _loc_hi = (((u_int64_t)loc)>>32); \ 490 if (asi == ASI_PHYS_CACHED) { \ 491 __asm __volatile("wr %3,%%g0,%%asi; " \ 492 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 493 " sllx %2,32,%0; or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 494 "r" ((long)(loc)), "r" (_loc_hi), \ 495 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 496 } else { \ 497 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 498 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 499 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 500 } \ 501 _lduba_v; \ 502 }) 503 #else 504 #define lduba(loc, asi) ({ \ 505 register int _lduba_v, _loc_hi; \ 506 _loc_hi = (((u_int64_t)loc)>>32); \ 507 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 508 " or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \ 509 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 510 _lduba_v; \ 511 }) 512 #endif 513 #endif 514 515 #ifdef __arch64__ 516 /* load half-word from alternate address space */ 517 #ifdef DCACHE_BUG 518 #define lduha(loc, asi) ({ \ 519 register int _lduha_v; \ 520 if (asi == ASI_PHYS_CACHED) { \ 521 __asm __volatile("wr %2,%%g0,%%asi; " \ 522 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 523 " lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \ 524 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 525 } else { \ 526 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 527 "r" ((long)(loc)), "r" (asi)); \ 528 } \ 529 _lduha_v; \ 530 }) 531 #else 532 #define lduha(loc, asi) ({ \ 533 register int _lduha_v; \ 534 __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \ 535 "r" ((long)(loc)), "r" (asi)); \ 536 _lduha_v; \ 537 }) 538 #endif 539 #else 540 /* load half-word from alternate address space */ 541 #ifdef DCACHE_BUG 542 #define lduha(loc, asi) ({ \ 543 register int _lduha_v, _loc_hi; \ 544 _loc_hi = (((u_int64_t)loc)>>32); \ 545 if (asi == ASI_PHYS_CACHED) { \ 546 __asm __volatile("wr %3,%%g0,%%asi; " \ 547 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 548 " sllx %2,32,%0; or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 549 "r" ((long)(loc)), "r" (_loc_hi), \ 550 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 551 } else { \ 552 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 553 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 554 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 555 } \ 556 _lduha_v; \ 557 }) 558 #else 559 #define lduha(loc, asi) ({ \ 560 register int _lduha_v, _loc_hi; \ 561 _loc_hi = (((u_int64_t)loc)>>32); \ 562 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 563 " or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \ 564 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 565 _lduha_v; \ 566 }) 567 #endif 568 #endif 569 570 #ifdef __arch64__ 571 /* load unsigned int from alternate address space */ 572 #ifdef DCACHE_BUG 573 #define lda(loc, asi) ({ \ 574 register int _lda_v; \ 575 if (asi == ASI_PHYS_CACHED) { \ 576 __asm __volatile("wr %2,%%g0,%%asi; " \ 577 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 578 " lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 579 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 580 } else { \ 581 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 582 "r" ((long)(loc)), "r" (asi)); \ 583 } \ 584 _lda_v; \ 585 }) 586 587 /* load signed int from alternate address space */ 588 #define ldswa(loc, asi) ({ \ 589 register int _lda_v; \ 590 if (asi == ASI_PHYS_CACHED) { \ 591 __asm __volatile("wr %2,%%g0,%%asi; " \ 592 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 593 " ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 594 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 595 } else { \ 596 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 597 "r" ((long)(loc)), "r" (asi)); \ 598 } \ 599 _lda_v; \ 600 }) 601 #else 602 #define lda(loc, asi) ({ \ 603 register int _lda_v; \ 604 __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \ 605 "r" ((long)(loc)), "r" (asi)); \ 606 _lda_v; \ 607 }) 608 609 #define ldswa(loc, asi) ({ \ 610 register int _lda_v; \ 611 __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \ 612 "r" ((long)(loc)), "r" (asi)); \ 613 _lda_v; \ 614 }) 615 #endif 616 #else /* __arch64__ */ 617 /* load unsigned int from alternate address space */ 618 #ifdef DCACHE_BUG 619 #define lda(loc, asi) ({ \ 620 register int _lda_v, _loc_hi; \ 621 _loc_hi = (((u_int64_t)loc)>>32); \ 622 if (asi == ASI_PHYS_CACHED) { \ 623 __asm __volatile("wr %3,%%g0,%%asi; " \ 624 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 625 " sllx %2,32,%0; or %0,%1,%0; lda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 626 "r" ((long)(loc)), "r" (_loc_hi), \ 627 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 628 } else { \ 629 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 630 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 631 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 632 } \ 633 _lda_v; \ 634 }) 635 636 /* load signed int from alternate address space */ 637 #define ldswa(loc, asi) ({ \ 638 register int _lda_v, _loc_hi; \ 639 _loc_hi = (((u_int64_t)loc)>>32); \ 640 if (asi == ASI_PHYS_CACHED) { \ 641 __asm __volatile("wr %3,%%g0,%%asi; " \ 642 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 643 " sllx %2,32,%0; or %0,%1,%0; ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 644 "r" ((long)(loc)), "r" (_loc_hi), \ 645 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 646 } else { \ 647 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 648 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 649 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 650 } \ 651 _lda_v; \ 652 }) 653 #else 654 #define lda(loc, asi) ({ \ 655 register int _lda_v, _loc_hi; \ 656 _loc_hi = (((u_int64_t)loc)>>32); \ 657 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 658 " or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 659 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 660 _lda_v; \ 661 }) 662 663 #define ldswa(loc, asi) ({ \ 664 register int _lda_v, _loc_hi; \ 665 _loc_hi = (((u_int64_t)loc)>>32); \ 666 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 667 " or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \ 668 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 669 _lda_v; \ 670 }) 671 #endif 672 #endif /* __arch64__ */ 673 674 #ifdef DCACHE_BUG 675 676 #ifdef __arch64__ 677 /* load 64-bit int from alternate address space */ 678 #define ldda(loc, asi) ({ \ 679 register long long _lda_v; \ 680 if (asi == ASI_PHYS_CACHED) { \ 681 __asm __volatile("wr %2,%%g0,%%asi; " \ 682 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 683 " ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \ 684 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 685 } else { \ 686 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 687 "r" ((long)(loc)), "r" (asi)); \ 688 } \ 689 _lda_v; \ 690 }) 691 #else 692 /* load 64-bit int from alternate address space */ 693 #define ldda(loc, asi) ({ \ 694 register long long _lda_v, _loc_hi; \ 695 _loc_hi = (((u_int64_t)loc)>>32); \ 696 if (asi == ASI_PHYS_CACHED) { \ 697 __asm __volatile("wr %3,%%g0,%%asi; " \ 698 " andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \ 699 " sllx %2,32,%0; or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 700 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 701 } else { \ 702 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 703 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 704 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 705 } \ 706 _lda_v; \ 707 }) 708 #endif 709 710 #ifdef __arch64__ 711 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 712 #define ldxa(loc, asi) ({ \ 713 register long _lda_v; \ 714 if (asi == ASI_PHYS_CACHED) { \ 715 __asm __volatile("wr %2,%%g0,%%asi; "\ 716 " andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \ 717 " ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \ 718 "r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \ 719 } else { \ 720 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 721 "r" ((long)(loc)), "r" (asi)); \ 722 } \ 723 _lda_v; \ 724 }) 725 #else 726 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 727 #define ldxa(loc, asi) ({ \ 728 volatile register long _ldxa_lo, _ldxa_hi, _loc_hi; \ 729 _loc_hi = (((u_int64_t)loc)>>32); \ 730 if (asi == ASI_PHYS_CACHED) { \ 731 __asm __volatile("wr %4,%%g0,%%asi; " \ 732 " andn %2,0x1f,%0; stxa %%g0,[%0] %5; membar #Sync; " \ 733 " sllx %2,32,%0; or %0,%1,%0; ldxa [%0]%%asi,%0; " \ 734 " srlx %0,32,%1; srl %0,0,%0" : \ 735 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 736 "r" ((long)(loc)), "r" (_loc_hi), \ 737 "r" (asi), "n" (ASI_DCACHE_TAG)); \ 738 } else { \ 739 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \ 740 " or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 741 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 742 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 743 } \ 744 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 745 }) 746 #endif 747 748 #else 749 750 #ifdef __arch64__ 751 /* load 64-bit int from alternate address space */ 752 #define ldda(loc, asi) ({ \ 753 register long long _lda_v; \ 754 __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \ 755 "r" ((long)(loc)), "r" (asi)); \ 756 _lda_v; \ 757 }) 758 #else 759 #define ldda(loc, asi) ({ \ 760 register long long _lda_v, _loc_hi; \ 761 _loc_hi = (((u_int64_t)loc)>>32); \ 762 __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \ 763 " or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \ 764 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 765 _lda_v; \ 766 }) 767 #endif 768 769 #ifdef __arch64__ 770 /* native load 64-bit int from alternate address space w/64-bit compiler*/ 771 #define ldxa(loc, asi) ({ \ 772 register long _lda_v; \ 773 __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \ 774 "r" ((long)(loc)), "r" (asi)); \ 775 _lda_v; \ 776 }) 777 #else 778 /* native load 64-bit int from alternate address space w/32-bit compiler*/ 779 #define ldxa(loc, asi) ({ \ 780 volatile register long _ldxa_lo, _ldxa_hi, _loc_hi; \ 781 _loc_hi = (((u_int64_t)loc)>>32); \ 782 __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \ 783 " or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \ 784 "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \ 785 "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 786 ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \ 787 }) 788 #endif 789 #endif 790 791 792 /* store byte to alternate address space */ 793 #ifdef __arch64__ 794 #define stba(loc, asi, value) ({ \ 795 __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \ 796 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 797 }) 798 #else 799 #define stba(loc, asi, value) ({ \ 800 register int _loc_hi; \ 801 _loc_hi = (((u_int64_t)loc)>>32); \ 802 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 803 " or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 804 "r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 805 }) 806 #endif 807 808 /* store half-word to alternate address space */ 809 #ifdef __arch64__ 810 #define stha(loc, asi, value) ({ \ 811 __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \ 812 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 813 }) 814 #else 815 #define stha(loc, asi, value) ({ \ 816 register int _loc_hi; \ 817 _loc_hi = (((u_int64_t)loc)>>32); \ 818 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 819 " or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 820 "r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \ 821 }) 822 #endif 823 824 /* store int to alternate address space */ 825 #ifdef __arch64__ 826 #define sta(loc, asi, value) ({ \ 827 __asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \ 828 "r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \ 829 }) 830 #else 831 #define sta(loc, asi, value) ({ \ 832 register int _loc_hi; \ 833 _loc_hi = (((u_int64_t)loc)>>32); \ 834 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 835 " or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 836 "r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ 837 }) 838 #endif 839 840 /* store 64-bit int to alternate address space */ 841 #ifdef __arch64__ 842 #define stda(loc, asi, value) ({ \ 843 __asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \ 844 "r" ((long long)(value)), "r" ((long)(loc)), "r" (asi)); \ 845 }) 846 #else 847 #define stda(loc, asi, value) ({ \ 848 register int _loc_hi; \ 849 _loc_hi = (((u_int64_t)loc)>>32); \ 850 __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \ 851 " or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \ 852 "r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ 853 }) 854 #endif 855 856 #ifdef __arch64__ 857 /* native store 64-bit int to alternate address space w/64-bit compiler*/ 858 #define stxa(loc, asi, value) ({ \ 859 __asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi" : : \ 860 "r" ((long)(value)), "r" ((long)(loc)), "r" (asi)); \ 861 }) 862 #else 863 /* native store 64-bit int to alternate address space w/32-bit compiler*/ 864 #define stxa(loc, asi, value) ({ \ 865 int _stxa_lo, _stxa_hi, _loc_hi; \ 866 _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \ 867 _loc_hi = (((u_int64_t)loc)>>32); \ 868 __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \ 869 " or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \ 870 "=&r" (_loc_hi), "=&r" (_stxa_hi) : \ 871 "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \ 872 "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \ 873 }) 874 #endif 875 876 /* flush address from data cache */ 877 #define flush(loc) ({ \ 878 __asm __volatile("flush %0" : : \ 879 "r" ((long)(loc))); \ 880 }) 881 882 /* Flush a D$ line */ 883 #if 0 884 #define flushline(loc) ({ \ 885 stxa(((paddr_t)loc)&(~0x1f), (ASI_DCACHE_TAG), 0); \ 886 membar_sync(); \ 887 }) 888 #else 889 #define flushline(loc) 890 #endif 891 892 /* The following two enable or disable the dcache in the LSU control register */ 893 #define dcenable() ({ \ 894 int res; \ 895 __asm __volatile("ldxa [%%g0] %1,%0; or %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 896 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 897 }) 898 #define dcdisable() ({ \ 899 int res; \ 900 __asm __volatile("ldxa [%%g0] %1,%0; andn %0,%2,%0; stxa %0,[%%g0] %1; membar #Sync" \ 901 : "r" (res) : "n" (ASI_MCCR), "n" (MCCR_DCACHE_EN)); \ 902 }) 903 904 /* 905 * SPARC V9 memory barrier instructions. 906 */ 907 /* Make all stores complete before next store */ 908 #define membar_storestore() __asm __volatile("membar #StoreStore" : :) 909 /* Make all loads complete before next store */ 910 #define membar_loadstore() __asm __volatile("membar #LoadStore" : :) 911 /* Make all stores complete before next load */ 912 #define membar_storeload() __asm __volatile("membar #StoreLoad" : :) 913 /* Make all loads complete before next load */ 914 #define membar_loadload() __asm __volatile("membar #LoadLoad" : :) 915 /* Complete all outstanding memory operations and exceptions */ 916 #define membar_sync() __asm __volatile("membar #Sync" : :) 917 /* Complete all outstanding memory operations */ 918 #define membar_memissue() __asm __volatile("membar #MemIssue" : :) 919 /* Complete all outstanding stores before any new loads */ 920 #define membar_lookaside() __asm __volatile("membar #Lookaside" : :) 921 922 #ifdef __arch64__ 923 /* read 64-bit %tick register */ 924 #define tick() ({ \ 925 register u_long _tick_tmp; \ 926 __asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \ 927 _tick_tmp; \ 928 }) 929 #else 930 /* read 64-bit %tick register on 32-bit system */ 931 #define tick() ({ \ 932 volatile register u_long _tick_tmp = 0; \ 933 volatile u_int64_t _tick_v; \ 934 volatile u_int64_t *_tick_a = &_tick_v; \ 935 __asm __volatile("rdpr %%tick, %0; stx %0,[%1]; membar #StoreLoad" : "=r" (_tick_tmp) : \ 936 "r" ((long)(_tick_a))); \ 937 _tick_v; \ 938 }) 939 #endif 940 941 #ifndef _LOCORE 942 extern next_tick __P((long)); 943 #endif 944
Indexes created Mon Sep 29 21:09:56 GMT 2025