hypervisor.h revision 1.2.6.2
1 /* $NetBSD: hypervisor.h,v 1.2.6.2 2014/05/22 11:40:09 yamt Exp $ */ 2 /* $OpenBSD: hypervisor.h,v 1.14 2011/06/26 17:23:46 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2008 Mark Kettenis 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * UltraSPARC Hypervisor API. 22 */ 23 24 /* 25 * API versioning 26 */ 27 28 int64_t hv_api_get_version(uint64_t api_group, 29 uint64_t *major_number, uint64_t *minor_number); 30 31 /* 32 * Domain services 33 */ 34 35 int64_t hv_mach_desc(paddr_t buffer, psize_t *length); 36 37 /* 38 * CPU services 39 */ 40 41 void hv_cpu_yield(void); 42 int64_t hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries); 43 44 #define CPU_MONDO_QUEUE 0x3c 45 #define DEVICE_MONDO_QUEUE 0x3d 46 47 int64_t hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data); 48 int64_t hv_cpu_myid(uint64_t *cpuid); 49 50 /* 51 * MMU services 52 */ 53 54 int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags); 55 int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags); 56 int64_t hv_mmu_demap_all(uint64_t flags); 57 int64_t hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags); 58 int64_t hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags); 59 int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte, 60 uint64_t flags); 61 int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags); 62 63 #define MAP_DTLB 0x1 64 #define MAP_ITLB 0x2 65 66 struct tsb_desc { 67 uint16_t td_idxpgsz; 68 uint16_t td_assoc; 69 uint32_t td_size; 70 uint32_t td_ctxidx; 71 uint32_t td_pgsz; 72 paddr_t td_pa; 73 uint64_t td_reserved; 74 }; 75 76 int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr); 77 int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr); 78 79 /* 80 * Cache and memory services 81 */ 82 83 int64_t hv_mem_scrub(paddr_t raddr, psize_t length); 84 int64_t hv_mem_sync(paddr_t raddr, psize_t length); 85 86 /* 87 * Device interrupt services 88 */ 89 90 int64_t hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino, 91 uint64_t *sysino); 92 int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled); 93 int64_t hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled); 94 int64_t hv_intr_getstate(uint64_t sysino, uint64_t *intr_state); 95 int64_t hv_intr_setstate(uint64_t sysino, uint64_t intr_state); 96 int64_t hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid); 97 int64_t hv_intr_settarget(uint64_t sysino, uint64_t cpuid); 98 99 #define INTR_DISABLED 0 100 #define INTR_ENABLED 1 101 102 #define INTR_IDLE 0 103 #define INTR_RECEIVED 1 104 #define INTR_DELIVERED 2 105 106 int64_t hv_vintr_getcookie(uint64_t devhandle, uint64_t devino, 107 uint64_t *cookie_value); 108 int64_t hv_vintr_setcookie(uint64_t devhandle, uint64_t devino, 109 uint64_t cookie_value); 110 int64_t hv_vintr_getenabled(uint64_t devhandle, uint64_t devino, 111 uint64_t *intr_enabled); 112 int64_t hv_vintr_setenabled(uint64_t devhandle, uint64_t devino, 113 uint64_t intr_enabled); 114 int64_t hv_vintr_getstate(uint64_t devhandle, uint64_t devino, 115 uint64_t *intr_state); 116 int64_t hv_vintr_setstate(uint64_t devhandle, uint64_t devino, 117 uint64_t intr_state); 118 int64_t hv_vintr_gettarget(uint64_t devhandle, uint64_t devino, 119 uint64_t *cpuid); 120 int64_t hv_vintr_settarget(uint64_t devhandle, uint64_t devino, 121 uint64_t cpuid); 122 123 /* 124 * Time of day services 125 */ 126 127 int64_t hv_tod_get(uint64_t *tod); 128 int64_t hv_tod_set(uint64_t tod); 129 130 /* 131 * Console services 132 */ 133 134 int64_t hv_cons_getchar(int64_t *ch); 135 int64_t hv_cons_putchar(int64_t ch); 136 int64_t hv_api_putchar(int64_t ch); 137 138 #define CONS_BREAK -1 139 #define CONS_HUP -2 140 141 /* 142 * Domain state services 143 */ 144 145 int64_t hv_soft_state_set(uint64_t software_state, 146 paddr_t software_description_ptr); 147 148 #define SIS_NORMAL 0x1 149 #define SIS_TRANSITION 0x2 150 151 /* 152 * PCI I/O services 153 */ 154 155 int64_t hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid, 156 uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p, 157 uint64_t *nttes_mapped); 158 int64_t hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid, 159 uint64_t nttes, uint64_t *nttes_demapped); 160 int64_t hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid, 161 uint64_t *io_attributes, paddr_t *r_addr); 162 int64_t hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr, 163 uint64_t io_attributes, uint64_t *io_addr); 164 165 int64_t hv_pci_config_get(uint64_t devhandle, uint64_t pci_device, 166 uint64_t pci_config_offset, uint64_t size, 167 uint64_t *error_flag, uint64_t *data); 168 int64_t hv_pci_config_put(uint64_t devhandle, uint64_t pci_device, 169 uint64_t pci_config_offset, uint64_t size, uint64_t data, 170 uint64_t *error_flag); 171 172 #define PCI_MAP_ATTR_READ 0x01 /* From memory */ 173 #define PCI_MAP_ATTR_WRITE 0x02 /* To memory */ 174 175 /* 176 * PCI MSI services 177 */ 178 179 int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid, 180 uint64_t r_addr, uint64_t nentries); 181 int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid, 182 uint64_t *r_addr, uint64_t *nentries); 183 184 int64_t hv_pci_msiq_getvalid(uint64_t devhandle, uint64_t msiqid, 185 uint64_t *msiqvalid); 186 int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid, 187 uint64_t msiqvalid); 188 189 #define PCI_MSIQ_INVALID 0 190 #define PCI_MSIQ_VALID 1 191 192 int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid, 193 uint64_t *msiqstate); 194 int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid, 195 uint64_t msiqstate); 196 197 #define PCI_MSIQSTATE_IDLE 0 198 #define PCI_MSIQSTATE_ERROR 1 199 200 int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid, 201 uint64_t *msiqhead); 202 int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid, 203 uint64_t msiqhead); 204 int64_t hv_pci_msiq_gettail(uint64_t devhandle, uint64_t msiqid, 205 uint64_t *msiqtail); 206 207 int64_t hv_pci_msi_getvalid(uint64_t devhandle, uint64_t msinum, 208 uint64_t *msivalidstate); 209 int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum, 210 uint64_t msivalidstate); 211 212 #define PCI_MSI_INVALID 0 213 #define PCI_MSI_VALID 1 214 215 int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum, 216 uint64_t *msiqid); 217 int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum, 218 uint64_t msitype, uint64_t msiqid); 219 220 int64_t hv_pci_msi_getstate(uint64_t devhandle, uint64_t msinum, 221 uint64_t *msistate); 222 int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum, 223 uint64_t msistate); 224 225 #define PCI_MSISTATE_IDLE 0 226 #define PCI_MSISTATE_DELIVERED 1 227 228 int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg, 229 uint64_t *msiqid); 230 int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg, 231 uint64_t msiqid); 232 233 int64_t hv_pci_msg_getvalid(uint64_t devhandle, uint64_t msg, 234 uint64_t *msgvalidstate); 235 int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg, 236 uint64_t msgvalidstate); 237 238 #define PCIE_MSG_INVALID 0 239 #define PCIE_MSG_VALID 1 240 241 #define PCIE_PME_MSG 0x18 242 #define PCIE_PME_ACK_MSG 0x1b 243 #define PCIE_CORR_MSG 0x30 244 #define PCIE_NONFATAL_MSG 0x31 245 #define PCIE_FATAL_MSG 0x32 246 247 /* 248 * Logical Domain Channel services 249 */ 250 251 int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr, 252 uint64_t nentries); 253 int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, 254 uint64_t *nentries); 255 int64_t hv_ldc_tx_get_state(uint64_t ldc_id, uint64_t *head_offset, 256 uint64_t *tail_offset, uint64_t *channel_state); 257 int64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset); 258 int64_t hv_ldc_rx_qconf(uint64_t ldc_id, paddr_t base_raddr, 259 uint64_t nentries); 260 int64_t hv_ldc_rx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, 261 uint64_t *nentries); 262 int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset, 263 uint64_t *tail_offset, uint64_t *channel_state); 264 int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset); 265 266 #define LDC_CHANNEL_DOWN 0 267 #define LDC_CHANNEL_UP 1 268 #define LDC_CHANNEL_RESET 2 269 270 int64_t hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr, 271 uint64_t nentries); 272 int64_t hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr, 273 uint64_t *nentries); 274 int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie, 275 paddr_t raddr, psize_t length, psize_t *ret_length); 276 277 #define LDC_COPY_IN 0 278 #define LDC_COPY_OUT 1 279 280 int64_t hv_ldc_mapin(uint64_t ldc_id, uint64_t cookie, paddr_t *raddr, 281 uint64_t *perms); 282 int64_t hv_ldc_unmap(paddr_t raddr, uint64_t *perms); 283 284 /* 285 * Cryptographic services 286 */ 287 288 int64_t hv_rng_get_diag_control(void); 289 int64_t hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta); 290 int64_t hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout, 291 uint64_t *delta); 292 293 #define RNG_STATE_UNCONFIGURED 0 294 #define RNG_STATE_CONFIGURED 1 295 #define RNG_STATE_HEALTHCHECK 2 296 #define RNG_STATE_ERROR 3 297 298 int64_t hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta); 299 int64_t hv_rng_data_read(paddr_t raddr, uint64_t *delta); 300 301 /* 302 * Error codes 303 */ 304 305 #define H_EOK 0 306 #define H_ENOCPU 1 307 #define H_ENORADDR 2 308 #define H_ENOINTR 3 309 #define H_EBADPGSZ 4 310 #define H_EBADTSB 5 311 #define H_EINVAL 6 312 #define H_EBADTRAP 7 313 #define H_EBADALIGN 8 314 #define H_EWOULDBLOCK 9 315 #define H_ENOACCESS 10 316 #define H_EIO 11 317 #define H_ECPUERROR 12 318 #define H_ENOTSUPPORTED 13 319 #define H_ENOMAP 14 320 #define H_ETOOMANY 15 321 #define H_ECHANNEL 16 322
Indexes created Thu Oct 02 14:10:14 GMT 2025