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hypervisor.h revision 1.3 
      1 /*	$NetBSD: hypervisor.h,v 1.3 2014/06/05 18:36:44 palle Exp $ */
      2 /*	$OpenBSD: hypervisor.h,v 1.14 2011/06/26 17:23:46 kettenis Exp $	*/
      3 
      4 /*
      5  * Copyright (c) 2008 Mark Kettenis
      6  *
      7  * Permission to use, copy, modify, and distribute this software for any
      8  * purpose with or without fee is hereby granted, provided that the above
      9  * copyright notice and this permission notice appear in all copies.
     10  *
     11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18  */
     19 
     20 #ifndef	_HYPERVISOR_H_
     21 #define	_HYPERVISOR_H_
     22 
     23 /*
     24  * UltraSPARC Hypervisor API.
     25  */
     26 
     27 /*
     28  * API versioning
     29  */
     30 
     31 int64_t	hv_api_get_version(uint64_t api_group,
     32 	    uint64_t *major_number, uint64_t *minor_number);
     33 
     34 /*
     35  * Domain services
     36  */
     37 
     38 int64_t hv_mach_desc(paddr_t buffer, psize_t *length);
     39 
     40 /*
     41  * CPU services
     42  */
     43 
     44 void	hv_cpu_yield(void);
     45 int64_t	hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries);
     46 
     47 #define CPU_MONDO_QUEUE		0x3c
     48 #define DEVICE_MONDO_QUEUE	0x3d
     49 
     50 int64_t	hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data);
     51 int64_t	hv_cpu_myid(uint64_t *cpuid);
     52 
     53 /*
     54  * MMU services
     55  */
     56 
     57 int64_t	hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags);
     58 int64_t	hv_mmu_demap_ctx(uint64_t context, uint64_t flags);
     59 int64_t	hv_mmu_demap_all(uint64_t flags);
     60 int64_t	hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags);
     61 int64_t	hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags);
     62 int64_t	hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte,
     63 	    uint64_t flags);
     64 int64_t	hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags);
     65 
     66 #define MAP_DTLB	0x1
     67 #define MAP_ITLB	0x2
     68 
     69 struct tsb_desc {
     70 	uint16_t	td_idxpgsz;
     71 	uint16_t	td_assoc;
     72 	uint32_t	td_size;
     73 	uint32_t	td_ctxidx;
     74 	uint32_t	td_pgsz;
     75 	paddr_t		td_pa;
     76 	uint64_t	td_reserved;
     77 };
     78 
     79 int64_t	hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr);
     80 int64_t	hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr);
     81 
     82 /*
     83  * Cache and memory services
     84  */
     85 
     86 int64_t	hv_mem_scrub(paddr_t raddr, psize_t length);
     87 int64_t	hv_mem_sync(paddr_t raddr, psize_t length);
     88 
     89 /*
     90  * Device interrupt services
     91  */
     92 
     93 int64_t	hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino,
     94 	    uint64_t *sysino);
     95 int64_t	hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled);
     96 int64_t	hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled);
     97 int64_t	hv_intr_getstate(uint64_t sysino, uint64_t *intr_state);
     98 int64_t	hv_intr_setstate(uint64_t sysino, uint64_t intr_state);
     99 int64_t	hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid);
    100 int64_t	hv_intr_settarget(uint64_t sysino, uint64_t cpuid);
    101 
    102 #define INTR_DISABLED	0
    103 #define INTR_ENABLED	1
    104 
    105 #define INTR_IDLE	0
    106 #define INTR_RECEIVED	1
    107 #define INTR_DELIVERED	2
    108 
    109 int64_t	hv_vintr_getcookie(uint64_t devhandle, uint64_t devino,
    110 	    uint64_t *cookie_value);
    111 int64_t	hv_vintr_setcookie(uint64_t devhandle, uint64_t devino,
    112 	    uint64_t cookie_value);
    113 int64_t	hv_vintr_getenabled(uint64_t devhandle, uint64_t devino,
    114 	    uint64_t *intr_enabled);
    115 int64_t	hv_vintr_setenabled(uint64_t devhandle, uint64_t devino,
    116 	    uint64_t intr_enabled);
    117 int64_t	hv_vintr_getstate(uint64_t devhandle, uint64_t devino,
    118 	    uint64_t *intr_state);
    119 int64_t	hv_vintr_setstate(uint64_t devhandle, uint64_t devino,
    120 	    uint64_t intr_state);
    121 int64_t	hv_vintr_gettarget(uint64_t devhandle, uint64_t devino,
    122 	    uint64_t *cpuid);
    123 int64_t	hv_vintr_settarget(uint64_t devhandle, uint64_t devino,
    124 	    uint64_t cpuid);
    125 
    126 /*
    127  * Time of day services
    128  */
    129 
    130 int64_t	hv_tod_get(uint64_t *tod);
    131 int64_t	hv_tod_set(uint64_t tod);
    132 
    133 /*
    134  * Console services
    135  */
    136 
    137 int64_t	hv_cons_getchar(int64_t *ch);
    138 int64_t	hv_cons_putchar(int64_t ch);
    139 int64_t	hv_api_putchar(int64_t ch);
    140 
    141 #define CONS_BREAK	-1
    142 #define CONS_HUP	-2
    143 
    144 /*
    145  * Domain state services
    146  */
    147 
    148 int64_t	hv_soft_state_set(uint64_t software_state,
    149 	    paddr_t software_description_ptr);
    150 
    151 #define SIS_NORMAL	0x1
    152 #define SIS_TRANSITION	0x2
    153 
    154 /*
    155  * PCI I/O services
    156  */
    157 
    158 int64_t	hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid,
    159 	    uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p,
    160 	    uint64_t *nttes_mapped);
    161 int64_t	hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid,
    162 	    uint64_t nttes, uint64_t *nttes_demapped);
    163 int64_t	hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid,
    164 	    uint64_t *io_attributes, paddr_t *r_addr);
    165 int64_t	hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr,
    166 	    uint64_t io_attributes, uint64_t *io_addr);
    167 
    168 int64_t	hv_pci_config_get(uint64_t devhandle, uint64_t pci_device,
    169             uint64_t pci_config_offset, uint64_t size,
    170 	    uint64_t *error_flag, uint64_t *data);
    171 int64_t	hv_pci_config_put(uint64_t devhandle, uint64_t pci_device,
    172             uint64_t pci_config_offset, uint64_t size, uint64_t data,
    173 	    uint64_t *error_flag);
    174 
    175 #define PCI_MAP_ATTR_READ  0x01		/* From memory */
    176 #define PCI_MAP_ATTR_WRITE 0x02		/* To memory */
    177 
    178 /*
    179  * PCI MSI services
    180  */
    181 
    182 int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid,
    183 	    uint64_t r_addr, uint64_t nentries);
    184 int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid,
    185 	    uint64_t *r_addr, uint64_t *nentries);
    186 
    187 int64_t hv_pci_msiq_getvalid(uint64_t devhandle, uint64_t msiqid,
    188 	    uint64_t *msiqvalid);
    189 int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid,
    190 	    uint64_t msiqvalid);
    191 
    192 #define PCI_MSIQ_INVALID	0
    193 #define PCI_MSIQ_VALID		1
    194 
    195 int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid,
    196 	    uint64_t *msiqstate);
    197 int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid,
    198 	    uint64_t msiqstate);
    199 
    200 #define PCI_MSIQSTATE_IDLE	0
    201 #define PCI_MSIQSTATE_ERROR	1
    202 
    203 int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid,
    204 	    uint64_t *msiqhead);
    205 int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid,
    206 	    uint64_t msiqhead);
    207 int64_t hv_pci_msiq_gettail(uint64_t devhandle, uint64_t msiqid,
    208 	    uint64_t *msiqtail);
    209 
    210 int64_t hv_pci_msi_getvalid(uint64_t devhandle, uint64_t msinum,
    211 	    uint64_t *msivalidstate);
    212 int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum,
    213 	    uint64_t msivalidstate);
    214 
    215 #define PCI_MSI_INVALID		0
    216 #define PCI_MSI_VALID		1
    217 
    218 int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum,
    219 	    uint64_t *msiqid);
    220 int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum,
    221 	    uint64_t msitype, uint64_t msiqid);
    222 
    223 int64_t hv_pci_msi_getstate(uint64_t devhandle, uint64_t msinum,
    224 	    uint64_t *msistate);
    225 int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum,
    226 	    uint64_t msistate);
    227 
    228 #define PCI_MSISTATE_IDLE	0
    229 #define PCI_MSISTATE_DELIVERED	1
    230 
    231 int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg,
    232 	    uint64_t *msiqid);
    233 int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg,
    234 	    uint64_t msiqid);
    235 
    236 int64_t hv_pci_msg_getvalid(uint64_t devhandle, uint64_t msg,
    237 	    uint64_t *msgvalidstate);
    238 int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg,
    239 	    uint64_t msgvalidstate);
    240 
    241 #define PCIE_MSG_INVALID	0
    242 #define PCIE_MSG_VALID		1
    243 
    244 #define PCIE_PME_MSG		0x18
    245 #define PCIE_PME_ACK_MSG	0x1b
    246 #define PCIE_CORR_MSG		0x30
    247 #define PCIE_NONFATAL_MSG	0x31
    248 #define PCIE_FATAL_MSG		0x32
    249 
    250 /*
    251  * Logical Domain Channel services
    252  */
    253 
    254 int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr,
    255 	    uint64_t nentries);
    256 int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr,
    257 	    uint64_t *nentries);
    258 int64_t hv_ldc_tx_get_state(uint64_t ldc_id, uint64_t *head_offset,
    259 	    uint64_t *tail_offset, uint64_t *channel_state);
    260 int64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
    261 int64_t hv_ldc_rx_qconf(uint64_t ldc_id, paddr_t base_raddr,
    262 	    uint64_t nentries);
    263 int64_t hv_ldc_rx_qinfo(uint64_t ldc_id, paddr_t *base_raddr,
    264 	    uint64_t *nentries);
    265 int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset,
    266 	    uint64_t *tail_offset, uint64_t *channel_state);
    267 int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
    268 
    269 #define LDC_CHANNEL_DOWN	0
    270 #define LDC_CHANNEL_UP		1
    271 #define LDC_CHANNEL_RESET	2
    272 
    273 int64_t	hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr,
    274 	    uint64_t nentries);
    275 int64_t	hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr,
    276 	    uint64_t *nentries);
    277 int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie,
    278 	    paddr_t raddr, psize_t length, psize_t *ret_length);
    279 
    280 #define LDC_COPY_IN		0
    281 #define LDC_COPY_OUT		1
    282 
    283 int64_t hv_ldc_mapin(uint64_t ldc_id, uint64_t cookie, paddr_t *raddr,
    284 	    uint64_t *perms);
    285 int64_t hv_ldc_unmap(paddr_t raddr, uint64_t *perms);
    286 
    287 /*
    288  * Cryptographic services
    289  */
    290 
    291 int64_t	hv_rng_get_diag_control(void);
    292 int64_t	hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta);
    293 int64_t	hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout,
    294 	uint64_t *delta);
    295 
    296 #define RNG_STATE_UNCONFIGURED	0
    297 #define RNG_STATE_CONFIGURED	1
    298 #define RNG_STATE_HEALTHCHECK	2
    299 #define RNG_STATE_ERROR		3
    300 
    301 int64_t	hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta);
    302 int64_t	hv_rng_data_read(paddr_t raddr, uint64_t *delta);
    303 
    304 /*
    305  * Error codes
    306  */
    307 
    308 #define H_EOK		0
    309 #define H_ENOCPU	1
    310 #define H_ENORADDR	2
    311 #define H_ENOINTR	3
    312 #define H_EBADPGSZ	4
    313 #define H_EBADTSB	5
    314 #define H_EINVAL	6
    315 #define H_EBADTRAP	7
    316 #define H_EBADALIGN	8
    317 #define H_EWOULDBLOCK	9
    318 #define H_ENOACCESS	10
    319 #define H_EIO		11
    320 #define H_ECPUERROR	12
    321 #define H_ENOTSUPPORTED	13
    322 #define H_ENOMAP	14
    323 #define H_ETOOMANY	15
    324 #define H_ECHANNEL	16
    325 
    326 #endif	/* _HYPERVISOR_H_ */
    327