hypervisor.h revision 1.8
1 /* $NetBSD: hypervisor.h,v 1.8 2021/07/03 19:18:55 palle Exp $ */ 2 /* $OpenBSD: hypervisor.h,v 1.14 2011/06/26 17:23:46 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2008 Mark Kettenis 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HYPERVISOR_H_ 21 #define _HYPERVISOR_H_ 22 23 /* 24 * UltraSPARC Hypervisor API. 25 */ 26 27 /* 28 * FAST_TRAP function numbers 29 */ 30 31 #define FT_MMU_MAP_PERM_ADDR 0x25 32 33 /* 34 * API versioning 35 */ 36 37 #ifndef _LOCORE 38 int64_t hv_api_get_version(uint64_t api_group, 39 uint64_t *major_number, 40 uint64_t *minor_number); 41 int64_t hv_api_set_version(uint64_t api_group, 42 uint64_t major_number, 43 uint64_t req_minor_number, 44 uint64_t* actual_minor_number); 45 #define HV_API_GROUP_INTERRUPT 0x002 46 #endif 47 /* 48 * Domain services 49 */ 50 51 #ifndef _LOCORE 52 int64_t hv_mach_desc(paddr_t buffer, psize_t *length); 53 #endif 54 55 /* 56 * CPU services 57 */ 58 59 #ifndef _LOCORE 60 void hv_cpu_yield(void); 61 int64_t hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries); 62 #endif 63 64 #define CPU_MONDO_QUEUE 0x3c 65 #define DEVICE_MONDO_QUEUE 0x3d 66 67 #ifndef _LOCORE 68 int64_t hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data); 69 int64_t hv_cpu_myid(uint64_t *cpuid); 70 #endif 71 72 /* 73 * MMU services 74 */ 75 76 #ifndef _LOCORE 77 int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags); 78 int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags); 79 int64_t hv_mmu_demap_all(uint64_t flags); 80 int64_t hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags); 81 int64_t hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags); 82 int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte, 83 uint64_t flags); 84 int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags); 85 #endif 86 87 #define MAP_DTLB 0x1 88 #define MAP_ITLB 0x2 89 90 #ifndef _LOCORE 91 struct tsb_desc { 92 uint16_t td_idxpgsz; 93 uint16_t td_assoc; 94 uint32_t td_size; 95 uint32_t td_ctxidx; 96 uint32_t td_pgsz; 97 paddr_t td_pa; 98 uint64_t td_reserved; 99 }; 100 101 struct mmufsa { 102 uint64_t ift; /* instruction fault type */ 103 uint64_t ifa; /* instruction fault address */ 104 uint64_t ifc; /* instruction fault context */ 105 uint64_t reserved1[5]; /* reserved */ 106 uint64_t dft; /* data fault type */ 107 uint64_t dfa; /* data fault address */ 108 uint64_t dfc; /* data fault context */ 109 uint64_t reserved2[5]; /* reserved */ 110 }; 111 112 int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr); 113 int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr); 114 #endif 115 116 /* 117 * Cache and memory services 118 */ 119 120 #ifndef _LOCORE 121 int64_t hv_mem_scrub(paddr_t raddr, psize_t length); 122 int64_t hv_mem_sync(paddr_t raddr, psize_t length); 123 #endif 124 125 /* 126 * Device interrupt services 127 */ 128 129 #ifndef _LOCORE 130 int64_t hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino, 131 uint64_t *sysino); 132 int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled); 133 int64_t hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled); 134 int64_t hv_intr_getstate(uint64_t sysino, uint64_t *intr_state); 135 int64_t hv_intr_setstate(uint64_t sysino, uint64_t intr_state); 136 int64_t hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid); 137 int64_t hv_intr_settarget(uint64_t sysino, uint64_t cpuid); 138 #endif 139 140 #define INTR_DISABLED 0 141 #define INTR_ENABLED 1 142 143 #define INTR_IDLE 0 144 #define INTR_RECEIVED 1 145 #define INTR_DELIVERED 2 146 147 #ifndef _LOCORE 148 int64_t hv_vintr_getcookie(uint64_t devhandle, uint64_t devino, 149 uint64_t *cookie_value); 150 int64_t hv_vintr_setcookie(uint64_t devhandle, uint64_t devino, 151 uint64_t cookie_value); 152 int64_t hv_vintr_getenabled(uint64_t devhandle, uint64_t devino, 153 uint64_t *intr_enabled); 154 int64_t hv_vintr_setenabled(uint64_t devhandle, uint64_t devino, 155 uint64_t intr_enabled); 156 int64_t hv_vintr_getstate(uint64_t devhandle, uint64_t devino, 157 uint64_t *intr_state); 158 int64_t hv_vintr_setstate(uint64_t devhandle, uint64_t devino, 159 uint64_t intr_state); 160 int64_t hv_vintr_gettarget(uint64_t devhandle, uint64_t devino, 161 uint64_t *cpuid); 162 int64_t hv_vintr_settarget(uint64_t devhandle, uint64_t devino, 163 uint64_t cpuid); 164 #endif 165 166 /* 167 * Time of day services 168 */ 169 170 #ifndef _LOCORE 171 int64_t hv_tod_get(uint64_t *tod); 172 int64_t hv_tod_set(uint64_t tod); 173 #endif 174 175 /* 176 * Console services 177 */ 178 179 #ifndef _LOCORE 180 int64_t hv_cons_getchar(int64_t *ch); 181 int64_t hv_cons_putchar(int64_t ch); 182 int64_t hv_api_putchar(int64_t ch); 183 #endif 184 185 #define CONS_BREAK -1 186 #define CONS_HUP -2 187 188 /* 189 * Domain state services 190 */ 191 192 #ifndef _LOCORE 193 int64_t hv_soft_state_set(uint64_t software_state, 194 paddr_t software_description_ptr); 195 #endif 196 197 #define SIS_NORMAL 0x1 198 #define SIS_TRANSITION 0x2 199 200 /* 201 * PCI I/O services 202 */ 203 204 #ifndef _LOCORE 205 int64_t hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid, 206 uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p, 207 uint64_t *nttes_mapped); 208 int64_t hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid, 209 uint64_t nttes, uint64_t *nttes_demapped); 210 int64_t hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid, 211 uint64_t *io_attributes, paddr_t *r_addr); 212 int64_t hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr, 213 uint64_t io_attributes, uint64_t *io_addr); 214 215 int64_t hv_pci_config_get(uint64_t devhandle, uint64_t pci_device, 216 uint64_t pci_config_offset, uint64_t size, 217 uint64_t *error_flag, uint64_t *data); 218 int64_t hv_pci_config_put(uint64_t devhandle, uint64_t pci_device, 219 uint64_t pci_config_offset, uint64_t size, uint64_t data, 220 uint64_t *error_flag); 221 #endif 222 223 #define PCI_MAP_ATTR_READ 0x01 /* From memory */ 224 #define PCI_MAP_ATTR_WRITE 0x02 /* To memory */ 225 226 /* 227 * PCI MSI services 228 */ 229 230 #ifndef _LOCORE 231 int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid, 232 uint64_t r_addr, uint64_t nentries); 233 int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid, 234 uint64_t *r_addr, uint64_t *nentries); 235 236 int64_t hv_pci_msiq_getvalid(uint64_t devhandle, uint64_t msiqid, 237 uint64_t *msiqvalid); 238 int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid, 239 uint64_t msiqvalid); 240 #endif 241 242 #define PCI_MSIQ_INVALID 0 243 #define PCI_MSIQ_VALID 1 244 245 #ifndef _LOCORE 246 int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid, 247 uint64_t *msiqstate); 248 int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid, 249 uint64_t msiqstate); 250 #endif 251 252 #define PCI_MSIQSTATE_IDLE 0 253 #define PCI_MSIQSTATE_ERROR 1 254 255 #ifndef _LOCORE 256 int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid, 257 uint64_t *msiqhead); 258 int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid, 259 uint64_t msiqhead); 260 int64_t hv_pci_msiq_gettail(uint64_t devhandle, uint64_t msiqid, 261 uint64_t *msiqtail); 262 263 int64_t hv_pci_msi_getvalid(uint64_t devhandle, uint64_t msinum, 264 uint64_t *msivalidstate); 265 int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum, 266 uint64_t msivalidstate); 267 #endif 268 269 #define PCI_MSI_INVALID 0 270 #define PCI_MSI_VALID 1 271 272 #ifndef _LOCORE 273 int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum, 274 uint64_t *msiqid); 275 int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum, 276 uint64_t msitype, uint64_t msiqid); 277 278 int64_t hv_pci_msi_getstate(uint64_t devhandle, uint64_t msinum, 279 uint64_t *msistate); 280 int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum, 281 uint64_t msistate); 282 #endif 283 284 #define PCI_MSISTATE_IDLE 0 285 #define PCI_MSISTATE_DELIVERED 1 286 287 #ifndef _LOCORE 288 int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg, 289 uint64_t *msiqid); 290 int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg, 291 uint64_t msiqid); 292 293 int64_t hv_pci_msg_getvalid(uint64_t devhandle, uint64_t msg, 294 uint64_t *msgvalidstate); 295 int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg, 296 uint64_t msgvalidstate); 297 #endif 298 299 #define PCIE_MSG_INVALID 0 300 #define PCIE_MSG_VALID 1 301 302 #define PCIE_PME_MSG 0x18 303 #define PCIE_PME_ACK_MSG 0x1b 304 #define PCIE_CORR_MSG 0x30 305 #define PCIE_NONFATAL_MSG 0x31 306 #define PCIE_FATAL_MSG 0x32 307 308 /* 309 * Logical Domain Channel services 310 */ 311 312 #ifndef _LOCORE 313 int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr, 314 uint64_t nentries); 315 int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, 316 uint64_t *nentries); 317 int64_t hv_ldc_tx_get_state(uint64_t ldc_id, uint64_t *head_offset, 318 uint64_t *tail_offset, uint64_t *channel_state); 319 int64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset); 320 int64_t hv_ldc_rx_qconf(uint64_t ldc_id, paddr_t base_raddr, 321 uint64_t nentries); 322 int64_t hv_ldc_rx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, 323 uint64_t *nentries); 324 int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset, 325 uint64_t *tail_offset, uint64_t *channel_state); 326 int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset); 327 #endif 328 329 #define LDC_CHANNEL_DOWN 0 330 #define LDC_CHANNEL_UP 1 331 #define LDC_CHANNEL_RESET 2 332 333 #ifndef _LOCORE 334 int64_t hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr, 335 uint64_t nentries); 336 int64_t hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr, 337 uint64_t *nentries); 338 int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie, 339 paddr_t raddr, psize_t length, psize_t *ret_length); 340 #endif 341 342 #define LDC_COPY_IN 0 343 #define LDC_COPY_OUT 1 344 345 #ifndef _LOCORE 346 int64_t hv_ldc_mapin(uint64_t ldc_id, uint64_t cookie, paddr_t *raddr, 347 uint64_t *perms); 348 int64_t hv_ldc_unmap(paddr_t raddr, uint64_t *perms); 349 #endif 350 351 /* 352 * Cryptographic services 353 */ 354 355 #ifndef _LOCORE 356 int64_t hv_rng_get_diag_control(void); 357 int64_t hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta); 358 int64_t hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout, 359 uint64_t *delta); 360 #endif 361 362 #define RNG_STATE_UNCONFIGURED 0 363 #define RNG_STATE_CONFIGURED 1 364 #define RNG_STATE_HEALTHCHECK 2 365 #define RNG_STATE_ERROR 3 366 367 #ifndef _LOCORE 368 int64_t hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta); 369 int64_t hv_rng_data_read(paddr_t raddr, uint64_t *delta); 370 #endif 371 372 /* 373 * Error codes 374 */ 375 376 #define H_EOK 0 377 #define H_ENOCPU 1 378 #define H_ENORADDR 2 379 #define H_ENOINTR 3 380 #define H_EBADPGSZ 4 381 #define H_EBADTSB 5 382 #define H_EINVAL 6 383 #define H_EBADTRAP 7 384 #define H_EBADALIGN 8 385 #define H_EWOULDBLOCK 9 386 #define H_ENOACCESS 10 387 #define H_EIO 11 388 #define H_ECPUERROR 12 389 #define H_ENOTSUPPORTED 13 390 #define H_ENOMAP 14 391 #define H_ETOOMANY 15 392 #define H_ECHANNEL 16 393 394 #ifndef _LOCORE 395 extern uint64_t sun4v_group_interrupt_major; 396 extern uint64_t sun4v_group_sdio_major; 397 398 int64_t sun4v_intr_devino_to_sysino(uint64_t, uint64_t, uint64_t *); 399 int64_t sun4v_intr_setcookie(uint64_t, uint64_t, uint64_t); 400 int64_t sun4v_intr_setenabled(uint64_t, uint64_t, uint64_t); 401 int64_t sun4v_intr_setstate(uint64_t, uint64_t, uint64_t); 402 int64_t sun4v_intr_settarget(uint64_t, uint64_t, uint64_t); 403 #endif 404 405 #endif /* _HYPERVISOR_H_ */ 406
Indexes created Thu Oct 02 14:10:14 GMT 2025