intr.h revision 1.31 1 1.31 matt /* $NetBSD: intr.h,v 1.31 2012/07/27 05:36:12 matt Exp $ */
2 1.1 mrg
3 1.1 mrg /*-
4 1.1 mrg * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * This code is derived from software contributed to The NetBSD Foundation
8 1.1 mrg * by Paul Kranenburg.
9 1.1 mrg *
10 1.1 mrg * Redistribution and use in source and binary forms, with or without
11 1.1 mrg * modification, are permitted provided that the following conditions
12 1.1 mrg * are met:
13 1.1 mrg * 1. Redistributions of source code must retain the above copyright
14 1.1 mrg * notice, this list of conditions and the following disclaimer.
15 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 mrg * notice, this list of conditions and the following disclaimer in the
17 1.1 mrg * documentation and/or other materials provided with the distribution.
18 1.1 mrg *
19 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 mrg * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 mrg * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 mrg * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 mrg * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 mrg * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 mrg * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 mrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 mrg * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 mrg * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 mrg * POSSIBILITY OF SUCH DAMAGE.
30 1.1 mrg */
31 1.1 mrg
32 1.10 chs #ifndef _SPARC64_INTR_H_
33 1.10 chs #define _SPARC64_INTR_H_
34 1.10 chs
35 1.30 mrg #ifdef _KERNEL
36 1.30 mrg
37 1.24 nakayama #if defined(_KERNEL_OPT)
38 1.24 nakayama #include "opt_multiprocessor.h"
39 1.24 nakayama #endif
40 1.24 nakayama
41 1.22 nakayama #ifndef _LOCORE
42 1.10 chs #include <machine/cpuset.h>
43 1.22 nakayama #endif
44 1.24 nakayama #include <machine/psl.h>
45 1.10 chs
46 1.1 mrg /* XXX - arbitrary numbers; no interpretation is defined yet */
47 1.6 eeh #define IPL_NONE 0 /* nothing */
48 1.6 eeh #define IPL_SOFTCLOCK 1 /* timeouts */
49 1.19 ad #define IPL_SOFTBIO 1 /* block I/O */
50 1.6 eeh #define IPL_SOFTNET 1 /* protocol stack */
51 1.6 eeh #define IPL_SOFTSERIAL 4 /* serial */
52 1.13 yamt #define IPL_VM PIL_VM /* memory allocation */
53 1.6 eeh #define IPL_SCHED PIL_SCHED /* scheduler */
54 1.6 eeh #define IPL_HIGH PIL_HIGH /* everything */
55 1.10 chs #define IPL_HALT 5 /* cpu stop-self */
56 1.10 chs #define IPL_PAUSE 13 /* pause cpu */
57 1.16 jnemeth #define IPL_FDSOFT PIL_FDSOFT /* floppy */
58 1.10 chs
59 1.31 matt /*
60 1.31 matt * IPL_SAFEPRI is a safe priority for sleep to set for a spin-wait
61 1.31 matt * during autoconfiguration or after a panic.
62 1.31 matt */
63 1.31 matt #define IPL_SAFEPRI IPL_NONE
64 1.31 matt
65 1.22 nakayama #ifndef _LOCORE
66 1.22 nakayama void fpusave_lwp(struct lwp *, bool);
67 1.22 nakayama #endif /* _LOCORE */
68 1.15 martin
69 1.10 chs #if defined(MULTIPROCESSOR)
70 1.22 nakayama #ifndef _LOCORE
71 1.11 petrov void sparc64_ipi_init (void);
72 1.29 martin void sparc64_ipi_halt_thiscpu (void *, void *);
73 1.27 mrg void sparc64_ipi_pause_thiscpu (void *);
74 1.21 martin void sparc64_do_pause(void);
75 1.29 martin void sparc64_ipi_drop_fpstate (void *, void *);
76 1.29 martin void sparc64_ipi_save_fpstate (void *, void *);
77 1.29 martin void sparc64_ipi_nop (void *, void *);
78 1.29 martin void sparc64_ipi_ccall(void *, void *);
79 1.14 mrg void mp_halt_cpus (void);
80 1.14 mrg void mp_pause_cpus (void);
81 1.14 mrg void mp_resume_cpus (void);
82 1.20 martin int mp_cpu_is_paused (sparc64_cpuset_t);
83 1.21 martin void mp_resume_cpu(int);
84 1.22 nakayama #endif /* _LOCORE */
85 1.28 mrg #endif
86 1.22 nakayama
87 1.30 mrg #endif /* _KERNEL */
88 1.30 mrg
89 1.22 nakayama #define IPI_EVCNT_TLB_PTE 0
90 1.26 nakayama #define IPI_EVCNT_FPU_SYNCH 1
91 1.26 nakayama #define IPI_EVCNT_FPU_FLUSH 2
92 1.26 nakayama #define IPI_EVCNT_NUM 3
93 1.26 nakayama #define IPI_EVCNT_NAMES { "TLB pte IPI", "FPU synch IPI", "FPU flush IPI" }
94 1.1 mrg
95 1.10 chs #endif /* _SPARC64_INTR_H_ */
96