1 1.31 riastrad /* $NetBSD: pci_machdep.h,v 1.31 2024/06/23 00:53:34 riastradh Exp $ */ 2 1.1 mrg 3 1.1 mrg /* 4 1.1 mrg * Copyright (c) 1999 Matthew R. Green 5 1.1 mrg * All rights reserved. 6 1.1 mrg * 7 1.1 mrg * Redistribution and use in source and binary forms, with or without 8 1.1 mrg * modification, are permitted provided that the following conditions 9 1.1 mrg * are met: 10 1.1 mrg * 1. Redistributions of source code must retain the above copyright 11 1.1 mrg * notice, this list of conditions and the following disclaimer. 12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 mrg * notice, this list of conditions and the following disclaimer in the 14 1.1 mrg * documentation and/or other materials provided with the distribution. 15 1.1 mrg * 16 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 mrg * SUCH DAMAGE. 27 1.1 mrg */ 28 1.1 mrg 29 1.1 mrg #ifndef _MACHINE_PCI_MACHDEP_H_ 30 1.1 mrg #define _MACHINE_PCI_MACHDEP_H_ 31 1.1 mrg 32 1.1 mrg /* 33 1.5 sommerfe * Forward declarations. 34 1.5 sommerfe */ 35 1.5 sommerfe struct pci_attach_args; 36 1.5 sommerfe 37 1.5 sommerfe /* 38 1.1 mrg * define some bits used to glue into the common PCI code. 39 1.1 mrg */ 40 1.1 mrg 41 1.7 eeh /* 42 1.7 eeh * The stuuuuuuupid allegedly MI PCI code expects pcitag_t to be a 43 1.7 eeh * scalar type. But we really need to store both the OFW node and 44 1.7 eeh * the bus/device/function info in it. (We'd like to store more, 45 1.7 eeh * like all the ofw properties, but we don't need to.) Luckily, 46 1.18 cdi * both are 32-bit values, so we can squeeze them into a uint64_t 47 1.7 eeh * with a little help from some macros. 48 1.7 eeh */ 49 1.7 eeh 50 1.7 eeh #define PCITAG_NODE(x) (int)(((x)>>32)&0xffffffff) 51 1.7 eeh #define PCITAG_OFFSET(x) ((x)&0xffffffff) 52 1.10 thorpej #define PCITAG_BUS(t) ((PCITAG_OFFSET(t)>>16)&0xff) 53 1.10 thorpej #define PCITAG_DEV(t) ((PCITAG_OFFSET(t)>>11)&0x1f) 54 1.10 thorpej #define PCITAG_FUN(t) ((PCITAG_OFFSET(t)>>8)&0x7) 55 1.18 cdi #define PCITAG_CREATE(n,b,d,f) (((uint64_t)(n)<<32)|((b)<<16)|((d)<<11)|((f)<<8)) 56 1.9 eeh #define PCITAG_SETNODE(t,n) ((t)&0xffffffff)|(((n)<<32) 57 1.28 msaitoh typedef uint64_t pcitag_t; 58 1.7 eeh 59 1.20 mrg typedef struct sparc_pci_chipset *pci_chipset_tag_t; 60 1.20 mrg typedef u_int pci_intr_handle_t; 61 1.20 mrg 62 1.20 mrg struct sparc_pci_chipset { 63 1.20 mrg void *cookie; /* psycho_pbm/, but sssh! */ 64 1.20 mrg int rootnode; /* PCI controller */ 65 1.20 mrg 66 1.20 mrg /* pci(9) interfaces */ 67 1.20 mrg pcireg_t (*spc_conf_read)(pci_chipset_tag_t, pcitag_t, int); 68 1.20 mrg void (*spc_conf_write)(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 69 1.20 mrg 70 1.25 dyoung int (*spc_intr_map)(const struct pci_attach_args *, pci_intr_handle_t *); 71 1.20 mrg void *(*spc_intr_establish)(pci_chipset_tag_t, pci_intr_handle_t, int, int (*)(void *), void *); 72 1.20 mrg 73 1.20 mrg /* private interfaces */ 74 1.25 dyoung int (*spc_find_ino)(const struct pci_attach_args *, pci_intr_handle_t *); 75 1.20 mrg 76 1.21 nakayama int spc_busmax; 77 1.20 mrg struct spc_busnode { 78 1.20 mrg int node; 79 1.20 mrg int (*valid)(void *); 80 1.20 mrg void *arg; 81 1.20 mrg } (*spc_busnode)[256]; 82 1.20 mrg }; 83 1.20 mrg 84 1.1 mrg 85 1.26 chs void pci_attach_hook(device_t, device_t, 86 1.26 chs struct pcibus_attach_args *); 87 1.3 cgd int pci_bus_maxdevs(pci_chipset_tag_t, int); 88 1.3 cgd pcitag_t pci_make_tag(pci_chipset_tag_t, int, int, int); 89 1.10 thorpej void pci_decompose_tag(pci_chipset_tag_t, pcitag_t, int *, int *, 90 1.10 thorpej int *); 91 1.27 christos const char *pci_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 92 1.27 christos char *, size_t); 93 1.4 cgd const struct evcnt *pci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t); 94 1.25 dyoung int pci_intr_map(const struct pci_attach_args *, 95 1.25 dyoung pci_intr_handle_t *); 96 1.3 cgd void pci_intr_disestablish(pci_chipset_tag_t, void *); 97 1.12 thorpej 98 1.31 riastrad int sparc64_pci_enumerate_bus1(struct pci_softc *, const int *, 99 1.31 riastrad int (*)(void *, const struct pci_attach_args *), void *, 100 1.13 thorpej struct pci_attach_args *); 101 1.31 riastrad #define PCI_MACHDEP_ENUMERATE_BUS1 sparc64_pci_enumerate_bus1 102 1.1 mrg 103 1.20 mrg #define pci_conf_read(pc, tag, reg) \ 104 1.20 mrg ((pc)->spc_conf_read(pc, tag, reg)) 105 1.20 mrg #define pci_conf_write(pc, tag, reg, val) \ 106 1.20 mrg ((pc)->spc_conf_write(pc, tag, reg, val)) 107 1.20 mrg #define pci_intr_establish(pc, handle, level, func, arg) \ 108 1.20 mrg ((pc)->spc_intr_establish(pc, handle, level, func, arg)) 109 1.20 mrg 110 1.22 mrg /* SPARC specific PCI interfaces */ 111 1.22 mrg int sparc_pci_childspace(int); 112 1.22 mrg 113 1.1 mrg #endif /* _MACHINE_PCI_MACHDEP_H_ */ 114
Indexes created Tue Sep 23 14:10:03 GMT 2025