pmap.h revision 1.62 1 1.62 mrg /* $NetBSD: pmap.h,v 1.62 2019/01/10 10:33:49 mrg Exp $ */
2 1.1 eeh
3 1.1 eeh /*-
4 1.1 eeh * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 1.1 eeh * Copyright (C) 1995, 1996 TooLs GmbH.
6 1.1 eeh * All rights reserved.
7 1.1 eeh *
8 1.1 eeh * Redistribution and use in source and binary forms, with or without
9 1.1 eeh * modification, are permitted provided that the following conditions
10 1.1 eeh * are met:
11 1.1 eeh * 1. Redistributions of source code must retain the above copyright
12 1.1 eeh * notice, this list of conditions and the following disclaimer.
13 1.1 eeh * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 eeh * notice, this list of conditions and the following disclaimer in the
15 1.1 eeh * documentation and/or other materials provided with the distribution.
16 1.1 eeh * 3. All advertising materials mentioning features or use of this software
17 1.1 eeh * must display the following acknowledgement:
18 1.1 eeh * This product includes software developed by TooLs GmbH.
19 1.1 eeh * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 1.1 eeh * derived from this software without specific prior written permission.
21 1.1 eeh *
22 1.1 eeh * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 1.1 eeh * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 eeh * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 eeh * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 1.1 eeh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 1.1 eeh * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 1.1 eeh * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 1.1 eeh * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 1.1 eeh * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 1.1 eeh * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 eeh */
33 1.1 eeh
34 1.1 eeh #ifndef _MACHINE_PMAP_H_
35 1.1 eeh #define _MACHINE_PMAP_H_
36 1.1 eeh
37 1.1 eeh #ifndef _LOCORE
38 1.1 eeh #include <machine/pte.h>
39 1.1 eeh #include <sys/queue.h>
40 1.23 chs #include <uvm/uvm_object.h>
41 1.44 pooka #ifdef _KERNEL
42 1.44 pooka #include <machine/cpuset.h>
43 1.59 palle #ifdef SUN4V
44 1.60 nakayama #include <machine/hypervisor.h>
45 1.59 palle #endif
46 1.44 pooka #endif
47 1.1 eeh #endif
48 1.1 eeh
49 1.1 eeh /*
50 1.1 eeh * This scheme uses 2-level page tables.
51 1.1 eeh *
52 1.1 eeh * While we're still in 32-bit mode we do the following:
53 1.1 eeh *
54 1.1 eeh * offset: 13 bits
55 1.1 eeh * 1st level: 1024 64-bit TTEs in an 8K page for 10 bits
56 1.1 eeh * 2nd level: 512 32-bit pointers in the pmap for 9 bits
57 1.1 eeh * -------
58 1.1 eeh * total: 32 bits
59 1.1 eeh *
60 1.4 eeh * In 64-bit mode the Spitfire and Blackbird CPUs support only
61 1.23 chs * 44-bit virtual addresses. All addresses between
62 1.4 eeh * 0x0000 07ff ffff ffff and 0xffff f800 0000 0000 are in the
63 1.4 eeh * "VA hole" and trap, so we don't have to track them. However,
64 1.4 eeh * we do need to keep them in mind during PT walking. If they
65 1.4 eeh * ever change the size of the address "hole" we need to rework
66 1.4 eeh * all the page table handling.
67 1.1 eeh *
68 1.1 eeh * offset: 13 bits
69 1.1 eeh * 1st level: 1024 64-bit TTEs in an 8K page for 10 bits
70 1.1 eeh * 2nd level: 1024 64-bit pointers in an 8K page for 10 bits
71 1.4 eeh * 3rd level: 1024 64-bit pointers in the segmap for 10 bits
72 1.1 eeh * -------
73 1.4 eeh * total: 43 bits
74 1.4 eeh *
75 1.4 eeh * Of course, this means for 32-bit spaces we always have a (practically)
76 1.4 eeh * wasted page for the segmap (only one entry used) and half a page wasted
77 1.4 eeh * for the page directory. We still have need of one extra bit 8^(.
78 1.1 eeh */
79 1.1 eeh
80 1.4 eeh #define HOLESHIFT (43)
81 1.4 eeh
82 1.33 heas #define PTSZ (PAGE_SIZE/8) /* page table entry */
83 1.33 heas #define PDSZ (PTSZ) /* page directory */
84 1.33 heas #define STSZ (PTSZ) /* psegs */
85 1.1 eeh
86 1.1 eeh #define PTSHIFT (13)
87 1.4 eeh #define PDSHIFT (10+PTSHIFT)
88 1.4 eeh #define STSHIFT (10+PDSHIFT)
89 1.1 eeh
90 1.1 eeh #define PTMASK (PTSZ-1)
91 1.4 eeh #define PDMASK (PDSZ-1)
92 1.1 eeh #define STMASK (STSZ-1)
93 1.1 eeh
94 1.1 eeh #ifndef _LOCORE
95 1.1 eeh
96 1.56 martin #ifdef _LP64
97 1.56 martin int sparc64_mmap_range_test(vaddr_t, vaddr_t);
98 1.56 martin #define MD_MMAP_RANGE_TEST(MINVA, MAXVA) sparc64_mmap_range_test(MINVA, MAXVA)
99 1.56 martin #endif
100 1.56 martin
101 1.1 eeh /*
102 1.1 eeh * Support for big page sizes. This maps the page size to the
103 1.1 eeh * page bits.
104 1.1 eeh */
105 1.1 eeh struct page_size_map {
106 1.36 cdi uint64_t mask;
107 1.36 cdi uint64_t code;
108 1.55 mrg #if defined(DEBUG) || 1
109 1.36 cdi uint64_t use;
110 1.1 eeh #endif
111 1.1 eeh };
112 1.1 eeh extern struct page_size_map page_size_map[];
113 1.1 eeh
114 1.1 eeh /*
115 1.1 eeh * Pmap stuff
116 1.1 eeh */
117 1.1 eeh
118 1.4 eeh #define va_to_seg(v) (int)((((paddr_t)(v))>>STSHIFT)&STMASK)
119 1.4 eeh #define va_to_dir(v) (int)((((paddr_t)(v))>>PDSHIFT)&PDMASK)
120 1.4 eeh #define va_to_pte(v) (int)((((paddr_t)(v))>>PTSHIFT)&PTMASK)
121 1.1 eeh
122 1.52 mrg #ifdef MULTIPROCESSOR
123 1.52 mrg #define PMAP_LIST_MAXNUMCPU CPUSET_MAXNUMCPU
124 1.52 mrg #else
125 1.52 mrg #define PMAP_LIST_MAXNUMCPU 1
126 1.52 mrg #endif
127 1.52 mrg
128 1.1 eeh struct pmap {
129 1.23 chs struct uvm_object pm_obj;
130 1.54 rmind kmutex_t pm_obj_lock;
131 1.23 chs #define pm_lock pm_obj.vmobjlock
132 1.23 chs #define pm_refs pm_obj.uo_refs
133 1.52 mrg LIST_ENTRY(pmap) pm_list[PMAP_LIST_MAXNUMCPU]; /* per cpu ctx used list */
134 1.25 martin
135 1.25 martin struct pmap_statistics pm_stats;
136 1.25 martin
137 1.39 martin /*
138 1.39 martin * We record the context used on any cpu here. If the context
139 1.39 martin * is actually present in the TLB, it will be the plain context
140 1.39 martin * number. If the context is allocated, but has been flushed
141 1.39 martin * from the tlb, the number will be negative.
142 1.39 martin * If this pmap has no context allocated on that cpu, the entry
143 1.39 martin * will be 0.
144 1.39 martin */
145 1.52 mrg int pm_ctx[PMAP_LIST_MAXNUMCPU]; /* Current context per cpu */
146 1.23 chs
147 1.23 chs /*
148 1.23 chs * This contains 64-bit pointers to pages that contain
149 1.4 eeh * 1024 64-bit pointers to page tables. All addresses
150 1.23 chs * are physical.
151 1.4 eeh *
152 1.4 eeh * !!! Only touch this through pseg_get() and pseg_set() !!!
153 1.4 eeh */
154 1.3 eeh paddr_t pm_physaddr; /* physical address of pm_segs */
155 1.12 eeh int64_t *pm_segs;
156 1.1 eeh };
157 1.1 eeh
158 1.1 eeh /*
159 1.1 eeh * This comes from the PROM and is used to map prom entries.
160 1.1 eeh */
161 1.1 eeh struct prom_map {
162 1.36 cdi uint64_t vstart;
163 1.36 cdi uint64_t vsize;
164 1.36 cdi uint64_t tte;
165 1.1 eeh };
166 1.1 eeh
167 1.61 macallan #define PMAP_NC 0x001 /* Don't cache, set the E bit in the page */
168 1.9 eeh #define PMAP_NVC 0x002 /* Don't enable the virtual cache */
169 1.9 eeh #define PMAP_LITTLE 0x004 /* Map in little endian mode */
170 1.23 chs /* Large page size hints --
171 1.23 chs we really should use another param to pmap_enter() */
172 1.9 eeh #define PMAP_8K 0x000
173 1.9 eeh #define PMAP_64K 0x008 /* Use 64K page */
174 1.9 eeh #define PMAP_512K 0x010
175 1.9 eeh #define PMAP_4M 0x018
176 1.9 eeh #define PMAP_SZ_TO_TTE(x) (((x)&0x018)<<58)
177 1.23 chs /* If these bits are different in va's to the same PA
178 1.23 chs then there is an aliasing in the d$ */
179 1.30 petrov #define VA_ALIAS_MASK (1 << 13)
180 1.61 macallan #define PMAP_WC 0x20 /* allow write combinimg */
181 1.1 eeh
182 1.1 eeh #ifdef _KERNEL
183 1.25 martin #ifdef PMAP_COUNT_DEBUG
184 1.25 martin /* diagnostic versions if PMAP_COUNT_DEBUG option is used */
185 1.37 cdi int pmap_count_res(struct pmap *);
186 1.37 cdi int pmap_count_wired(struct pmap *);
187 1.21 eeh #define pmap_resident_count(pm) pmap_count_res((pm))
188 1.21 eeh #define pmap_wired_count(pm) pmap_count_wired((pm))
189 1.25 martin #else
190 1.25 martin #define pmap_resident_count(pm) ((pm)->pm_stats.resident_count)
191 1.25 martin #define pmap_wired_count(pm) ((pm)->pm_stats.wired_count)
192 1.25 martin #endif
193 1.25 martin
194 1.21 eeh #define pmap_phys_address(x) (x)
195 1.23 chs
196 1.23 chs void pmap_activate_pmap(struct pmap *);
197 1.31 chs void pmap_update(struct pmap *);
198 1.37 cdi void pmap_bootstrap(u_long, u_long);
199 1.58 martin
200 1.11 eeh /* make sure all page mappings are modulo 16K to prevent d$ aliasing */
201 1.58 martin #define PMAP_PREFER(fo, va, sz, td) pmap_prefer((fo), (va), (td))
202 1.58 martin static inline void
203 1.58 martin pmap_prefer(vaddr_t fo, vaddr_t *va, int td)
204 1.58 martin {
205 1.58 martin vaddr_t newva;
206 1.58 martin vaddr_t m;
207 1.58 martin
208 1.58 martin m = 2 * PAGE_SIZE;
209 1.58 martin newva = (*va & ~(m - 1)) | (fo & (m - 1));
210 1.58 martin
211 1.58 martin if (td) {
212 1.58 martin if (newva > *va)
213 1.58 martin newva -= m;
214 1.58 martin } else {
215 1.58 martin if (newva < *va)
216 1.58 martin newva += m;
217 1.58 martin }
218 1.58 martin *va = newva;
219 1.58 martin }
220 1.13 eeh
221 1.21 eeh #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
222 1.23 chs #define PMAP_NEED_PROCWR
223 1.23 chs
224 1.23 chs void pmap_procwr(struct proc *, vaddr_t, size_t);
225 1.1 eeh
226 1.1 eeh /* SPARC specific? */
227 1.37 cdi int pmap_dumpsize(void);
228 1.38 christos int pmap_dumpmmu(int (*)(dev_t, daddr_t, void *, size_t),
229 1.37 cdi daddr_t);
230 1.37 cdi int pmap_pa_exists(paddr_t);
231 1.37 cdi void switchexit(struct lwp *, int);
232 1.29 chs void pmap_kprotect(vaddr_t, vm_prot_t);
233 1.1 eeh
234 1.51 mrg /* SPARC64 specific */
235 1.51 mrg void pmap_copy_page_phys(paddr_t, paddr_t);
236 1.51 mrg void pmap_zero_page_phys(paddr_t);
237 1.51 mrg
238 1.57 palle #ifdef SUN4V
239 1.57 palle /* sun4v specific */
240 1.57 palle void pmap_setup_intstack_sun4v(paddr_t);
241 1.59 palle void pmap_setup_tsb_sun4v(struct tsb_desc*);
242 1.57 palle #endif
243 1.57 palle
244 1.35 cdi /* Installed physical memory, as discovered during bootstrap. */
245 1.35 cdi extern int phys_installed_size;
246 1.35 cdi extern struct mem_region *phys_installed;
247 1.35 cdi
248 1.53 uebayasi #define __HAVE_VM_PAGE_MD
249 1.53 uebayasi
250 1.53 uebayasi /*
251 1.53 uebayasi * For each struct vm_page, there is a list of all currently valid virtual
252 1.53 uebayasi * mappings of that page. An entry is a pv_entry_t.
253 1.53 uebayasi */
254 1.53 uebayasi struct pmap;
255 1.53 uebayasi typedef struct pv_entry {
256 1.53 uebayasi struct pv_entry *pv_next; /* next pv_entry */
257 1.53 uebayasi struct pmap *pv_pmap; /* pmap where mapping lies */
258 1.53 uebayasi vaddr_t pv_va; /* virtual address for mapping */
259 1.53 uebayasi } *pv_entry_t;
260 1.53 uebayasi /* PV flags encoded in the low bits of the VA of the first pv_entry */
261 1.53 uebayasi
262 1.53 uebayasi struct vm_page_md {
263 1.53 uebayasi struct pv_entry mdpg_pvh;
264 1.53 uebayasi };
265 1.53 uebayasi #define VM_MDPAGE_INIT(pg) \
266 1.53 uebayasi do { \
267 1.53 uebayasi (pg)->mdpage.mdpg_pvh.pv_next = NULL; \
268 1.53 uebayasi (pg)->mdpage.mdpg_pvh.pv_pmap = NULL; \
269 1.53 uebayasi (pg)->mdpage.mdpg_pvh.pv_va = 0; \
270 1.53 uebayasi } while (/*CONSTCOND*/0)
271 1.53 uebayasi
272 1.62 mrg #ifdef MULTIPROCESSOR
273 1.62 mrg #define pmap_ctx_cpu(PM, C) ((PM)->pm_ctx[(C)])
274 1.62 mrg #define pmap_ctx(PM) pmap_ctx_cpu((PM), cpu_number())
275 1.62 mrg #else
276 1.62 mrg #define pmap_ctx(PM) ((PM)->pm_ctx[0])
277 1.62 mrg #endif
278 1.62 mrg
279 1.1 eeh #endif /* _KERNEL */
280 1.18 martin
281 1.18 martin #endif /* _LOCORE */
282 1.1 eeh #endif /* _MACHINE_PMAP_H_ */
283