psl.h revision 1.17
1 /* $NetBSD: psl.h,v 1.17 2000/12/29 18:37:05 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)psl.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 #ifndef PSR_IMPL 48 49 /* 50 * SPARC Process Status Register (in psl.h for hysterical raisins). 51 * Of course, this register does not exist in v9, but we keep this stuff 52 * in here in case we need it for compatibility w/v7 and v8. 53 * 54 * The picture in the Sun manuals looks like this: 55 * 1 1 56 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0 57 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 58 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP | 59 * | | |n z v c| |C|F| | |S|T| | 60 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 61 */ 62 63 #define PSR_IMPL 0xf0000000 /* implementation */ 64 #define PSR_VER 0x0f000000 /* version */ 65 #define PSR_ICC 0x00f00000 /* integer condition codes */ 66 #define PSR_N 0x00800000 /* negative */ 67 #define PSR_Z 0x00400000 /* zero */ 68 #define PSR_O 0x00200000 /* overflow */ 69 #define PSR_C 0x00100000 /* carry */ 70 #define PSR_EC 0x00002000 /* coprocessor enable */ 71 #define PSR_EF 0x00001000 /* FP enable */ 72 #define PSR_PIL 0x00000f00 /* interrupt level */ 73 #define PSR_S 0x00000080 /* supervisor (kernel) mode */ 74 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */ 75 #define PSR_ET 0x00000020 /* trap enable */ 76 #define PSR_CWP 0x0000001f /* current window pointer */ 77 78 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET" 79 80 /* Interesting spl()s */ 81 #define PIL_SCSI 3 82 #define PIL_FDSOFT 4 83 #define PIL_AUSOFT 4 84 #define PIL_BIO 5 85 #define PIL_VIDEO 5 86 #define PIL_TTY 6 87 #define PIL_LPT 6 88 #define PIL_NET 6 89 #define PIL_IMP 7 90 #define PIL_CLOCK 10 91 #define PIL_FD 11 92 #define PIL_SER 12 93 #define PIL_AUD 13 94 #define PIL_HIGH 15 95 #define PIL_SCHED PIL_CLOCK 96 #define PIL_LOCK PIL_HIGH 97 98 /* 99 * SPARC V9 CCR register 100 * 101 */ 102 103 #define ICC_C 0x01L 104 #define ICC_V 0x02L 105 #define ICC_Z 0x04L 106 #define ICC_N 0x08L 107 #define XCC_SHIFT 4 108 #define XCC_C (ICC_C<<XCC_SHIFT) 109 #define XCC_V (ICC_V<<XCC_SHIFT) 110 #define XCC_Z (ICC_Z<<XCC_SHIFT) 111 #define XCC_N (ICC_N<<XCC_SHIFT) 112 113 114 /* 115 * SPARC V9 PSTATE register (what replaces the PSR in V9) 116 * 117 * Here's the layout: 118 * 119 * 11 10 9 8 7 6 5 4 3 2 1 0 120 * +------------------------------------------------------------+ 121 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 122 * +------------------------------------------------------------+ 123 */ 124 125 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 126 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 127 #define PSTATE_CLE 0x200 /* current little endian */ 128 #define PSTATE_TLE 0x100 /* traps little endian */ 129 #define PSTATE_MM 0x0c0 /* memory model */ 130 #define PSTATE_MM_TSO 0x000 /* total store order */ 131 #define PSTATE_MM_PSO 0x040 /* partial store order */ 132 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 133 #define PSTATE_RED 0x020 /* RED state */ 134 #define PSTATE_PEF 0x010 /* enable floating point */ 135 #define PSTATE_AM 0x008 /* 32-bit address masking */ 136 #define PSTATE_PRIV 0x004 /* privileged mode */ 137 #define PSTATE_IE 0x002 /* interrupt enable */ 138 #define PSTATE_AG 0x001 /* enable alternate globals */ 139 140 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 141 142 143 /* 144 * 32-bit code requires TSO or at best PSO since that's what's supported on 145 * SPARC V8 and earlier machines. 146 * 147 * 64-bit code sets the memory model in the ELF header. 148 * 149 * We're running kernel code in TSO for the moment so we don't need to worry 150 * about possible memory barrier bugs. 151 */ 152 153 #ifdef __arch64__ 154 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 155 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 156 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 157 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 158 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 159 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) 160 #else 161 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 162 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) 163 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) 164 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 165 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 166 #define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 167 #endif 168 169 /* 170 * SPARC V9 TSTATE register 171 * 172 * 39 32 31 24 23 18 17 8 7 5 4 0 173 * +-----+-----+-----+--------+---+-----+ 174 * | CCR | ASI | - | PSTATE | - | CWP | 175 * +-----+-----+-----+--------+---+-----+ 176 * */ 177 178 #define TSTATE_CWP 0x01f 179 #define TSTATE_PSTATE 0x6ff00 180 #define TSTATE_PSTATE_SHIFT 8 181 #define TSTATE_ASI 0xff000000LL 182 #define TSTATE_ASI_SHIFT 24 183 #define TSTATE_CCR 0xff00000000LL 184 #define TSTATE_CCR_SHIFT 32 185 186 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 187 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 188 189 /* 190 * These are here to simplify life. 191 */ 192 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 193 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 194 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 195 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 196 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 197 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 198 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 199 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 200 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 201 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 202 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 203 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 204 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 205 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 206 207 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 208 209 #define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 210 #define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT) 211 /* 212 * SPARC V9 VER version register. 213 * 214 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 215 * +-------+------+------+-----+-------+---+--------+ 216 * | manuf | impl | mask | - | maxtl | - | maxwin | 217 * +-------+------+------+-----+-------+---+--------+ 218 * 219 */ 220 221 #define VER_MANUF 0xffff000000000000LL 222 #define VER_MANUF_SHIFT 48 223 #define VER_IMPL 0x0000ffff00000000LL 224 #define VER_IMPL_SHIFT 32 225 #define VER_MASK 0x00000000ff000000LL 226 #define VER_MASK_SHIFT 24 227 #define VER_MAXTL 0x000000000000ff00LL 228 #define VER_MAXTL_SHIFT 8 229 #define VER_MAXWIN 0x000000000000001fLL 230 231 /* 232 * Here are a few things to help us transition between user and kernel mode: 233 */ 234 235 /* Memory models */ 236 #define KERN_MM PSTATE_MM_TSO 237 #define USER_MM PSTATE_MM_RMO 238 239 /* 240 * Register window handlers. These point to generic routines that check the 241 * stack pointer and then vector to the real handler. We could optimize this 242 * if we could guarantee only 32-bit or 64-bit stacks. 243 */ 244 #define WSTATE_KERN 026 245 #define WSTATE_USER 022 246 247 #define CWP 0x01f 248 249 /* 64-byte alignment -- this seems the best place to put this. */ 250 #define BLOCK_SIZE 64 251 #define BLOCK_ALIGN 0x3f 252 253 #if defined(_KERNEL) && !defined(_LOCORE) 254 255 extern u_int64_t ver; /* Copy of v9 version register. We need to read this only once, in locore.s. */ 256 static __inline int getpstate __P((void)); 257 static __inline void setpstate __P((int)); 258 static __inline int getcwp __P((void)); 259 static __inline void setcwp __P((int)); 260 #ifndef SPLDEBUG 261 static __inline void splx __P((int)); 262 #endif 263 static __inline u_int64_t getver __P((void)); 264 265 /* 266 * GCC pseudo-functions for manipulating privileged registers 267 */ 268 static __inline int getpstate() 269 { 270 int pstate; 271 272 __asm __volatile("rdpr %%pstate,%0" : "=r" (pstate)); 273 return (pstate); 274 } 275 276 static __inline void setpstate(newpstate) 277 int newpstate; 278 { 279 __asm __volatile("wrpr %0,0,%%pstate" : : "r" (newpstate)); 280 } 281 282 static __inline int getcwp() 283 { 284 int cwp; 285 286 __asm __volatile("rdpr %%cwp,%0" : "=r" (cwp)); 287 return (cwp); 288 } 289 290 static __inline void setcwp(newcwp) 291 int newcwp; 292 { 293 __asm __volatile("wrpr %0,0,%%cwp" : : "r" (newcwp)); 294 } 295 296 static __inline u_int64_t getver() 297 { 298 u_int64_t ver; 299 300 __asm __volatile("rdpr %%ver,%0" : "=r" (ver)); 301 return (ver); 302 } 303 304 /* 305 * GCC pseudo-functions for manipulating PIL 306 */ 307 308 #ifdef SPLDEBUG 309 void prom_printf __P((const char *fmt, ...)); 310 extern int printspl; 311 #define SPLPRINT(x) if(printspl) { int i=10000000; prom_printf x ; while(i--); } 312 #define SPL(name, newpil) \ 313 static __inline int name##X __P((const char*, int)); \ 314 static __inline int name##X(const char* file, int line) \ 315 { \ 316 int oldpil; \ 317 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 318 SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \ 319 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 320 return (oldpil); \ 321 } 322 /* A non-priority-decreasing version of SPL */ 323 #define SPLHOLD(name, newpil) \ 324 static __inline int name##X __P((const char*, int)); \ 325 static __inline int name##X(const char* file, int line) \ 326 { \ 327 int oldpil; \ 328 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 329 if (newpil <= oldpil) \ 330 return oldpil; \ 331 SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \ 332 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 333 return (oldpil); \ 334 } 335 336 #else 337 #define SPLPRINT(x) 338 #define SPL(name, newpil) \ 339 static __inline int name __P((void)); \ 340 static __inline int name() \ 341 { \ 342 int oldpil; \ 343 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 344 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 345 return (oldpil); \ 346 } 347 /* A non-priority-decreasing version of SPL */ 348 #define SPLHOLD(name, newpil) \ 349 static __inline int name __P((void)); \ 350 static __inline int name() \ 351 { \ 352 int oldpil; \ 353 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 354 if (newpil <= oldpil) \ 355 return oldpil; \ 356 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 357 return (oldpil); \ 358 } 359 #endif 360 361 SPL(spl0, 0) 362 363 SPL(spllowersoftclock, 1) 364 365 SPLHOLD(splsoftint, 1) 366 #define splsoftclock splsoftint 367 #define splsoftnet splsoftint 368 369 /* audio software interrupts are at software level 4 */ 370 SPLHOLD(splausoft, PIL_AUSOFT) 371 372 /* floppy software interrupts are at software level 4 too */ 373 SPLHOLD(splfdsoft, PIL_FDSOFT) 374 375 /* Block devices */ 376 SPLHOLD(splbio, PIL_BIO) 377 378 /* network hardware interrupts are at level 6 */ 379 SPLHOLD(splnet, PIL_NET) 380 381 /* tty input runs at software level 6 */ 382 SPLHOLD(spltty, PIL_TTY) 383 384 /* parallel port runs at software level 6 */ 385 SPLHOLD(spllpt, PIL_LPT) 386 387 /* 388 * Memory allocation (must be as high as highest network, tty, or disk device) 389 */ 390 SPLHOLD(splimp, PIL_IMP) 391 SPLHOLD(splpmap, PIL_IMP) 392 393 SPLHOLD(splclock, PIL_CLOCK) 394 395 /* fd hardware interrupts are at level 11 */ 396 SPLHOLD(splfd, PIL_FD) 397 398 /* zs hardware interrupts are at level 12 */ 399 SPLHOLD(splzs, PIL_SER) 400 SPLHOLD(splserial, PIL_SER) 401 402 /* audio hardware interrupts are at level 13 */ 403 SPLHOLD(splaudio, PIL_AUD) 404 405 /* second sparc timer interrupts at level 14 */ 406 SPLHOLD(splstatclock, 14) 407 408 SPLHOLD(splsched, PIL_SCHED) 409 SPLHOLD(spllock, PIL_LOCK) 410 411 SPLHOLD(splhigh, PIL_HIGH) 412 413 /* splx does not have a return value */ 414 #ifdef SPLDEBUG 415 /* Keep gcc happy -- reduce warnings */ 416 #if 0 417 static __inline void splx(newpil) 418 int newpil; 419 { 420 int pil; 421 422 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 423 SPLPRINT(("{%d->%d}", pil, newpil)); \ 424 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 425 } 426 #endif 427 428 #define spl0() spl0X(__FILE__, __LINE__) 429 #define spllowersoftclock() spllowersoftclockX(__FILE__, __LINE__) 430 #define splsoftint() splsoftintX(__FILE__, __LINE__) 431 #define splausoft() splausoftX(__FILE__, __LINE__) 432 #define splfdsoft() splfdsoftX(__FILE__, __LINE__) 433 #define splbio() splbioX(__FILE__, __LINE__) 434 #define splnet() splnetX(__FILE__, __LINE__) 435 #define spltty() splttyX(__FILE__, __LINE__) 436 #define spllpt() spllptX(__FILE__, __LINE__) 437 #define splimp() splimpX(__FILE__, __LINE__) 438 #define splpmap() splpmapX(__FILE__, __LINE__) 439 #define splclock() splclockX(__FILE__, __LINE__) 440 #define splfd() splfdX(__FILE__, __LINE__) 441 #define splzs() splzsX(__FILE__, __LINE__) 442 #define splserial() splzerialX(__FILE__, __LINE__) 443 #define splaudio() splaudioX(__FILE__, __LINE__) 444 #define splstatclock() splstatclockX(__FILE__, __LINE__) 445 #define splsched() splschedX(__FILE__, __LINE__) 446 #define spllock() spllockX(__FILE__, __LINE__) 447 #define splhigh() splhighX(__FILE__, __LINE__) 448 #define splx(x) splxX((x),__FILE__, __LINE__) 449 450 static __inline void splxX __P((int, const char*, int)); 451 static __inline void splxX(newpil, file, line) 452 int newpil, line; 453 const char* file; 454 #else 455 static __inline void splx(newpil) 456 int newpil; 457 #endif 458 { 459 int pil; 460 461 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 462 SPLPRINT(("{%d->%d}", pil, newpil)); \ 463 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 464 } 465 #endif /* KERNEL && !_LOCORE */ 466 467 #endif /* PSR_IMPL */ 468
Indexes created Sat Sep 27 14:09:57 GMT 2025