psl.h revision 1.19
1 /* $NetBSD: psl.h,v 1.19 2001/03/02 07:36:57 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)psl.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 #ifndef PSR_IMPL 48 49 /* 50 * SPARC Process Status Register (in psl.h for hysterical raisins). This 51 * doesn't exist on the V9. 52 * 53 * The picture in the Sun manuals looks like this: 54 * 1 1 55 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0 56 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 57 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP | 58 * | | |n z v c| |C|F| | |S|T| | 59 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 60 */ 61 62 #define PSR_IMPL 0xf0000000 /* implementation */ 63 #define PSR_VER 0x0f000000 /* version */ 64 #define PSR_ICC 0x00f00000 /* integer condition codes */ 65 #define PSR_N 0x00800000 /* negative */ 66 #define PSR_Z 0x00400000 /* zero */ 67 #define PSR_O 0x00200000 /* overflow */ 68 #define PSR_C 0x00100000 /* carry */ 69 #define PSR_EC 0x00002000 /* coprocessor enable */ 70 #define PSR_EF 0x00001000 /* FP enable */ 71 #define PSR_PIL 0x00000f00 /* interrupt level */ 72 #define PSR_S 0x00000080 /* supervisor (kernel) mode */ 73 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */ 74 #define PSR_ET 0x00000020 /* trap enable */ 75 #define PSR_CWP 0x0000001f /* current window pointer */ 76 77 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET" 78 79 /* Interesting spl()s */ 80 #define PIL_SCSI 3 81 #define PIL_FDSOFT 4 82 #define PIL_AUSOFT 4 83 #define PIL_BIO 5 84 #define PIL_VIDEO 5 85 #define PIL_TTY 6 86 #define PIL_LPT 6 87 #define PIL_NET 6 88 #define PIL_IMP 7 89 #define PIL_CLOCK 10 90 #define PIL_FD 11 91 #define PIL_SER 12 92 #define PIL_AUD 13 93 #define PIL_HIGH 15 94 #define PIL_SCHED PIL_CLOCK 95 #define PIL_LOCK PIL_HIGH 96 97 /* 98 * SPARC V9 CCR register 99 */ 100 101 #define ICC_C 0x01L 102 #define ICC_V 0x02L 103 #define ICC_Z 0x04L 104 #define ICC_N 0x08L 105 #define XCC_SHIFT 4 106 #define XCC_C (ICC_C<<XCC_SHIFT) 107 #define XCC_V (ICC_V<<XCC_SHIFT) 108 #define XCC_Z (ICC_Z<<XCC_SHIFT) 109 #define XCC_N (ICC_N<<XCC_SHIFT) 110 111 112 /* 113 * SPARC V9 PSTATE register (what replaces the PSR in V9) 114 * 115 * Here's the layout: 116 * 117 * 11 10 9 8 7 6 5 4 3 2 1 0 118 * +------------------------------------------------------------+ 119 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 120 * +------------------------------------------------------------+ 121 */ 122 123 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 124 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 125 #define PSTATE_CLE 0x200 /* current little endian */ 126 #define PSTATE_TLE 0x100 /* traps little endian */ 127 #define PSTATE_MM 0x0c0 /* memory model */ 128 #define PSTATE_MM_TSO 0x000 /* total store order */ 129 #define PSTATE_MM_PSO 0x040 /* partial store order */ 130 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 131 #define PSTATE_RED 0x020 /* RED state */ 132 #define PSTATE_PEF 0x010 /* enable floating point */ 133 #define PSTATE_AM 0x008 /* 32-bit address masking */ 134 #define PSTATE_PRIV 0x004 /* privileged mode */ 135 #define PSTATE_IE 0x002 /* interrupt enable */ 136 #define PSTATE_AG 0x001 /* enable alternate globals */ 137 138 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 139 140 141 /* 142 * 32-bit code requires TSO or at best PSO since that's what's supported on 143 * SPARC V8 and earlier machines. 144 * 145 * 64-bit code sets the memory model in the ELF header. 146 * 147 * We're running kernel code in TSO for the moment so we don't need to worry 148 * about possible memory barrier bugs. 149 */ 150 151 #ifdef __arch64__ 152 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 153 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 154 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 155 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 156 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 157 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) 158 #else 159 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 160 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) 161 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) 162 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 163 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 164 #define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 165 #endif 166 167 168 /* 169 * SPARC V9 TSTATE register 170 * 171 * 39 32 31 24 23 18 17 8 7 5 4 0 172 * +-----+-----+-----+--------+---+-----+ 173 * | CCR | ASI | - | PSTATE | - | CWP | 174 * +-----+-----+-----+--------+---+-----+ 175 */ 176 177 #define TSTATE_CWP 0x01f 178 #define TSTATE_PSTATE 0x6ff00 179 #define TSTATE_PSTATE_SHIFT 8 180 #define TSTATE_ASI 0xff000000LL 181 #define TSTATE_ASI_SHIFT 24 182 #define TSTATE_CCR 0xff00000000LL 183 #define TSTATE_CCR_SHIFT 32 184 185 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 186 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 187 188 /* 189 * These are here to simplify life. 190 */ 191 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 192 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 193 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 194 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 195 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 196 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 197 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 198 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 199 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 200 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 201 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 202 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 203 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 204 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 205 206 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 207 208 #define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 209 #define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT) 210 /* 211 * SPARC V9 VER version register. 212 * 213 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 214 * +-------+------+------+-----+-------+---+--------+ 215 * | manuf | impl | mask | - | maxtl | - | maxwin | 216 * +-------+------+------+-----+-------+---+--------+ 217 * 218 */ 219 220 #define VER_MANUF 0xffff000000000000LL 221 #define VER_MANUF_SHIFT 48 222 #define VER_IMPL 0x0000ffff00000000LL 223 #define VER_IMPL_SHIFT 32 224 #define VER_MASK 0x00000000ff000000LL 225 #define VER_MASK_SHIFT 24 226 #define VER_MAXTL 0x000000000000ff00LL 227 #define VER_MAXTL_SHIFT 8 228 #define VER_MAXWIN 0x000000000000001fLL 229 230 /* 231 * Here are a few things to help us transition between user and kernel mode: 232 */ 233 234 /* Memory models */ 235 #define KERN_MM PSTATE_MM_TSO 236 #define USER_MM PSTATE_MM_RMO 237 238 /* 239 * Register window handlers. These point to generic routines that check the 240 * stack pointer and then vector to the real handler. We could optimize this 241 * if we could guarantee only 32-bit or 64-bit stacks. 242 */ 243 #define WSTATE_KERN 026 244 #define WSTATE_USER 022 245 246 #define CWP 0x01f 247 248 /* 64-byte alignment -- this seems the best place to put this. */ 249 #define BLOCK_SIZE 64 250 #define BLOCK_ALIGN 0x3f 251 252 #if defined(_KERNEL) && !defined(_LOCORE) 253 254 extern u_int64_t ver; /* Copy of v9 version register. We need to read this only once, in locore.s. */ 255 static __inline int getpstate __P((void)); 256 static __inline void setpstate __P((int)); 257 static __inline int getcwp __P((void)); 258 static __inline void setcwp __P((int)); 259 #ifndef SPLDEBUG 260 static __inline void splx __P((int)); 261 #endif 262 static __inline u_int64_t getver __P((void)); 263 264 /* 265 * GCC pseudo-functions for manipulating privileged registers 266 */ 267 static __inline int getpstate() 268 { 269 int pstate; 270 271 __asm __volatile("rdpr %%pstate,%0" : "=r" (pstate)); 272 return (pstate); 273 } 274 275 static __inline void setpstate(newpstate) 276 int newpstate; 277 { 278 __asm __volatile("wrpr %0,0,%%pstate" : : "r" (newpstate)); 279 } 280 281 static __inline int getcwp() 282 { 283 int cwp; 284 285 __asm __volatile("rdpr %%cwp,%0" : "=r" (cwp)); 286 return (cwp); 287 } 288 289 static __inline void setcwp(newcwp) 290 int newcwp; 291 { 292 __asm __volatile("wrpr %0,0,%%cwp" : : "r" (newcwp)); 293 } 294 295 static __inline u_int64_t getver() 296 { 297 u_int64_t ver; 298 299 __asm __volatile("rdpr %%ver,%0" : "=r" (ver)); 300 return (ver); 301 } 302 303 /* 304 * GCC pseudo-functions for manipulating PIL 305 */ 306 307 #ifdef SPLDEBUG 308 void prom_printf __P((const char *fmt, ...)); 309 extern int printspl; 310 #define SPLPRINT(x) if(printspl) { int i=10000000; prom_printf x ; while(i--); } 311 #define SPL(name, newpil) \ 312 static __inline int name##X __P((const char*, int)); \ 313 static __inline int name##X(const char* file, int line) \ 314 { \ 315 int oldpil; \ 316 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 317 SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \ 318 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 319 return (oldpil); \ 320 } 321 /* A non-priority-decreasing version of SPL */ 322 #define SPLHOLD(name, newpil) \ 323 static __inline int name##X __P((const char*, int)); \ 324 static __inline int name##X(const char* file, int line) \ 325 { \ 326 int oldpil; \ 327 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 328 if (newpil <= oldpil) \ 329 return oldpil; \ 330 SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \ 331 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 332 return (oldpil); \ 333 } 334 335 #else 336 #define SPLPRINT(x) 337 #define SPL(name, newpil) \ 338 static __inline int name __P((void)); \ 339 static __inline int name() \ 340 { \ 341 int oldpil; \ 342 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 343 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 344 return (oldpil); \ 345 } 346 /* A non-priority-decreasing version of SPL */ 347 #define SPLHOLD(name, newpil) \ 348 static __inline int name __P((void)); \ 349 static __inline int name() \ 350 { \ 351 int oldpil; \ 352 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 353 if (newpil <= oldpil) \ 354 return oldpil; \ 355 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 356 return (oldpil); \ 357 } 358 #endif 359 360 SPL(spl0, 0) 361 362 SPL(spllowersoftclock, 1) 363 364 SPLHOLD(splsoftint, 1) 365 #define splsoftclock splsoftint 366 #define splsoftnet splsoftint 367 368 /* audio software interrupts are at software level 4 */ 369 SPLHOLD(splausoft, PIL_AUSOFT) 370 371 /* floppy software interrupts are at software level 4 too */ 372 SPLHOLD(splfdsoft, PIL_FDSOFT) 373 374 /* Block devices */ 375 SPLHOLD(splbio, PIL_BIO) 376 377 /* network hardware interrupts are at level 6 */ 378 SPLHOLD(splnet, PIL_NET) 379 380 /* tty input runs at software level 6 */ 381 SPLHOLD(spltty, PIL_TTY) 382 383 /* parallel port runs at software level 6 */ 384 SPLHOLD(spllpt, PIL_LPT) 385 386 /* 387 * Memory allocation (must be as high as highest network, tty, or disk device) 388 */ 389 SPLHOLD(splimp, PIL_IMP) 390 SPLHOLD(splvm, PIL_IMP) 391 392 SPLHOLD(splclock, PIL_CLOCK) 393 394 /* fd hardware interrupts are at level 11 */ 395 SPLHOLD(splfd, PIL_FD) 396 397 /* zs hardware interrupts are at level 12 */ 398 SPLHOLD(splzs, PIL_SER) 399 SPLHOLD(splserial, PIL_SER) 400 401 /* audio hardware interrupts are at level 13 */ 402 SPLHOLD(splaudio, PIL_AUD) 403 404 /* second sparc timer interrupts at level 14 */ 405 SPLHOLD(splstatclock, 14) 406 407 SPLHOLD(splsched, PIL_SCHED) 408 SPLHOLD(spllock, PIL_LOCK) 409 410 SPLHOLD(splhigh, PIL_HIGH) 411 412 /* splx does not have a return value */ 413 #ifdef SPLDEBUG 414 /* Keep gcc happy -- reduce warnings */ 415 #if 0 416 static __inline void splx(newpil) 417 int newpil; 418 { 419 int pil; 420 421 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 422 SPLPRINT(("{%d->%d}", pil, newpil)); \ 423 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 424 } 425 #endif 426 427 #define spl0() spl0X(__FILE__, __LINE__) 428 #define spllowersoftclock() spllowersoftclockX(__FILE__, __LINE__) 429 #define splsoftint() splsoftintX(__FILE__, __LINE__) 430 #define splausoft() splausoftX(__FILE__, __LINE__) 431 #define splfdsoft() splfdsoftX(__FILE__, __LINE__) 432 #define splbio() splbioX(__FILE__, __LINE__) 433 #define splnet() splnetX(__FILE__, __LINE__) 434 #define spltty() splttyX(__FILE__, __LINE__) 435 #define spllpt() spllptX(__FILE__, __LINE__) 436 #define splimp() splimpX(__FILE__, __LINE__) 437 #define splvm() splvmX(__FILE__, __LINE__) 438 #define splclock() splclockX(__FILE__, __LINE__) 439 #define splfd() splfdX(__FILE__, __LINE__) 440 #define splzs() splzsX(__FILE__, __LINE__) 441 #define splserial() splzerialX(__FILE__, __LINE__) 442 #define splaudio() splaudioX(__FILE__, __LINE__) 443 #define splstatclock() splstatclockX(__FILE__, __LINE__) 444 #define splsched() splschedX(__FILE__, __LINE__) 445 #define spllock() spllockX(__FILE__, __LINE__) 446 #define splhigh() splhighX(__FILE__, __LINE__) 447 #define splx(x) splxX((x),__FILE__, __LINE__) 448 449 static __inline void splxX __P((int, const char*, int)); 450 static __inline void splxX(newpil, file, line) 451 int newpil, line; 452 const char* file; 453 #else 454 static __inline void splx(newpil) 455 int newpil; 456 #endif 457 { 458 int pil; 459 460 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 461 SPLPRINT(("{%d->%d}", pil, newpil)); \ 462 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 463 } 464 #endif /* KERNEL && !_LOCORE */ 465 466 #endif /* PSR_IMPL */ 467
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