psl.h revision 1.24
1 /* $NetBSD: psl.h,v 1.24 2003/11/09 21:52:31 petrov Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)psl.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 #ifndef PSR_IMPL 44 45 /* 46 * SPARC Process Status Register (in psl.h for hysterical raisins). This 47 * doesn't exist on the V9. 48 * 49 * The picture in the Sun manuals looks like this: 50 * 1 1 51 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0 52 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 53 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP | 54 * | | |n z v c| |C|F| | |S|T| | 55 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 56 */ 57 58 #define PSR_IMPL 0xf0000000 /* implementation */ 59 #define PSR_VER 0x0f000000 /* version */ 60 #define PSR_ICC 0x00f00000 /* integer condition codes */ 61 #define PSR_N 0x00800000 /* negative */ 62 #define PSR_Z 0x00400000 /* zero */ 63 #define PSR_O 0x00200000 /* overflow */ 64 #define PSR_C 0x00100000 /* carry */ 65 #define PSR_EC 0x00002000 /* coprocessor enable */ 66 #define PSR_EF 0x00001000 /* FP enable */ 67 #define PSR_PIL 0x00000f00 /* interrupt level */ 68 #define PSR_S 0x00000080 /* supervisor (kernel) mode */ 69 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */ 70 #define PSR_ET 0x00000020 /* trap enable */ 71 #define PSR_CWP 0x0000001f /* current window pointer */ 72 73 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET" 74 75 /* Interesting spl()s */ 76 #define PIL_SCSI 3 77 #define PIL_FDSOFT 4 78 #define PIL_AUSOFT 4 79 #define PIL_BIO 5 80 #define PIL_VIDEO 5 81 #define PIL_TTY 6 82 #define PIL_LPT 6 83 #define PIL_NET 6 84 #define PIL_IMP 7 85 #define PIL_AUD 8 86 #define PIL_CLOCK 10 87 #define PIL_FD 11 88 #define PIL_SER 12 89 #define PIL_HIGH 15 90 #define PIL_SCHED PIL_CLOCK 91 #define PIL_LOCK PIL_HIGH 92 93 /* 94 * SPARC V9 CCR register 95 */ 96 97 #define ICC_C 0x01L 98 #define ICC_V 0x02L 99 #define ICC_Z 0x04L 100 #define ICC_N 0x08L 101 #define XCC_SHIFT 4 102 #define XCC_C (ICC_C<<XCC_SHIFT) 103 #define XCC_V (ICC_V<<XCC_SHIFT) 104 #define XCC_Z (ICC_Z<<XCC_SHIFT) 105 #define XCC_N (ICC_N<<XCC_SHIFT) 106 107 108 /* 109 * SPARC V9 PSTATE register (what replaces the PSR in V9) 110 * 111 * Here's the layout: 112 * 113 * 11 10 9 8 7 6 5 4 3 2 1 0 114 * +------------------------------------------------------------+ 115 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 116 * +------------------------------------------------------------+ 117 */ 118 119 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 120 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 121 #define PSTATE_CLE 0x200 /* current little endian */ 122 #define PSTATE_TLE 0x100 /* traps little endian */ 123 #define PSTATE_MM 0x0c0 /* memory model */ 124 #define PSTATE_MM_TSO 0x000 /* total store order */ 125 #define PSTATE_MM_PSO 0x040 /* partial store order */ 126 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 127 #define PSTATE_RED 0x020 /* RED state */ 128 #define PSTATE_PEF 0x010 /* enable floating point */ 129 #define PSTATE_AM 0x008 /* 32-bit address masking */ 130 #define PSTATE_PRIV 0x004 /* privileged mode */ 131 #define PSTATE_IE 0x002 /* interrupt enable */ 132 #define PSTATE_AG 0x001 /* enable alternate globals */ 133 134 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 135 136 137 /* 138 * 32-bit code requires TSO or at best PSO since that's what's supported on 139 * SPARC V8 and earlier machines. 140 * 141 * 64-bit code sets the memory model in the ELF header. 142 * 143 * We're running kernel code in TSO for the moment so we don't need to worry 144 * about possible memory barrier bugs. 145 */ 146 147 #ifdef __arch64__ 148 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 149 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 150 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 151 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 152 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 153 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) 154 #else 155 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 156 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) 157 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) 158 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 159 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 160 #define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 161 #endif 162 163 164 /* 165 * SPARC V9 TSTATE register 166 * 167 * 39 32 31 24 23 18 17 8 7 5 4 0 168 * +-----+-----+-----+--------+---+-----+ 169 * | CCR | ASI | - | PSTATE | - | CWP | 170 * +-----+-----+-----+--------+---+-----+ 171 */ 172 173 #define TSTATE_CWP 0x01f 174 #define TSTATE_PSTATE 0x6ff00 175 #define TSTATE_PSTATE_SHIFT 8 176 #define TSTATE_ASI 0xff000000LL 177 #define TSTATE_ASI_SHIFT 24 178 #define TSTATE_CCR 0xff00000000LL 179 #define TSTATE_CCR_SHIFT 32 180 181 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 182 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 183 184 /* 185 * These are here to simplify life. 186 */ 187 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 188 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 189 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 190 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 191 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 192 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 193 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 194 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 195 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 196 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 197 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 198 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 199 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 200 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 201 202 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 203 204 #define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 205 #define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT) 206 /* 207 * SPARC V9 VER version register. 208 * 209 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 210 * +-------+------+------+-----+-------+---+--------+ 211 * | manuf | impl | mask | - | maxtl | - | maxwin | 212 * +-------+------+------+-----+-------+---+--------+ 213 * 214 */ 215 216 #define VER_MANUF 0xffff000000000000LL 217 #define VER_MANUF_SHIFT 48 218 #define VER_IMPL 0x0000ffff00000000LL 219 #define VER_IMPL_SHIFT 32 220 #define VER_MASK 0x00000000ff000000LL 221 #define VER_MASK_SHIFT 24 222 #define VER_MAXTL 0x000000000000ff00LL 223 #define VER_MAXTL_SHIFT 8 224 #define VER_MAXWIN 0x000000000000001fLL 225 226 /* 227 * Here are a few things to help us transition between user and kernel mode: 228 */ 229 230 /* Memory models */ 231 #define KERN_MM PSTATE_MM_TSO 232 #define USER_MM PSTATE_MM_RMO 233 234 /* 235 * Register window handlers. These point to generic routines that check the 236 * stack pointer and then vector to the real handler. We could optimize this 237 * if we could guarantee only 32-bit or 64-bit stacks. 238 */ 239 #define WSTATE_KERN 026 240 #define WSTATE_USER 022 241 242 #define CWP 0x01f 243 244 /* 64-byte alignment -- this seems the best place to put this. */ 245 #define BLOCK_SIZE 64 246 #define BLOCK_ALIGN 0x3f 247 248 #if defined(_KERNEL) && !defined(_LOCORE) 249 250 extern u_int64_t ver; /* Copy of v9 version register. We need to read this only once, in locore.s. */ 251 static __inline int getpstate __P((void)); 252 static __inline void setpstate __P((int)); 253 static __inline int getcwp __P((void)); 254 static __inline void setcwp __P((int)); 255 #ifndef SPLDEBUG 256 static __inline void splx __P((int)); 257 #endif 258 static __inline u_int64_t getver __P((void)); 259 260 /* 261 * GCC pseudo-functions for manipulating privileged registers 262 */ 263 static __inline int getpstate() 264 { 265 int pstate; 266 267 __asm __volatile("rdpr %%pstate,%0" : "=r" (pstate)); 268 return (pstate); 269 } 270 271 static __inline void setpstate(newpstate) 272 int newpstate; 273 { 274 __asm __volatile("wrpr %0,0,%%pstate" : : "r" (newpstate)); 275 } 276 277 static __inline int getcwp() 278 { 279 int cwp; 280 281 __asm __volatile("rdpr %%cwp,%0" : "=r" (cwp)); 282 return (cwp); 283 } 284 285 static __inline void setcwp(newcwp) 286 int newcwp; 287 { 288 __asm __volatile("wrpr %0,0,%%cwp" : : "r" (newcwp)); 289 } 290 291 static __inline u_int64_t getver() 292 { 293 u_int64_t ver; 294 295 __asm __volatile("rdpr %%ver,%0" : "=r" (ver)); 296 return (ver); 297 } 298 299 /* 300 * GCC pseudo-functions for manipulating PIL 301 */ 302 303 #ifdef SPLDEBUG 304 void prom_printf __P((const char *fmt, ...)); 305 extern int printspl; 306 #define SPLPRINT(x) \ 307 { \ 308 if (printspl) { \ 309 int i = 10000000; \ 310 prom_printf x ; \ 311 while (i--) \ 312 ; \ 313 } \ 314 } 315 #define SPL(name, newpil) \ 316 static __inline int name##X __P((const char*, int)); \ 317 static __inline int name##X(const char* file, int line) \ 318 { \ 319 int oldpil; \ 320 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 321 SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \ 322 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 323 return (oldpil); \ 324 } 325 /* A non-priority-decreasing version of SPL */ 326 #define SPLHOLD(name, newpil) \ 327 static __inline int name##X __P((const char*, int)); \ 328 static __inline int name##X(const char* file, int line) \ 329 { \ 330 int oldpil; \ 331 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 332 if (newpil <= oldpil) \ 333 return oldpil; \ 334 SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \ 335 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 336 return (oldpil); \ 337 } 338 339 #else 340 #define SPLPRINT(x) 341 #define SPL(name, newpil) \ 342 static __inline int name __P((void)); \ 343 static __inline int name() \ 344 { \ 345 int oldpil; \ 346 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 347 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 348 return (oldpil); \ 349 } 350 /* A non-priority-decreasing version of SPL */ 351 #define SPLHOLD(name, newpil) \ 352 static __inline int name __P((void)); \ 353 static __inline int name() \ 354 { \ 355 int oldpil; \ 356 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 357 if (newpil <= oldpil) \ 358 return oldpil; \ 359 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 360 return (oldpil); \ 361 } 362 #endif 363 364 SPL(spl0, 0) 365 366 SPL(spllowersoftclock, 1) 367 368 SPLHOLD(splsoftint, 1) 369 #define splsoftclock splsoftint 370 #define splsoftnet splsoftint 371 372 SPLHOLD(splsoftserial, 4) 373 374 /* audio software interrupts are at software level 4 */ 375 SPLHOLD(splausoft, PIL_AUSOFT) 376 377 /* floppy software interrupts are at software level 4 too */ 378 SPLHOLD(splfdsoft, PIL_FDSOFT) 379 380 /* Block devices */ 381 SPLHOLD(splbio, PIL_BIO) 382 383 /* network hardware interrupts are at level 6 */ 384 SPLHOLD(splnet, PIL_NET) 385 386 /* tty input runs at software level 6 */ 387 SPLHOLD(spltty, PIL_TTY) 388 389 /* parallel port runs at software level 6 */ 390 SPLHOLD(spllpt, PIL_LPT) 391 392 /* 393 * Memory allocation (must be as high as highest network, tty, or disk device) 394 */ 395 SPLHOLD(splvm, PIL_IMP) 396 397 SPLHOLD(splclock, PIL_CLOCK) 398 399 /* fd hardware interrupts are at level 11 */ 400 SPLHOLD(splfd, PIL_FD) 401 402 /* zs hardware interrupts are at level 12 */ 403 SPLHOLD(splzs, PIL_SER) 404 SPLHOLD(splserial, PIL_SER) 405 406 /* audio hardware interrupts are at level 13 */ 407 SPLHOLD(splaudio, PIL_AUD) 408 409 /* second sparc timer interrupts at level 14 */ 410 SPLHOLD(splstatclock, 14) 411 412 SPLHOLD(splsched, PIL_SCHED) 413 SPLHOLD(spllock, PIL_LOCK) 414 415 SPLHOLD(splhigh, PIL_HIGH) 416 417 /* splx does not have a return value */ 418 #ifdef SPLDEBUG 419 #define spl0() spl0X(__FILE__, __LINE__) 420 #define spllowersoftclock() spllowersoftclockX(__FILE__, __LINE__) 421 #define splsoftint() splsoftintX(__FILE__, __LINE__) 422 #define splsoftserial() splsoftserialX(__FILE__, __LINE__) 423 #define splausoft() splausoftX(__FILE__, __LINE__) 424 #define splfdsoft() splfdsoftX(__FILE__, __LINE__) 425 #define splbio() splbioX(__FILE__, __LINE__) 426 #define splnet() splnetX(__FILE__, __LINE__) 427 #define spltty() splttyX(__FILE__, __LINE__) 428 #define spllpt() spllptX(__FILE__, __LINE__) 429 #define splvm() splvmX(__FILE__, __LINE__) 430 #define splclock() splclockX(__FILE__, __LINE__) 431 #define splfd() splfdX(__FILE__, __LINE__) 432 #define splzs() splzsX(__FILE__, __LINE__) 433 #define splserial() splzerialX(__FILE__, __LINE__) 434 #define splaudio() splaudioX(__FILE__, __LINE__) 435 #define splstatclock() splstatclockX(__FILE__, __LINE__) 436 #define splsched() splschedX(__FILE__, __LINE__) 437 #define spllock() spllockX(__FILE__, __LINE__) 438 #define splhigh() splhighX(__FILE__, __LINE__) 439 #define splx(x) splxX((x),__FILE__, __LINE__) 440 441 static __inline void splxX __P((int, const char*, int)); 442 static __inline void splxX(newpil, file, line) 443 int newpil; 444 const char *file; 445 int line; 446 #else 447 static __inline void splx(newpil) 448 int newpil; 449 #endif 450 { 451 #ifdef SPLDEBUG 452 int pil; 453 454 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 455 SPLPRINT(("{%d->%d}", pil, newpil)); 456 #endif 457 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 458 } 459 #endif /* KERNEL && !_LOCORE */ 460 461 #endif /* PSR_IMPL */ 462
Indexes created Sat Sep 27 22:09:54 GMT 2025