psl.h revision 1.8
1 /* $NetBSD: psl.h,v 1.8 1999/06/05 20:38:25 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)psl.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 #ifndef PSR_IMPL 48 49 /* 50 * SPARC Process Status Register (in psl.h for hysterical raisins). 51 * Of course, this register does not exist in v9, but we keep this stuff 52 * in here in case we need it for compatibility w/v7 and v8. 53 * 54 * The picture in the Sun manuals looks like this: 55 * 1 1 56 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0 57 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 58 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP | 59 * | | |n z v c| |C|F| | |S|T| | 60 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 61 */ 62 63 #define PSR_IMPL 0xf0000000 /* implementation */ 64 #define PSR_VER 0x0f000000 /* version */ 65 #define PSR_ICC 0x00f00000 /* integer condition codes */ 66 #define PSR_N 0x00800000 /* negative */ 67 #define PSR_Z 0x00400000 /* zero */ 68 #define PSR_O 0x00200000 /* overflow */ 69 #define PSR_C 0x00100000 /* carry */ 70 #define PSR_EC 0x00002000 /* coprocessor enable */ 71 #define PSR_EF 0x00001000 /* FP enable */ 72 #define PSR_PIL 0x00000f00 /* interrupt level */ 73 #define PSR_S 0x00000080 /* supervisor (kernel) mode */ 74 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */ 75 #define PSR_ET 0x00000020 /* trap enable */ 76 #define PSR_CWP 0x0000001f /* current window pointer */ 77 78 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET" 79 80 /* Interesting spl()s */ 81 #define PIL_SCSI 3 82 #define PIL_FDSOFT 4 83 #define PIL_AUSOFT 4 84 #define PIL_BIO 5 85 #define PIL_VIDEO 5 86 #define PIL_TTY 6 87 #define PIL_LPT 6 88 #define PIL_NET 6 89 #define PIL_IMP 7 90 #define PIL_CLOCK 10 91 #define PIL_FD 11 92 #define PIL_SER 12 93 #define PIL_AUD 13 94 95 /* 96 * SPARC V9 CCR register 97 * 98 */ 99 100 #define ICC_C 0x01L 101 #define ICC_V 0x02L 102 #define ICC_Z 0x04L 103 #define ICC_N 0x08L 104 #define XCC_SHIFT 4 105 #define XCC_C (ICC_C<<XCC_SHIFT) 106 #define XCC_V (ICC_V<<XCC_SHIFT) 107 #define XCC_Z (ICC_Z<<XCC_SHIFT) 108 #define XCC_N (ICC_N<<XCC_SHIFT) 109 110 111 /* 112 * SPARC V9 PSTATE register (what replaces the PSR in V9) 113 * 114 * Here's the layout: 115 * 116 * 11 10 9 8 7 6 5 4 3 2 1 0 117 * +------------------------------------------------------------+ 118 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 119 * +------------------------------------------------------------+ 120 */ 121 122 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 123 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 124 #define PSTATE_CLE 0x200 /* current little endian */ 125 #define PSTATE_TLE 0x100 /* traps little endian */ 126 #define PSTATE_MM 0x0c0 /* memory model */ 127 #define PSTATE_MM_TSO 0x000 /* total store order */ 128 #define PSTATE_MM_PSO 0x040 /* partial store order */ 129 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 130 #define PSTATE_RED 0x020 /* RED state */ 131 #define PSTATE_PEF 0x010 /* enable floating point */ 132 #define PSTATE_AM 0x008 /* 32-bit address masking */ 133 #define PSTATE_PRIV 0x004 /* privileged mode */ 134 #define PSTATE_IE 0x002 /* interrupt enable */ 135 #define PSTATE_AG 0x001 /* enable alternate globals */ 136 137 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 138 139 #ifdef __arch64__ 140 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 141 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 142 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 143 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 144 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) /* It's easier to debug */ 145 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_AM|PSTATE_IE) 146 #else 147 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 148 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) 149 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) 150 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 151 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) /* It's easier to debug */ 152 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_AM|PSTATE_IE) 153 #endif 154 155 /* 156 * SPARC V9 TSTATE register 157 * 158 * 39 32 31 24 23 18 17 8 7 5 4 0 159 * +-----+-----+-----+--------+---+-----+ 160 * | CCR | ASI | - | PSTATE | - | CWP | 161 * +-----+-----+-----+--------+---+-----+ 162 * 163 */ 164 165 #define TSTATE_CWP 0x01f 166 #define TSTATE_PSTATE 0x6ff00 167 #define TSTATE_PSTATE_SHIFT 8 168 #define TSTATE_ASI 0xff000000LL 169 #define TSTATE_ASI_SHIFT 24 170 #define TSTATE_CCR 0xff00000000LL 171 #define TSTATE_CCR_SHIFT 32 172 173 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 174 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 175 176 /* 177 * These are here to simplify life. 178 */ 179 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 180 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 181 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 182 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 183 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 184 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 185 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 186 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 187 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 188 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 189 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 190 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 191 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 192 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 193 194 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 195 196 #define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 197 #define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT) 198 /* 199 * SPARC V9 VER version register. 200 * 201 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 202 * +-------+------+------+-----+-------+---+--------+ 203 * | manuf | impl | mask | - | maxtl | - | maxwin | 204 * +-------+------+------+-----+-------+---+--------+ 205 * 206 */ 207 208 #define VER_MANUF 0xffff000000000000LL 209 #define VER_MANUF_SHIFT 48 210 #define VER_IMPL 0x0000ffff00000000LL 211 #define VER_IMPL_SHIFT 32 212 #define VER_MASK 0x00000000ff000000LL 213 #define VER_MASK_SHIFT 24 214 #define VER_MAXTL 0x000000000000ff00LL 215 #define VER_MAXTL_SHIFT 8 216 #define VER_MAXWIN 0x000000000000001fLL 217 218 /* 219 * Here are a few things to help us transition between user and kernel mode: 220 */ 221 222 /* Memory models */ 223 #define KERN_MM PSTATE_MM_TSO 224 #define USER_MM PSTATE_MM_RMO 225 226 /* 227 * Register window handlers. These point to generic routines that check the 228 * stack pointer and then vector to the real handler. We could optimize this 229 * if we could guarantee only 32-bit or 64-bit stacks. 230 */ 231 #define WSTATE_KERN 026 232 #define WSTATE_USER 022 233 234 #define CWP 0x01f 235 236 /* 64-byte alignment -- this seems the best place to put this. */ 237 #define BLOCK_SIZE 64 238 #define BLOCK_ALIGN 0x3f 239 240 #if defined(_KERNEL) && !defined(_LOCORE) 241 242 extern u_int64_t ver; /* Copy of v9 version register. We need to read this only once, in locore.s. */ 243 static __inline int getpstate __P((void)); 244 static __inline void setpstate __P((int)); 245 static __inline int getcwp __P((void)); 246 static __inline void setcwp __P((int)); 247 #ifndef SPLDEBUG 248 static __inline void splx __P((int)); 249 #endif 250 static __inline u_int64_t getver __P((void)); 251 252 /* 253 * GCC pseudo-functions for manipulating privileged registers 254 */ 255 static __inline int getpstate() 256 { 257 int pstate; 258 259 __asm __volatile("rdpr %%pstate,%0" : "=r" (pstate)); 260 return (pstate); 261 } 262 263 static __inline void setpstate(newpstate) 264 int newpstate; 265 { 266 __asm __volatile("wrpr %0,0,%%pstate" : : "r" (newpstate)); 267 } 268 269 static __inline int getcwp() 270 { 271 int cwp; 272 273 __asm __volatile("rdpr %%cwp,%0" : "=r" (cwp)); 274 return (cwp); 275 } 276 277 static __inline void setcwp(newcwp) 278 int newcwp; 279 { 280 __asm __volatile("wrpr %0,0,%%cwp" : : "r" (newcwp)); 281 } 282 283 static __inline u_int64_t getver() 284 { 285 u_int64_t ver; 286 287 __asm __volatile("rdpr %%ver,%0" : "=r" (ver)); 288 return (ver); 289 } 290 291 /* 292 * GCC pseudo-functions for manipulating PIL 293 */ 294 295 #ifdef SPLDEBUG 296 void prom_printf __P((const char *fmt, ...)); 297 extern int printspl; 298 #define SPLPRINT(x) if(printspl) { int i=10000000; prom_printf x ; while(i--); } 299 #define SPL(name, newpil) \ 300 static __inline int name##X __P((const char*, int)); \ 301 static __inline int name##X(const char* file, int line) \ 302 { \ 303 int oldpil; \ 304 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 305 SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \ 306 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 307 return (oldpil); \ 308 } 309 /* A non-priority-decreasing version of SPL */ 310 #define SPLHOLD(name, newpil) \ 311 static __inline int name##X __P((const char*, int)); \ 312 static __inline int name##X(const char* file, int line) \ 313 { \ 314 int oldpil; \ 315 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 316 if (newpil <= oldpil) \ 317 return oldpil; \ 318 SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \ 319 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 320 return (oldpil); \ 321 } 322 323 #else 324 #define SPLPRINT(x) 325 #define SPL(name, newpil) \ 326 static __inline int name __P((void)); \ 327 static __inline int name() \ 328 { \ 329 int oldpil; \ 330 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 331 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 332 return (oldpil); \ 333 } 334 /* A non-priority-decreasing version of SPL */ 335 #define SPLHOLD(name, newpil) \ 336 static __inline int name __P((void)); \ 337 static __inline int name() \ 338 { \ 339 int oldpil; \ 340 __asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \ 341 if (newpil <= oldpil) \ 342 return oldpil; \ 343 __asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \ 344 return (oldpil); \ 345 } 346 #endif 347 348 SPL(spl0, 0) 349 350 SPLHOLD(splsoftint, 1) 351 #define splsoftclock splsoftint 352 #define splsoftnet splsoftint 353 354 /* audio software interrupts are at software level 4 */ 355 SPLHOLD(splausoft, PIL_AUSOFT) 356 357 /* floppy software interrupts are at software level 4 too */ 358 SPLHOLD(splfdsoft, PIL_FDSOFT) 359 360 /* Block devices */ 361 SPLHOLD(splbio, PIL_BIO) 362 363 /* network hardware interrupts are at level 6 */ 364 SPLHOLD(splnet, PIL_NET) 365 366 /* tty input runs at software level 6 */ 367 SPLHOLD(spltty, PIL_TTY) 368 369 /* parallel port runs at software level 6 */ 370 SPLHOLD(spllpt, PIL_LPT) 371 372 /* 373 * Memory allocation (must be as high as highest network, tty, or disk device) 374 */ 375 SPLHOLD(splimp, PIL_IMP) 376 SPLHOLD(splpmap, PIL_IMP) 377 378 SPLHOLD(splclock, PIL_CLOCK) 379 380 /* fd hardware interrupts are at level 11 */ 381 SPLHOLD(splfd, PIL_FD) 382 383 /* zs hardware interrupts are at level 12 */ 384 SPLHOLD(splzs, PIL_SER) 385 SPLHOLD(splserial, PIL_SER) 386 387 /* audio hardware interrupts are at level 13 */ 388 SPLHOLD(splaudio, PIL_AUD) 389 390 /* second sparc timer interrupts at level 14 */ 391 SPLHOLD(splstatclock, 14) 392 393 SPLHOLD(splhigh, 15) 394 395 /* splx does not have a return value */ 396 #ifdef SPLDEBUG 397 /* Keep gcc happy -- reduce warnings */ 398 #if 0 399 static __inline void splx(newpil) 400 int newpil; 401 { 402 int pil; 403 404 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 405 SPLPRINT(("{%d->%d}", pil, newpil)); \ 406 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 407 } 408 #endif 409 410 #define spl0() spl0X(__FILE__, __LINE__) 411 #define splsoftint() splsoftintX(__FILE__, __LINE__) 412 #define splausoft() splausoftX(__FILE__, __LINE__) 413 #define splfdsoft() splfdsoftX(__FILE__, __LINE__) 414 #define splbio() splbioX(__FILE__, __LINE__) 415 #define splnet() splnetX(__FILE__, __LINE__) 416 #define spltty() splttyX(__FILE__, __LINE__) 417 #define spllpt() spllptX(__FILE__, __LINE__) 418 #define splimp() splimpX(__FILE__, __LINE__) 419 #define splpmap() splpmapX(__FILE__, __LINE__) 420 #define splclock() splclockX(__FILE__, __LINE__) 421 #define splfd() splfdX(__FILE__, __LINE__) 422 #define splzs() splzsX(__FILE__, __LINE__) 423 #define splserial() splzerialX(__FILE__, __LINE__) 424 #define splaudio() splaudioX(__FILE__, __LINE__) 425 #define splstatclock() splstatclockX(__FILE__, __LINE__) 426 #define splhigh() splhighX(__FILE__, __LINE__) 427 #define splx(x) splxX((x),__FILE__, __LINE__) 428 429 static __inline void splxX __P((int, const char*, int)); 430 static __inline void splxX(newpil, file, line) 431 int newpil, line; 432 const char* file; 433 #else 434 static __inline void splx(newpil) 435 int newpil; 436 #endif 437 { 438 int pil; 439 440 __asm __volatile("rdpr %%pil,%0" : "=r" (pil)); 441 SPLPRINT(("{%d->%d}", pil, newpil)); \ 442 __asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil)); 443 } 444 #endif /* KERNEL && !_LOCORE */ 445 446 #endif /* PSR_IMPL */ 447
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