pte.h revision 1.18
1 /* $NetBSD: pte.h,v 1.18 2006/09/08 23:08:05 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 #ifndef _MACHINE_PTE_H_ 27 #define _MACHINE_PTE_H_ 28 29 #if defined(_KERNEL_OPT) 30 #include "opt_sparc_arch.h" 31 #endif 32 33 /* 34 * Address translation works as follows: 35 * 36 ** 37 * For sun4u: 38 * 39 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 40 * Oh, here's the sun4u TTE for reference: 41 * 42 * struct sun4u_tte { 43 * uint64 tag_g:1, (global flag) 44 * tag_ctxt:15, (context for mapping) 45 * tag_unassigned:6, 46 * tag_va:42; (virtual address bits<64:22>) 47 * uint64 data_v:1, (valid bit) 48 * data_size:2, (page size [8K*8**<SIZE>]) 49 * data_nfo:1, (no-fault only) 50 * data_ie:1, (invert endianness [inefficient]) 51 * data_soft2:2, (reserved for S/W) 52 * data_pa:36, (physical address) 53 * data_soft:6, (reserved for S/W) 54 * data_lock:1, (lock into TLB) 55 * data_cacheable:2, (cacheability control) 56 * data_e:1, (explicit accesses only) 57 * data_priv:1, (privileged page) 58 * data_w:1, (writable) 59 * data_g:1; (same as tag_g) 60 * }; 61 */ 62 63 /* virtual address to virtual page number */ 64 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 65 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 66 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 67 68 /* virtual address to offset within page */ 69 #define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF) 70 #define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF) 71 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 72 73 /* When we go to 64-bit VAs we need to handle the hole */ 74 #define VA_VPG(va) VA_SUN4U_VPG(va) 75 #define VA_OFF(va) VA_SUN4U_OFF(va) 76 77 #define PG_SHIFT4U 13 78 #define MMU_PAGE_ALIGN 8192 79 80 /* If you know where a tte is in the tsb, how do you find its va? */ 81 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 82 83 #ifndef _LOCORE 84 /* 85 * This is the spitfire TTE. 86 * 87 * We could use bitmasks and shifts to construct this if 88 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 89 * a real pain to do this in C. 90 */ 91 #if 0 92 /* We don't use bitfeilds anyway. */ 93 struct sun4u_tag_fields { 94 uint64_t tag_g:1, /* global flag */ 95 tag_ctxt:15, /* context for mapping */ 96 tag_unassigned:6, 97 tag_va:42; /* virtual address bits<64:22> */ 98 }; 99 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 100 struct sun4u_data_fields { 101 uint64_t data_v:1, /* valid bit */ 102 data_size:2, /* page size [8K*8**<SIZE>] */ 103 data_nfo:1, /* no-fault only */ 104 data_ie:1, /* invert endianness [inefficient] */ 105 data_soft2:2, /* reserved for S/W */ 106 data_pa:36, /* physical address */ 107 data_accessed:1,/* S/W accessed bit */ 108 data_modified:1,/* S/W modified bit */ 109 data_realw:1, /* S/W real writable bit (to manage modified) */ 110 data_tsblock:1, /* S/W TSB locked entry */ 111 data_exec:1, /* S/W Executable */ 112 data_onlyexec:1,/* S/W Executable only */ 113 data_lock:1, /* lock into TLB */ 114 data_cacheable:2, /* cacheability control */ 115 data_e:1, /* explicit accesses only */ 116 data_priv:1, /* privileged page */ 117 data_w:1, /* writable */ 118 data_g:1; /* same as tag_g */ 119 }; 120 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 121 struct sun4u_tte { 122 union sun4u_tag tag; 123 union sun4u_data data; 124 }; 125 #else 126 struct sun4u_tte { 127 int64_t tag; 128 int64_t data; 129 }; 130 #endif 131 typedef struct sun4u_tte pte_t; 132 133 /* TLB shootdown handler arguments. */ 134 struct ipi_tlb_args { 135 vaddr_t ita_vaddr; 136 int ita_ctx; 137 }; 138 139 /* Assembly routines to flush TLB mappings */ 140 void sp_tlb_flush_pte(vaddr_t, int); 141 void sp_tlb_flush_ctx(int); 142 void sp_tlb_flush_all(void); 143 144 #if defined(MULTIPROCESSOR) 145 void smp_tlb_flush_pte(vaddr_t, int); 146 void smp_tlb_flush_ctx(int); 147 void smp_tlb_flush_all(void); 148 #define tlb_flush_pte(va,ctx) smp_tlb_flush_pte(va, ctx) 149 #define tlb_flush_ctx(ctx) smp_tlb_flush_ctx(ctx) 150 #define tlb_flush_all() smp_tlb_flush_all() 151 #else 152 #define tlb_flush_pte(va,ctx) sp_tlb_flush_pte(va, ctx) 153 #define tlb_flush_ctx(ctx) sp_tlb_flush_ctx(ctx) 154 #define tlb_flush_all() sp_tlb_flush_all() 155 #endif 156 157 #endif /* _LOCORE */ 158 159 /* TSB tag masks */ 160 #define CTX_MASK ((1<<13)-1) 161 #define TSB_TAG_CTX_SHIFT 48 162 #define TSB_TAG_VA_SHIFT 22 163 #define TSB_TAG_G 0x8000000000000000LL 164 165 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 166 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 167 #define TSB_TAG(g,ctx,va) ((((uint64_t)((g)!=0))<<63)|(((uint64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((uint64_t)va)>>TSB_TAG_VA_SHIFT)) 168 169 /* Page sizes */ 170 #define PGSZ_8K 0 171 #define PGSZ_64K 1 172 #define PGSZ_512K 2 173 #define PGSZ_4M 3 174 175 #define PGSZ_SHIFT 61 176 #define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT) 177 178 /* TLB data masks */ 179 #define TLB_V 0x8000000000000000LL 180 #define TLB_8K TLB_SZ(PGSZ_8K) 181 #define TLB_64K TLB_SZ(PGSZ_64K) 182 #define TLB_512K TLB_SZ(PGSZ_512K) 183 #define TLB_4M TLB_SZ(PGSZ_4M) 184 #define TLB_SZ_MASK 0x6000000000000000LL 185 #define TLB_NFO 0x1000000000000000LL 186 #define TLB_IE 0x0800000000000000LL 187 #define TLB_SOFT2_MASK 0x07fe000000000000LL 188 #define TLB_DIAG_MASK 0x0001fe0000000000LL 189 #define TLB_PA_MASK 0x000001ffffffe000LL 190 #define TLB_SOFT_MASK 0x0000000000001f80LL 191 /* S/W bits */ 192 /* Access & TSB locked bits are swapped so I can set access w/one insn */ 193 /* #define TLB_ACCESS 0x0000000000001000LL */ 194 #define TLB_ACCESS 0x0000000000000200LL 195 #define TLB_MODIFY 0x0000000000000800LL 196 #define TLB_REAL_W 0x0000000000000400LL 197 /* #define TLB_TSB_LOCK 0x0000000000000200LL */ 198 #define TLB_TSB_LOCK 0x0000000000001000LL 199 #define TLB_EXEC 0x0000000000000100LL 200 #define TLB_EXEC_ONLY 0x0000000000000080LL 201 /* H/W bits */ 202 #define TLB_L 0x0000000000000040LL 203 #define TLB_CACHE_MASK 0x0000000000000030LL 204 #define TLB_CP 0x0000000000000020LL 205 #define TLB_CV 0x0000000000000010LL 206 #define TLB_E 0x0000000000000008LL 207 #define TLB_P 0x0000000000000004LL 208 #define TLB_W 0x0000000000000002LL 209 #define TLB_G 0x0000000000000001LL 210 211 /* Use a bit in the SOFT2 area to indicate a locked mapping. */ 212 #define TLB_WIRED 0x0010000000000000LL 213 214 /* 215 * The following bits are used by locore so they should 216 * be duplicates of the above w/o the "long long" 217 */ 218 /* S/W bits */ 219 /* #define TTE_ACCESS 0x0000000000001000 */ 220 #define TTE_ACCESS 0x0000000000000200 221 #define TTE_MODIFY 0x0000000000000800 222 #define TTE_REAL_W 0x0000000000000400 223 /* #define TTE_TSB_LOCK 0x0000000000000200 */ 224 #define TTE_TSB_LOCK 0x0000000000001000 225 #define TTE_EXEC 0x0000000000000100 226 #define TTE_EXEC_ONLY 0x0000000000000080 227 /* H/W bits */ 228 #define TTE_L 0x0000000000000040 229 #define TTE_CACHE_MASK 0x0000000000000030 230 #define TTE_CP 0x0000000000000020 231 #define TTE_CV 0x0000000000000010 232 #define TTE_E 0x0000000000000008 233 #define TTE_P 0x0000000000000004 234 #define TTE_W 0x0000000000000002 235 #define TTE_G 0x0000000000000001 236 237 #define TTE_DATA_BITS "\177\20" \ 238 "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \ 239 "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \ 240 "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \ 241 "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \ 242 "b\6L\0" "b\5CP\0" "b\4CV\0" \ 243 "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0" 244 245 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 246 (((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((uint64_t)(pa))&TLB_PA_MASK)|\ 247 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ 248 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL)) 249 250 #define MMU_CACHE_VIRT 0x3 251 #define MMU_CACHE_PHYS 0x2 252 #define MMU_CACHE_NONE 0x0 253 254 /* This needs to be updated for sun4u IOMMUs */ 255 /* 256 * IOMMU PTE bits. 257 */ 258 #define IOPTE_PPN_MASK 0x07ffff00 259 #define IOPTE_PPN_SHIFT 8 260 #define IOPTE_RSVD 0x000000f1 261 #define IOPTE_WRITE 0x00000004 262 #define IOPTE_VALID 0x00000002 263 264 /* 265 * This is purely for compatibility with the old SPARC machines. 266 */ 267 #define NBPRG (1 << 24) /* bytes per region */ 268 #define RGSHIFT 24 /* log2(NBPRG) */ 269 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 270 271 #define NBPSG (1 << 18) /* bytes per segment */ 272 #define SGSHIFT 18 /* log2(NBPSG) */ 273 274 /* there is no `struct pte'; we just use `int'; this is for non-4M only */ 275 #define PG_V 0x80000000 276 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 277 278 /* virtual address to virtual region number */ 279 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 280 281 /* virtual address to virtual segment number */ 282 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 283 284 #ifndef _LOCORE 285 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 286 #endif 287 288 /* 289 * Here are the bit definitions for 4M/SRMMU pte's 290 */ 291 /* MMU TABLE ENTRIES */ 292 #define SRMMU_TETYPE 0x3 /* mask for table entry type */ 293 #define SRMMU_TEPTE 0x2 /* Page Table Entry */ 294 /* PTE FIELDS */ 295 #define SRMMU_PPNMASK 0xFFFFFF00 296 #define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */ 297 298 #endif /* _MACHINE_PTE_H_ */ 299
Indexes created Tue Sep 30 20:09:53 GMT 2025