pte.h revision 1.3
1 /* $NetBSD: pte.h,v 1.3 1998/09/05 23:57:26 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgements: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgements: 29 * This product includes software developed by Harvard University. 30 * This product includes software developed by the University of 31 * California, Berkeley and its contributors. 32 * 4. Neither the name of the University nor the names of its contributors 33 * may be used to endorse or promote products derived from this software 34 * without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 46 * SUCH DAMAGE. 47 * 48 * @(#)pte.h 8.1 (Berkeley) 6/11/93 49 */ 50 51 /* 52 * Address translation works as follows: 53 * 54 ** 55 * For sun4u: 56 * 57 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 58 * Oh, here's the sun4u TTE for reference: 59 * 60 * struct sun4u_tte { 61 * u_int64 tag_g:1, (global flag) 62 * tag_ctxt:15, (context for mapping) 63 * tag_unassigned:6, 64 * tag_va:42; (virtual address bits<64:22>) 65 * u_int64 data_v:1, (valid bit) 66 * data_size:2, (page size [8K*8**<SIZE>]) 67 * data_nfo:1, (no-fault only) 68 * data_ie:1, (invert endianness [inefficient]) 69 * data_soft2:2, (reserved for S/W) 70 * data_pa:36, (physical address) 71 * data_soft:6, (reserved for S/W) 72 * data_lock:1, (lock into TLB) 73 * data_cacheable:2, (cacheability control) 74 * data_e:1, (explicit accesses only) 75 * data_priv:1, (privileged page) 76 * data_w:1, (writeable) 77 * data_g:1; (same as tag_g) 78 * }; 79 */ 80 81 /* virtual address to virtual page number */ 82 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 83 84 /* virtual address to offset within page */ 85 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 86 87 /* When we go to 64-bit VAs we need to handle the hole */ 88 #define VA_VPG(va) VA_SUN4U_VPG(va) 89 #define VA_OFF(va) VA_SUN4U_OFF(va) 90 91 #define PG_SHIFT4U 13 92 #define MMU_PAGE_ALIGN 8192 93 94 /* If you know where a tte is in the tsb, how do you find its va? */ 95 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 96 97 #ifndef _LOCORE 98 /* 99 * This is the spitfire TTE. 100 * 101 * We could use bitmasks and shifts to construct this if 102 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 103 * a real pain to do this in C. 104 */ 105 struct sun4u_tag_fields { 106 u_int64_t tag_g:1, /* global flag */ 107 tag_ctxt:15, /* context for mapping */ 108 tag_unassigned:6, 109 tag_va:42; /* virtual address bits<64:22> */ 110 }; 111 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 112 struct sun4u_data_fields { 113 u_int64_t data_v:1, /* valid bit */ 114 data_size:2, /* page size [8K*8**<SIZE>] */ 115 data_nfo:1, /* no-fault only */ 116 data_ie:1, /* invert endianness [inefficient] */ 117 data_soft2:2, /* reserved for S/W */ 118 data_pa:36, /* physical address */ 119 data_accessed:1,/* S/W accessed bit */ 120 data_modified:1,/* S/W modified bit */ 121 data_realw:1, /* S/W real writable bit (to manage modified) */ 122 data_tsblock:1, /* S/W TSB locked entry */ 123 data_exec:1, /* S/W Executable */ 124 data_onlyexec:1,/* S/W Executable only */ 125 data_lock:1, /* lock into TLB */ 126 data_cacheable:2, /* cacheability control */ 127 data_e:1, /* explicit accesses only */ 128 data_priv:1, /* privileged page */ 129 data_w:1, /* writeable */ 130 data_g:1; /* same as tag_g */ 131 }; 132 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 133 struct sun4u_tte { 134 union sun4u_tag tag; 135 union sun4u_data data; 136 }; 137 typedef struct sun4u_tte pte_t; 138 139 /* Assembly routine to flush a mapping */ 140 extern void tlb_flush_pte __P((vaddr_t addr, int ctx)); 141 extern void tlb_flush_ctx __P((int ctx)); 142 143 #endif /* _LOCORE */ 144 145 /* TSB tag masks */ 146 #define CTX_MASK ((1<<13)-1) 147 #define TSB_TAG_CTX_SHIFT 48 148 #define TSB_TAG_VA_SHIFT 22 149 #define TSB_TAG_G 0x8000000000000000LL 150 151 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 152 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 153 #define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT)) 154 155 /* TLB data masks */ 156 #define TLB_V 0x8000000000000000LL 157 #define TLB_8K 0x0000000000000000LL 158 #define TLB_64K 0x2000000000000000LL 159 #define TLB_512K 0x4000000000000000LL 160 #define TLB_4M 0x6000000000000000LL 161 #define TLB_SZ_MASK 0x6000000000000000LL 162 #define TLB_NFO 0x1000000000000000LL 163 #define TLB_IE 0x0800000000000000LL 164 #define TLB_SOFT2_MASK 0x07fe000000000000LL 165 #define TLB_DIAG_MASK 0x0001fe0000000000LL 166 #define TLB_PA_MASK 0x000001ffffffe000LL 167 #define TLB_SOFT_MASK 0x0000000000001f80LL 168 /* S/W bits */ 169 /* Access & TSB locked bits are swapped so I can set access w/one insn */ 170 /* #define TLB_ACCESS 0x0000000000001000LL */ 171 #define TLB_ACCESS 0x0000000000000200LL 172 #define TLB_MODIFY 0x0000000000000800LL 173 #define TLB_REAL_W 0x0000000000000400LL 174 /* #define TLB_TSB_LOCK 0x0000000000000200LL */ 175 #define TLB_TSB_LOCK 0x0000000000001000LL 176 #define TLB_EXEC 0x0000000000000100LL 177 #define TLB_EXEC_ONLY 0x0000000000000080LL 178 /* H/W bits */ 179 #define TLB_L 0x0000000000000040LL 180 #define TLB_CACHE_MASK 0x0000000000000030LL 181 #define TLB_CP 0x0000000000000020LL 182 #define TLB_CV 0x0000000000000010LL 183 #define TLB_E 0x0000000000000008LL 184 #define TLB_P 0x0000000000000004LL 185 #define TLB_W 0x0000000000000002LL 186 #define TLB_G 0x0000000000000001LL 187 188 /* 189 * The following bits are used by locore so they should 190 * be duplicates of the above w/o the "long long" 191 */ 192 /* S/W bits */ 193 /* #define TTE_ACCESS 0x0000000000001000 */ 194 #define TTE_ACCESS 0x0000000000000200 195 #define TTE_MODIFY 0x0000000000000800 196 #define TTE_REAL_W 0x0000000000000400 197 /* #define TTE_TSB_LOCK 0x0000000000000200 */ 198 #define TTE_TSB_LOCK 0x0000000000001000 199 #define TTE_EXEC 0x0000000000000100 200 #define TTE_EXEC_ONLY 0x0000000000000080 201 /* H/W bits */ 202 #define TTE_L 0x0000000000000040 203 #define TTE_CACHE_MASK 0x0000000000000030 204 #define TTE_CP 0x0000000000000020 205 #define TTE_CV 0x0000000000000010 206 #define TTE_E 0x0000000000000008 207 #define TTE_P 0x0000000000000004 208 #define TTE_W 0x0000000000000002 209 #define TTE_G 0x0000000000000001 210 211 #define TTE_DATA_BITS "\177\20" \ 212 "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \ 213 "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \ 214 "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \ 215 "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \ 216 "b\6L\0" "b\5CP\0" "b\4CV\0" \ 217 "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0" 218 219 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid) \ 220 (((valid)?TLB_V:0LL)|(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\ 221 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ 222 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)) 223 224 #define MMU_CACHE_VIRT 0x3 225 #define MMU_CACHE_PHYS 0x2 226 #define MMU_CACHE_NONE 0x0 227 228 /* This needs to be updated for sun4u IOMMUs */ 229 /* 230 * IOMMU PTE bits. 231 */ 232 #define IOPTE_PPN_MASK 0x07ffff00 233 #define IOPTE_PPN_SHIFT 8 234 #define IOPTE_RSVD 0x000000f1 235 #define IOPTE_WRITE 0x00000004 236 #define IOPTE_VALID 0x00000002 237
Indexes created Mon Sep 29 03:10:08 GMT 2025