pte.h revision 1.5
1 /* $NetBSD: pte.h,v 1.5 1999/06/05 21:58:18 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 /* 27 * Address translation works as follows: 28 * 29 ** 30 * For sun4u: 31 * 32 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4. 33 * Oh, here's the sun4u TTE for reference: 34 * 35 * struct sun4u_tte { 36 * u_int64 tag_g:1, (global flag) 37 * tag_ctxt:15, (context for mapping) 38 * tag_unassigned:6, 39 * tag_va:42; (virtual address bits<64:22>) 40 * u_int64 data_v:1, (valid bit) 41 * data_size:2, (page size [8K*8**<SIZE>]) 42 * data_nfo:1, (no-fault only) 43 * data_ie:1, (invert endianness [inefficient]) 44 * data_soft2:2, (reserved for S/W) 45 * data_pa:36, (physical address) 46 * data_soft:6, (reserved for S/W) 47 * data_lock:1, (lock into TLB) 48 * data_cacheable:2, (cacheability control) 49 * data_e:1, (explicit accesses only) 50 * data_priv:1, (privileged page) 51 * data_w:1, (writeable) 52 * data_g:1; (same as tag_g) 53 * }; 54 */ 55 56 /* virtual address to virtual page number */ 57 #define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31) 58 59 /* virtual address to offset within page */ 60 #define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF) 61 62 /* When we go to 64-bit VAs we need to handle the hole */ 63 #define VA_VPG(va) VA_SUN4U_VPG(va) 64 #define VA_OFF(va) VA_SUN4U_OFF(va) 65 66 #define PG_SHIFT4U 13 67 #define MMU_PAGE_ALIGN 8192 68 69 /* If you know where a tte is in the tsb, how do you find its va? */ 70 #define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000)) 71 72 #ifndef _LOCORE 73 /* 74 * This is the spitfire TTE. 75 * 76 * We could use bitmasks and shifts to construct this if 77 * we had a 64-bit compiler w/64-bit longs. Otherwise it's 78 * a real pain to do this in C. 79 */ 80 struct sun4u_tag_fields { 81 u_int64_t tag_g:1, /* global flag */ 82 tag_ctxt:15, /* context for mapping */ 83 tag_unassigned:6, 84 tag_va:42; /* virtual address bits<64:22> */ 85 }; 86 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; }; 87 struct sun4u_data_fields { 88 u_int64_t data_v:1, /* valid bit */ 89 data_size:2, /* page size [8K*8**<SIZE>] */ 90 data_nfo:1, /* no-fault only */ 91 data_ie:1, /* invert endianness [inefficient] */ 92 data_soft2:2, /* reserved for S/W */ 93 data_pa:36, /* physical address */ 94 data_accessed:1,/* S/W accessed bit */ 95 data_modified:1,/* S/W modified bit */ 96 data_realw:1, /* S/W real writable bit (to manage modified) */ 97 data_tsblock:1, /* S/W TSB locked entry */ 98 data_exec:1, /* S/W Executable */ 99 data_onlyexec:1,/* S/W Executable only */ 100 data_lock:1, /* lock into TLB */ 101 data_cacheable:2, /* cacheability control */ 102 data_e:1, /* explicit accesses only */ 103 data_priv:1, /* privileged page */ 104 data_w:1, /* writeable */ 105 data_g:1; /* same as tag_g */ 106 }; 107 union sun4u_data { struct sun4u_data_fields f; int64_t data; }; 108 struct sun4u_tte { 109 union sun4u_tag tag; 110 union sun4u_data data; 111 }; 112 typedef struct sun4u_tte pte_t; 113 114 /* Assembly routine to flush a mapping */ 115 extern void tlb_flush_pte __P((vaddr_t addr, int ctx)); 116 extern void tlb_flush_ctx __P((int ctx)); 117 118 #endif /* _LOCORE */ 119 120 /* TSB tag masks */ 121 #define CTX_MASK ((1<<13)-1) 122 #define TSB_TAG_CTX_SHIFT 48 123 #define TSB_TAG_VA_SHIFT 22 124 #define TSB_TAG_G 0x8000000000000000LL 125 126 #define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK) 127 #define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT)) 128 #define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT)) 129 130 /* TLB data masks */ 131 #define TLB_V 0x8000000000000000LL 132 #define TLB_8K 0x0000000000000000LL 133 #define TLB_64K 0x2000000000000000LL 134 #define TLB_512K 0x4000000000000000LL 135 #define TLB_4M 0x6000000000000000LL 136 #define TLB_SZ_MASK 0x6000000000000000LL 137 #define TLB_NFO 0x1000000000000000LL 138 #define TLB_IE 0x0800000000000000LL 139 #define TLB_SOFT2_MASK 0x07fe000000000000LL 140 #define TLB_DIAG_MASK 0x0001fe0000000000LL 141 #define TLB_PA_MASK 0x000001ffffffe000LL 142 #define TLB_SOFT_MASK 0x0000000000001f80LL 143 /* S/W bits */ 144 /* Access & TSB locked bits are swapped so I can set access w/one insn */ 145 /* #define TLB_ACCESS 0x0000000000001000LL */ 146 #define TLB_ACCESS 0x0000000000000200LL 147 #define TLB_MODIFY 0x0000000000000800LL 148 #define TLB_REAL_W 0x0000000000000400LL 149 /* #define TLB_TSB_LOCK 0x0000000000000200LL */ 150 #define TLB_TSB_LOCK 0x0000000000001000LL 151 #define TLB_EXEC 0x0000000000000100LL 152 #define TLB_EXEC_ONLY 0x0000000000000080LL 153 /* H/W bits */ 154 #define TLB_L 0x0000000000000040LL 155 #define TLB_CACHE_MASK 0x0000000000000030LL 156 #define TLB_CP 0x0000000000000020LL 157 #define TLB_CV 0x0000000000000010LL 158 #define TLB_E 0x0000000000000008LL 159 #define TLB_P 0x0000000000000004LL 160 #define TLB_W 0x0000000000000002LL 161 #define TLB_G 0x0000000000000001LL 162 163 /* 164 * The following bits are used by locore so they should 165 * be duplicates of the above w/o the "long long" 166 */ 167 /* S/W bits */ 168 /* #define TTE_ACCESS 0x0000000000001000 */ 169 #define TTE_ACCESS 0x0000000000000200 170 #define TTE_MODIFY 0x0000000000000800 171 #define TTE_REAL_W 0x0000000000000400 172 /* #define TTE_TSB_LOCK 0x0000000000000200 */ 173 #define TTE_TSB_LOCK 0x0000000000001000 174 #define TTE_EXEC 0x0000000000000100 175 #define TTE_EXEC_ONLY 0x0000000000000080 176 /* H/W bits */ 177 #define TTE_L 0x0000000000000040 178 #define TTE_CACHE_MASK 0x0000000000000030 179 #define TTE_CP 0x0000000000000020 180 #define TTE_CV 0x0000000000000010 181 #define TTE_E 0x0000000000000008 182 #define TTE_P 0x0000000000000004 183 #define TTE_W 0x0000000000000002 184 #define TTE_G 0x0000000000000001 185 186 #define TTE_DATA_BITS "\177\20" \ 187 "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \ 188 "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \ 189 "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \ 190 "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \ 191 "b\6L\0" "b\5CP\0" "b\4CV\0" \ 192 "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0" 193 194 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \ 195 (((valid)?TLB_V:0LL)|(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\ 196 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\ 197 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL)) 198 199 #define MMU_CACHE_VIRT 0x3 200 #define MMU_CACHE_PHYS 0x2 201 #define MMU_CACHE_NONE 0x0 202 203 /* This needs to be updated for sun4u IOMMUs */ 204 /* 205 * IOMMU PTE bits. 206 */ 207 #define IOPTE_PPN_MASK 0x07ffff00 208 #define IOPTE_PPN_SHIFT 8 209 #define IOPTE_RSVD 0x000000f1 210 #define IOPTE_WRITE 0x00000004 211 #define IOPTE_VALID 0x00000002 212
Indexes created Mon Sep 29 21:09:56 GMT 2025