Home | History | Annotate | Line # | Download | only in include
pte.h revision 1.6 
      1 /*	$NetBSD: pte.h,v 1.6 2001/06/21 00:24:22 eeh Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1996-1999 Eduardo Horvath
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  *
     12  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
     13  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     14  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     15  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
     16  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     17  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     18  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     19  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     20  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     21  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     22  * SUCH DAMAGE.
     23  *
     24  */
     25 
     26 /*
     27  * Address translation works as follows:
     28  *
     29  **
     30  * For sun4u:
     31  *
     32  *	Take your pick; it's all S/W anyway.  We'll start by emulating a sun4.
     33  *	Oh, here's the sun4u TTE for reference:
     34  *
     35  *	struct sun4u_tte {
     36  *		u_int64	tag_g:1,	(global flag)
     37  *			tag_ctxt:15,	(context for mapping)
     38  *			tag_unassigned:6,
     39  *			tag_va:42;	(virtual address bits<64:22>)
     40  *		u_int64	data_v:1,	(valid bit)
     41  *			data_size:2,	(page size [8K*8**<SIZE>])
     42  *			data_nfo:1,	(no-fault only)
     43  *			data_ie:1,	(invert endianness [inefficient])
     44  *			data_soft2:2,	(reserved for S/W)
     45  *			data_pa:36,	(physical address)
     46  *			data_soft:6,	(reserved for S/W)
     47  *			data_lock:1,	(lock into TLB)
     48  *			data_cacheable:2,	(cacheability control)
     49  *			data_e:1,	(explicit accesses only)
     50  *			data_priv:1,	(privileged page)
     51  *			data_w:1,	(writeable)
     52  *			data_g:1;	(same as tag_g)
     53  *	};
     54  */
     55 
     56 /* virtual address to virtual page number */
     57 #define	VA_SUN4U_VPG(va)	(((int)(va) >> 13) & 31)
     58 
     59 /* virtual address to offset within page */
     60 #define VA_SUN4U_OFF(va)       	(((int)(va)) & 0x1FFF)
     61 
     62 /* When we go to 64-bit VAs we need to handle the hole */
     63 #define VA_VPG(va)	VA_SUN4U_VPG(va)
     64 #define VA_OFF(va)	VA_SUN4U_OFF(va)
     65 
     66 #define PG_SHIFT4U	13
     67 #define MMU_PAGE_ALIGN	8192
     68 
     69 /* If you know where a tte is in the tsb, how do you find its va? */
     70 #define TSBVA(i)	((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000))
     71 
     72 #ifndef _LOCORE
     73 /*
     74  *  This is the spitfire TTE.
     75  *
     76  *  We could use bitmasks and shifts to construct this if
     77  *  we had a 64-bit compiler w/64-bit longs.  Otherwise it's
     78  *  a real pain to do this in C.
     79  */
     80 struct sun4u_tag_fields {
     81 	u_int64_t	tag_g:1,	/* global flag */
     82 		tag_ctxt:15,	/* context for mapping */
     83 		tag_unassigned:6,
     84 		tag_va:42;	/* virtual address bits<64:22> */
     85 };
     86 union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; };
     87 struct sun4u_data_fields {
     88 	u_int64_t	data_v:1,	/* valid bit */
     89 		data_size:2,	/* page size [8K*8**<SIZE>] */
     90 		data_nfo:1,	/* no-fault only */
     91 		data_ie:1,	/* invert endianness [inefficient] */
     92 		data_soft2:2,	/* reserved for S/W */
     93 		data_pa:36,	/* physical address */
     94 		data_accessed:1,/* S/W accessed bit */
     95 		data_modified:1,/* S/W modified bit */
     96 		data_realw:1,	/* S/W real writable bit (to manage modified) */
     97 		data_tsblock:1,	/* S/W TSB locked entry */
     98 		data_exec:1,	/* S/W Executable */
     99 		data_onlyexec:1,/* S/W Executable only */
    100 		data_lock:1,	/* lock into TLB */
    101 		data_cacheable:2,	/* cacheability control */
    102 		data_e:1,	/* explicit accesses only */
    103 		data_priv:1,	/* privileged page */
    104 		data_w:1,	/* writeable */
    105 		data_g:1;	/* same as tag_g */
    106 };
    107 union sun4u_data { struct sun4u_data_fields f; int64_t data; };
    108 struct sun4u_tte {
    109 	union sun4u_tag tag;
    110 	union sun4u_data data;
    111 };
    112 typedef struct sun4u_tte pte_t;
    113 
    114 /* Assembly routine to flush a mapping */
    115 extern void tlb_flush_pte __P((vaddr_t addr, int ctx));
    116 extern void tlb_flush_ctx __P((int ctx));
    117 
    118 #endif /* _LOCORE */
    119 
    120 /* TSB tag masks */
    121 #define CTX_MASK		((1<<13)-1)
    122 #define TSB_TAG_CTX_SHIFT	48
    123 #define TSB_TAG_VA_SHIFT	22
    124 #define TSB_TAG_G		0x8000000000000000LL
    125 
    126 #define TSB_TAG_CTX(t)		((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK)
    127 #define TSB_TAG_VA(t)		((((int64_t)(t))<<TSB_TAG_VA_SHIFT))
    128 #define TSB_TAG(g,ctx,va)	((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT))
    129 
    130 /* Page sizes */
    131 #define	PGSZ_8K			0
    132 #define	PGSZ_64K		1
    133 #define	PGSZ_512K		2
    134 #define	PGSZ_4M			3
    135 
    136 #define	PGSZ_SHIFT		61
    137 
    138 /*
    139  * Why couldn't Sun pick better page sizes?
    140  *
    141  * Page sizes are 2**(12+(3*sz)), except for 8K which
    142  * is 2**12+1 instead of 2**12.
    143  */
    144 #define	PG_SZ(s)		(1<<(12+(s?(3*s):1)))
    145 #define	TLB_SZ(s)		(((uint64_t)(s))<<PGSZ_SHIFT)
    146 
    147 /* TLB data masks */
    148 #define TLB_V			0x8000000000000000LL
    149 #define TLB_8K			TLB_SZ(PGSZ_8K)
    150 #define TLB_64K			TLB_SZ(PGSZ_64K)
    151 #define TLB_512K		TLB_SZ(PGSZ_512K)
    152 #define TLB_4M			TLB_SZ(PGSZ_4M)
    153 #define TLB_SZ_MASK		0x6000000000000000LL
    154 #define TLB_NFO			0x1000000000000000LL
    155 #define TLB_IE			0x0800000000000000LL
    156 #define TLB_SOFT2_MASK		0x07fe000000000000LL
    157 #define TLB_DIAG_MASK		0x0001fe0000000000LL
    158 #define TLB_PA_MASK		0x000001ffffffe000LL
    159 #define TLB_SOFT_MASK		0x0000000000001f80LL
    160 /* S/W bits */
    161 /* Access & TSB locked bits are swapped so I can set access w/one insn */
    162 /* #define TLB_ACCESS		0x0000000000001000LL */
    163 #define TLB_ACCESS		0x0000000000000200LL
    164 #define TLB_MODIFY		0x0000000000000800LL
    165 #define TLB_REAL_W		0x0000000000000400LL
    166 /* #define TLB_TSB_LOCK		0x0000000000000200LL */
    167 #define TLB_TSB_LOCK		0x0000000000001000LL
    168 #define TLB_EXEC		0x0000000000000100LL
    169 #define TLB_EXEC_ONLY		0x0000000000000080LL
    170 /* H/W bits */
    171 #define TLB_L			0x0000000000000040LL
    172 #define TLB_CACHE_MASK		0x0000000000000030LL
    173 #define TLB_CP			0x0000000000000020LL
    174 #define TLB_CV			0x0000000000000010LL
    175 #define TLB_E			0x0000000000000008LL
    176 #define TLB_P			0x0000000000000004LL
    177 #define TLB_W			0x0000000000000002LL
    178 #define TLB_G			0x0000000000000001LL
    179 
    180 /*
    181  * The following bits are used by locore so they should
    182  * be duplicates of the above w/o the "long long"
    183  */
    184 /* S/W bits */
    185 /* #define TTE_ACCESS		0x0000000000001000 */
    186 #define TTE_ACCESS		0x0000000000000200
    187 #define TTE_MODIFY		0x0000000000000800
    188 #define TTE_REAL_W		0x0000000000000400
    189 /* #define TTE_TSB_LOCK		0x0000000000000200 */
    190 #define TTE_TSB_LOCK		0x0000000000001000
    191 #define TTE_EXEC		0x0000000000000100
    192 #define TTE_EXEC_ONLY		0x0000000000000080
    193 /* H/W bits */
    194 #define TTE_L			0x0000000000000040
    195 #define TTE_CACHE_MASK		0x0000000000000030
    196 #define TTE_CP			0x0000000000000020
    197 #define TTE_CV			0x0000000000000010
    198 #define TTE_E			0x0000000000000008
    199 #define TTE_P			0x0000000000000004
    200 #define TTE_W			0x0000000000000002
    201 #define TTE_G			0x0000000000000001
    202 
    203 #define TTE_DATA_BITS	"\177\20" \
    204         "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \
    205         "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \
    206         "b\74NFO\0"     "b\73IE\0"      "f\62\10SOFT2\0" \
    207         "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \
    208         "b\6L\0"        "b\5CP\0"       "b\4CV\0" \
    209         "b\3E\0"        "b\2P\0"        "b\1W\0"        "b\0G\0"
    210 
    211 #define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
    212 (((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\
    213 ((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\
    214 ((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL))
    215 
    216 #define MMU_CACHE_VIRT	0x3
    217 #define MMU_CACHE_PHYS	0x2
    218 #define MMU_CACHE_NONE	0x0
    219 
    220 /* This needs to be updated for sun4u IOMMUs */
    221 /*
    222  * IOMMU PTE bits.
    223  */
    224 #define IOPTE_PPN_MASK  0x07ffff00
    225 #define IOPTE_PPN_SHIFT 8
    226 #define IOPTE_RSVD      0x000000f1
    227 #define IOPTE_WRITE     0x00000004
    228 #define IOPTE_VALID     0x00000002
    229