zs.c revision 1.1
1 /* $NetBSD: zs.c,v 1.1 2002/03/22 00:23:53 fredette Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kgdb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/kernel.h> 57 #include <sys/proc.h> 58 #include <sys/tty.h> 59 #include <sys/time.h> 60 #include <sys/syslog.h> 61 62 #include <machine/autoconf.h> 63 #include <machine/promlib.h> 64 #include <machine/conf.h> 65 #include <machine/cpu.h> 66 #include <machine/eeprom.h> 67 #include <machine/psl.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 #include <dev/sun/kbd_ms_ttyvar.h> 73 #include <ddb/db_output.h> 74 75 #include <sun2/dev/cons.h> 76 77 #include "kbd.h" /* NKBD */ 78 #include "ms.h" /* NMS */ 79 80 /* 81 * Some warts needed by z8530tty.c - 82 * The default parity REALLY needs to be the same as the PROM uses, 83 * or you can not see messages done with printf during boot-up... 84 */ 85 int zs_def_cflag = (CREAD | CS8 | HUPCL); 86 int zs_major = 12; 87 88 /* ZS channel used as the console device (if any) */ 89 void *zs_conschan_get, *zs_conschan_put; 90 91 static u_char zs_init_reg[16] = { 92 0, /* 0: CMD (reset, etc.) */ 93 0, /* 1: No interrupts yet. */ 94 #ifdef ZS_INIT_IVECT 95 ZS_INIT_IVECT, /* 2: IVECT */ 96 #else 97 0, /* 2: IVECT */ 98 #endif 99 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 100 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 101 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 102 0, /* 6: TXSYNC/SYNCLO */ 103 0, /* 7: RXSYNC/SYNCHI */ 104 0, /* 8: alias for data port */ 105 #ifdef ZS_INIT_IVECT 106 ZSWR9_MASTER_IE, 107 #else 108 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 109 #endif 110 0, /*10: Misc. TX/RX control bits */ 111 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 112 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 113 0, /*13: BAUDHI (default=9600) */ 114 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 115 ZSWR15_BREAK_IE, 116 }; 117 118 /* Console ops */ 119 static int zscngetc __P((dev_t)); 120 static void zscnputc __P((dev_t, int)); 121 static void zscnpollc __P((dev_t, int)); 122 123 struct consdev zs_consdev = { 124 NULL, 125 NULL, 126 zscngetc, 127 zscnputc, 128 zscnpollc, 129 NULL, 130 }; 131 132 133 /**************************************************************** 134 * Autoconfig 135 ****************************************************************/ 136 137 static int zs_print __P((void *, const char *name)); 138 139 extern struct cfdriver zs_cd; 140 141 /* Interrupt handlers. */ 142 int zscheckintr __P((void *)); 143 static int zshard __P((void *)); 144 static void zssoft __P((void *)); 145 146 static int zs_get_speed __P((struct zs_chanstate *)); 147 148 /* 149 * Attach a found zs. 150 * 151 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 152 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 153 */ 154 void 155 zs_attach(zsc, zsd, pri) 156 struct zsc_softc *zsc; 157 struct zsdevice *zsd; 158 int pri; 159 { 160 struct zsc_attach_args zsc_args; 161 struct zs_chanstate *cs; 162 int s, channel, softpri = IPL_SOFTSERIAL; 163 164 if (zsd == NULL) { 165 printf("configuration incomplete\n"); 166 return; 167 } 168 169 printf(" softpri %d\n", softpri); 170 171 /* 172 * Initialize software state for each channel. 173 */ 174 for (channel = 0; channel < 2; channel++) { 175 struct zschan *zc; 176 struct device *child; 177 extern struct cfdriver zstty_cd; /* in ioconf.c */ 178 179 zsc_args.channel = channel; 180 cs = &zsc->zsc_cs_store[channel]; 181 zsc->zsc_cs[channel] = cs; 182 183 cs->cs_channel = channel; 184 cs->cs_private = NULL; 185 cs->cs_ops = &zsops_null; 186 cs->cs_brg_clk = PCLK / 16; 187 188 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 189 190 zsc_args.consdev = NULL; 191 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 192 zsc->zsc_node, 193 channel); 194 195 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 196 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 197 zsc_args.consdev = &zs_consdev; 198 } 199 200 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 201 zs_conschan_get = zc; 202 } 203 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 204 zs_conschan_put = zc; 205 } 206 207 /* Children need to set cn_dev, etc */ 208 cs->cs_reg_csr = &zc->zc_csr; 209 cs->cs_reg_data = &zc->zc_data; 210 211 bcopy(zs_init_reg, cs->cs_creg, 16); 212 bcopy(zs_init_reg, cs->cs_preg, 16); 213 214 /* XXX: Consult PROM properties for this?! */ 215 cs->cs_defspeed = zs_get_speed(cs); 216 cs->cs_defcflag = zs_def_cflag; 217 218 /* Make these correspond to cs_defcflag (-crtscts) */ 219 cs->cs_rr0_dcd = ZSRR0_DCD; 220 cs->cs_rr0_cts = 0; 221 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 222 cs->cs_wr5_rts = 0; 223 224 /* 225 * Clear the master interrupt enable. 226 * The INTENA is common to both channels, 227 * so just do it on the A channel. 228 */ 229 if (channel == 0) { 230 zs_write_reg(cs, 9, 0); 231 } 232 233 /* 234 * Look for a child driver for this channel. 235 * The child attach will setup the hardware. 236 */ 237 if (!(child = 238 config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print))) { 239 /* No sub-driver. Just reset it. */ 240 u_char reset = (channel == 0) ? 241 ZSWR9_A_RESET : ZSWR9_B_RESET; 242 s = splzs(); 243 zs_write_reg(cs, 9, reset); 244 splx(s); 245 } 246 #if (NKBD > 0) || (NMS > 0) 247 /* 248 * If this was a zstty it has a keyboard 249 * property on it we need to attach the 250 * sunkbd and sunms line disciplines. 251 */ 252 if (child 253 && (child->dv_cfdata->cf_driver == &zstty_cd)) { 254 struct kbd_ms_tty_attach_args kma; 255 struct zstty_softc { 256 /* The following are the only fields we need here */ 257 struct device zst_dev; 258 struct tty *zst_tty; 259 struct zs_chanstate *zst_cs; 260 } *zst = (struct zstty_softc *)child; 261 struct tty *tp; 262 263 kma.kmta_tp = tp = zst->zst_tty; 264 if (tp != NULL) { 265 kma.kmta_dev = tp->t_dev; 266 kma.kmta_consdev = zsc_args.consdev; 267 268 /* Attach 'em if we got 'em. */ 269 switch(zs_peripheral_type(zsc->zsc_promunit, 270 zsc->zsc_node, 271 channel)) { 272 case ZS_PERIPHERAL_SUNKBD: 273 #if (NKBD > 0) 274 kma.kmta_name = "keyboard"; 275 config_found(child, (void *)&kma, NULL); 276 #endif 277 break; 278 case ZS_PERIPHERAL_SUNMS: 279 #if (NMS > 0) 280 kma.kmta_name = "mouse"; 281 config_found(child, (void *)&kma, NULL); 282 #endif 283 break; 284 default: 285 break; 286 } 287 } 288 } 289 #endif 290 } 291 292 /* 293 * Now safe to install interrupt handlers. Note the arguments 294 * to the interrupt handlers aren't used. Note, we only do this 295 * once since both SCCs interrupt at the same level and vector. 296 */ 297 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc); 298 if (!(zsc->zsc_softintr = softintr_establish(softpri, zssoft, zsc))) 299 panic("zsattach: could not establish soft interrupt\n"); 300 301 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 302 zsc->zsc_dev.dv_xname, "intr"); 303 304 305 /* 306 * Set the master interrupt enable and interrupt vector. 307 * (common to both channels, do it on A) 308 */ 309 cs = zsc->zsc_cs[0]; 310 s = splhigh(); 311 /* interrupt vector */ 312 zs_write_reg(cs, 2, zs_init_reg[2]); 313 /* master interrupt control (enable) */ 314 zs_write_reg(cs, 9, zs_init_reg[9]); 315 splx(s); 316 317 } 318 319 static int 320 zs_print(aux, name) 321 void *aux; 322 const char *name; 323 { 324 struct zsc_attach_args *args = aux; 325 326 if (name != NULL) 327 printf("%s: ", name); 328 329 if (args->channel != -1) 330 printf(" channel %d", args->channel); 331 332 return (UNCONF); 333 } 334 335 static int 336 zshard(arg) 337 void *arg; 338 { 339 struct zsc_softc *zsc = (struct zsc_softc *)arg; 340 int rr3, rval; 341 342 rval = 0; 343 while ((rr3 = zsc_intr_hard(zsc))) { 344 /* Count up the interrupts. */ 345 rval |= rr3; 346 zsc->zsc_intrcnt.ev_count++; 347 } 348 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 349 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 350 zsc->zsc_softintr) { 351 softintr_schedule(zsc->zsc_softintr); 352 } 353 return (rval); 354 } 355 356 int 357 zscheckintr(arg) 358 void *arg; 359 { 360 struct zsc_softc *zsc; 361 int unit, rval; 362 363 rval = 0; 364 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 365 366 zsc = zs_cd.cd_devs[unit]; 367 if (zsc == NULL) 368 continue; 369 rval = (zshard((void *)zsc) || rval); 370 } 371 return (rval); 372 } 373 374 375 /* 376 * We need this only for TTY_DEBUG purposes. 377 */ 378 static void 379 zssoft(arg) 380 void *arg; 381 { 382 struct zsc_softc *zsc = (struct zsc_softc *)arg; 383 int s; 384 385 /* Make sure we call the tty layer at spltty. */ 386 s = spltty(); 387 (void)zsc_intr_soft(zsc); 388 #ifdef TTY_DEBUG 389 { 390 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 391 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 392 if (zst0->zst_overflows || zst1->zst_overflows ) { 393 struct trapframe *frame = (struct trapframe *)arg; 394 395 printf("zs silo overflow from %p\n", 396 (long)frame->tf_pc); 397 } 398 } 399 #endif 400 splx(s); 401 } 402 403 404 /* 405 * Compute the current baud rate given a ZS channel. 406 */ 407 static int 408 zs_get_speed(cs) 409 struct zs_chanstate *cs; 410 { 411 int tconst; 412 413 tconst = zs_read_reg(cs, 12); 414 tconst |= zs_read_reg(cs, 13) << 8; 415 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 416 } 417 418 /* 419 * MD functions for setting the baud rate and control modes. 420 */ 421 int 422 zs_set_speed(cs, bps) 423 struct zs_chanstate *cs; 424 int bps; /* bits per second */ 425 { 426 int tconst, real_bps; 427 428 if (bps == 0) 429 return (0); 430 431 #ifdef DIAGNOSTIC 432 if (cs->cs_brg_clk == 0) 433 panic("zs_set_speed"); 434 #endif 435 436 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 437 if (tconst < 0) 438 return (EINVAL); 439 440 /* Convert back to make sure we can do it. */ 441 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 442 443 /* XXX - Allow some tolerance here? */ 444 if (real_bps != bps) 445 return (EINVAL); 446 447 cs->cs_preg[12] = tconst; 448 cs->cs_preg[13] = tconst >> 8; 449 450 /* Caller will stuff the pending registers. */ 451 return (0); 452 } 453 454 int 455 zs_set_modes(cs, cflag) 456 struct zs_chanstate *cs; 457 int cflag; /* bits per second */ 458 { 459 int s; 460 461 /* 462 * Output hardware flow control on the chip is horrendous: 463 * if carrier detect drops, the receiver is disabled, and if 464 * CTS drops, the transmitter is stoped IN MID CHARACTER! 465 * Therefore, NEVER set the HFC bit, and instead use the 466 * status interrupt to detect CTS changes. 467 */ 468 s = splzs(); 469 cs->cs_rr0_pps = 0; 470 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 471 cs->cs_rr0_dcd = 0; 472 if ((cflag & MDMBUF) == 0) 473 cs->cs_rr0_pps = ZSRR0_DCD; 474 } else 475 cs->cs_rr0_dcd = ZSRR0_DCD; 476 if ((cflag & CRTSCTS) != 0) { 477 cs->cs_wr5_dtr = ZSWR5_DTR; 478 cs->cs_wr5_rts = ZSWR5_RTS; 479 cs->cs_rr0_cts = ZSRR0_CTS; 480 } else if ((cflag & CDTRCTS) != 0) { 481 cs->cs_wr5_dtr = 0; 482 cs->cs_wr5_rts = ZSWR5_DTR; 483 cs->cs_rr0_cts = ZSRR0_CTS; 484 } else if ((cflag & MDMBUF) != 0) { 485 cs->cs_wr5_dtr = 0; 486 cs->cs_wr5_rts = ZSWR5_DTR; 487 cs->cs_rr0_cts = ZSRR0_DCD; 488 } else { 489 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 490 cs->cs_wr5_rts = 0; 491 cs->cs_rr0_cts = 0; 492 } 493 splx(s); 494 495 /* Caller will stuff the pending registers. */ 496 return (0); 497 } 498 499 500 /* 501 * Read or write the chip with suitable delays. 502 */ 503 504 u_char 505 zs_read_reg(cs, reg) 506 struct zs_chanstate *cs; 507 u_char reg; 508 { 509 u_char val; 510 511 *cs->cs_reg_csr = reg; 512 ZS_DELAY(); 513 val = *cs->cs_reg_csr; 514 ZS_DELAY(); 515 return (val); 516 } 517 518 void 519 zs_write_reg(cs, reg, val) 520 struct zs_chanstate *cs; 521 u_char reg, val; 522 { 523 *cs->cs_reg_csr = reg; 524 ZS_DELAY(); 525 *cs->cs_reg_csr = val; 526 ZS_DELAY(); 527 } 528 529 u_char 530 zs_read_csr(cs) 531 struct zs_chanstate *cs; 532 { 533 u_char val; 534 535 val = *cs->cs_reg_csr; 536 ZS_DELAY(); 537 return (val); 538 } 539 540 void zs_write_csr(cs, val) 541 struct zs_chanstate *cs; 542 u_char val; 543 { 544 *cs->cs_reg_csr = val; 545 ZS_DELAY(); 546 } 547 548 u_char zs_read_data(cs) 549 struct zs_chanstate *cs; 550 { 551 u_char val; 552 553 val = *cs->cs_reg_data; 554 ZS_DELAY(); 555 return (val); 556 } 557 558 void zs_write_data(cs, val) 559 struct zs_chanstate *cs; 560 u_char val; 561 { 562 *cs->cs_reg_data = val; 563 ZS_DELAY(); 564 } 565 566 /**************************************************************** 567 * Console support functions (Sun specific!) 568 * Note: this code is allowed to know about the layout of 569 * the chip registers, and uses that to keep things simple. 570 * XXX - I think I like the mvme167 code better. -gwr 571 ****************************************************************/ 572 573 extern void Debugger __P((void)); 574 575 /* 576 * Handle user request to enter kernel debugger. 577 */ 578 void 579 zs_abort(cs) 580 struct zs_chanstate *cs; 581 { 582 volatile struct zschan *zc = zs_conschan_get; 583 int rr0; 584 585 /* Wait for end of break to avoid PROM abort. */ 586 /* XXX - Limit the wait? */ 587 do { 588 rr0 = zc->zc_csr; 589 ZS_DELAY(); 590 } while (rr0 & ZSRR0_BREAK); 591 592 #if defined(KGDB) 593 zskgdb(cs); 594 #elif defined(DDB) 595 { 596 extern int db_active; 597 598 if (!db_active) 599 Debugger(); 600 else 601 /* Debugger is probably hozed */ 602 callrom(); 603 } 604 #else 605 printf("stopping on keyboard abort\n"); 606 callrom(); 607 #endif 608 } 609 610 611 /* 612 * Polled input char. 613 */ 614 int 615 zs_getc(arg) 616 void *arg; 617 { 618 volatile struct zschan *zc = arg; 619 int s, c, rr0; 620 621 s = splhigh(); 622 /* Wait for a character to arrive. */ 623 do { 624 rr0 = zc->zc_csr; 625 ZS_DELAY(); 626 } while ((rr0 & ZSRR0_RX_READY) == 0); 627 628 c = zc->zc_data; 629 ZS_DELAY(); 630 splx(s); 631 632 /* 633 * This is used by the kd driver to read scan codes, 634 * so don't translate '\r' ==> '\n' here... 635 */ 636 return (c); 637 } 638 639 /* 640 * Polled output char. 641 */ 642 void 643 zs_putc(arg, c) 644 void *arg; 645 int c; 646 { 647 volatile struct zschan *zc = arg; 648 int s, rr0; 649 650 s = splhigh(); 651 652 /* Wait for transmitter to become ready. */ 653 do { 654 rr0 = zc->zc_csr; 655 ZS_DELAY(); 656 } while ((rr0 & ZSRR0_TX_READY) == 0); 657 658 /* 659 * Send the next character. 660 * Now you'd think that this could be followed by a ZS_DELAY() 661 * just like all the other chip accesses, but it turns out that 662 * the `transmit-ready' interrupt isn't de-asserted until 663 * some period of time after the register write completes 664 * (more than a couple instructions). So to avoid stray 665 * interrupts we put in the 2us delay regardless of cpu model. 666 */ 667 zc->zc_data = c; 668 delay(2); 669 670 splx(s); 671 } 672 673 /*****************************************************************/ 674 675 676 677 678 /* 679 * Polled console input putchar. 680 */ 681 static int 682 zscngetc(dev) 683 dev_t dev; 684 { 685 return (zs_getc(zs_conschan_get)); 686 } 687 688 /* 689 * Polled console output putchar. 690 */ 691 static void 692 zscnputc(dev, c) 693 dev_t dev; 694 int c; 695 { 696 zs_putc(zs_conschan_put, c); 697 } 698 699 int swallow_zsintrs; 700 701 static void 702 zscnpollc(dev, on) 703 dev_t dev; 704 int on; 705 { 706 /* 707 * Need to tell zs driver to acknowledge all interrupts or we get 708 * annoying spurious interrupt messages. This is because mucking 709 * with spl() levels during polling does not prevent interrupts from 710 * being generated. 711 */ 712 713 if (on) swallow_zsintrs++; 714 else swallow_zsintrs--; 715 } 716 717
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