zs.c revision 1.5
1 /* $NetBSD: zs.c,v 1.5 2002/12/13 20:44:44 fredette Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kgdb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/kernel.h> 57 #include <sys/proc.h> 58 #include <sys/tty.h> 59 #include <sys/time.h> 60 #include <sys/syslog.h> 61 62 #include <machine/autoconf.h> 63 #include <machine/promlib.h> 64 #include <machine/cpu.h> 65 #include <machine/eeprom.h> 66 #include <machine/psl.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/cons.h> 70 #include <dev/ic/z8530reg.h> 71 #include <dev/sun/kbd_ms_ttyvar.h> 72 #include <ddb/db_output.h> 73 74 #include <sun2/dev/cons.h> 75 76 #include "kbd.h" /* NKBD */ 77 #include "ms.h" /* NMS */ 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 86 /* ZS channel used as the console device (if any) */ 87 void *zs_conschan_get, *zs_conschan_put; 88 89 static u_char zs_init_reg[16] = { 90 0, /* 0: CMD (reset, etc.) */ 91 0, /* 1: No interrupts yet. */ 92 #ifdef ZS_INIT_IVECT 93 ZS_INIT_IVECT, /* 2: IVECT */ 94 #else 95 0, /* 2: IVECT */ 96 #endif 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 #ifdef ZS_INIT_IVECT 104 ZSWR9_MASTER_IE, 105 #else 106 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 107 #endif 108 0, /*10: Misc. TX/RX control bits */ 109 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 110 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 111 0, /*13: BAUDHI (default=9600) */ 112 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 113 ZSWR15_BREAK_IE, 114 }; 115 116 /* Console ops */ 117 static int zscngetc __P((dev_t)); 118 static void zscnputc __P((dev_t, int)); 119 static void zscnpollc __P((dev_t, int)); 120 121 struct consdev zs_consdev = { 122 NULL, 123 NULL, 124 zscngetc, 125 zscnputc, 126 zscnpollc, 127 NULL, 128 }; 129 130 131 /**************************************************************** 132 * Autoconfig 133 ****************************************************************/ 134 135 static int zs_print __P((void *, const char *name)); 136 137 extern struct cfdriver zs_cd; 138 139 /* Interrupt handlers. */ 140 int zscheckintr __P((void *)); 141 static int zshard __P((void *)); 142 static void zssoft __P((void *)); 143 144 static int zs_get_speed __P((struct zs_chanstate *)); 145 146 /* 147 * Attach a found zs. 148 * 149 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 150 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 151 */ 152 void 153 zs_attach(zsc, zsd, pri) 154 struct zsc_softc *zsc; 155 struct zsdevice *zsd; 156 int pri; 157 { 158 struct zsc_attach_args zsc_args; 159 struct zs_chanstate *cs; 160 int s, channel, softpri = IPL_SOFTSERIAL; 161 162 if (zsd == NULL) { 163 printf("configuration incomplete\n"); 164 return; 165 } 166 167 printf(" softpri %d\n", softpri); 168 169 /* 170 * Initialize software state for each channel. 171 */ 172 for (channel = 0; channel < 2; channel++) { 173 struct zschan *zc; 174 struct device *child; 175 176 zsc_args.channel = channel; 177 cs = &zsc->zsc_cs_store[channel]; 178 zsc->zsc_cs[channel] = cs; 179 180 cs->cs_channel = channel; 181 cs->cs_private = NULL; 182 cs->cs_ops = &zsops_null; 183 cs->cs_brg_clk = PCLK / 16; 184 185 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 186 187 zsc_args.consdev = NULL; 188 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 189 zsc->zsc_node, 190 channel); 191 192 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 193 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 194 zsc_args.consdev = &zs_consdev; 195 } 196 197 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 198 zs_conschan_get = zc; 199 } 200 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 201 zs_conschan_put = zc; 202 } 203 204 /* Children need to set cn_dev, etc */ 205 cs->cs_reg_csr = &zc->zc_csr; 206 cs->cs_reg_data = &zc->zc_data; 207 208 memcpy(cs->cs_creg, zs_init_reg, 16); 209 memcpy(cs->cs_preg, zs_init_reg, 16); 210 211 /* XXX: Consult PROM properties for this?! */ 212 cs->cs_defspeed = zs_get_speed(cs); 213 cs->cs_defcflag = zs_def_cflag; 214 215 /* Make these correspond to cs_defcflag (-crtscts) */ 216 cs->cs_rr0_dcd = ZSRR0_DCD; 217 cs->cs_rr0_cts = 0; 218 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 219 cs->cs_wr5_rts = 0; 220 221 /* 222 * Clear the master interrupt enable. 223 * The INTENA is common to both channels, 224 * so just do it on the A channel. 225 */ 226 if (channel == 0) { 227 zs_write_reg(cs, 9, 0); 228 } 229 230 /* 231 * Look for a child driver for this channel. 232 * The child attach will setup the hardware. 233 */ 234 if (!(child = 235 config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print))) { 236 /* No sub-driver. Just reset it. */ 237 u_char reset = (channel == 0) ? 238 ZSWR9_A_RESET : ZSWR9_B_RESET; 239 s = splzs(); 240 zs_write_reg(cs, 9, reset); 241 splx(s); 242 } 243 #if (NKBD > 0) || (NMS > 0) 244 /* 245 * If this was a zstty it has a keyboard 246 * property on it we need to attach the 247 * sunkbd and sunms line disciplines. 248 */ 249 if (child 250 && (!strcmp(child->dv_cfdata->cf_name, 251 "zstty"))) { 252 struct kbd_ms_tty_attach_args kma; 253 struct zstty_softc { 254 /* The following are the only fields we need here */ 255 struct device zst_dev; 256 struct tty *zst_tty; 257 struct zs_chanstate *zst_cs; 258 } *zst = (struct zstty_softc *)child; 259 struct tty *tp; 260 261 kma.kmta_tp = tp = zst->zst_tty; 262 if (tp != NULL) { 263 kma.kmta_dev = tp->t_dev; 264 kma.kmta_consdev = zsc_args.consdev; 265 266 /* Attach 'em if we got 'em. */ 267 switch(zs_peripheral_type(zsc->zsc_promunit, 268 zsc->zsc_node, 269 channel)) { 270 case ZS_PERIPHERAL_SUNKBD: 271 #if (NKBD > 0) 272 kma.kmta_name = "keyboard"; 273 config_found(child, (void *)&kma, NULL); 274 #endif 275 break; 276 case ZS_PERIPHERAL_SUNMS: 277 #if (NMS > 0) 278 kma.kmta_name = "mouse"; 279 config_found(child, (void *)&kma, NULL); 280 #endif 281 break; 282 default: 283 break; 284 } 285 } 286 } 287 #endif 288 } 289 290 /* 291 * Now safe to install interrupt handlers. Note the arguments 292 * to the interrupt handlers aren't used. Note, we only do this 293 * once since both SCCs interrupt at the same level and vector. 294 */ 295 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc); 296 if (!(zsc->zsc_softintr = softintr_establish(softpri, zssoft, zsc))) 297 panic("zsattach: could not establish soft interrupt"); 298 299 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 300 zsc->zsc_dev.dv_xname, "intr"); 301 302 303 /* 304 * Set the master interrupt enable and interrupt vector. 305 * (common to both channels, do it on A) 306 */ 307 cs = zsc->zsc_cs[0]; 308 s = splhigh(); 309 /* interrupt vector */ 310 zs_write_reg(cs, 2, zs_init_reg[2]); 311 /* master interrupt control (enable) */ 312 zs_write_reg(cs, 9, zs_init_reg[9]); 313 splx(s); 314 315 } 316 317 static int 318 zs_print(aux, name) 319 void *aux; 320 const char *name; 321 { 322 struct zsc_attach_args *args = aux; 323 324 if (name != NULL) 325 printf("%s: ", name); 326 327 if (args->channel != -1) 328 printf(" channel %d", args->channel); 329 330 return (UNCONF); 331 } 332 333 static int 334 zshard(arg) 335 void *arg; 336 { 337 struct zsc_softc *zsc = (struct zsc_softc *)arg; 338 int rr3, rval; 339 340 rval = 0; 341 while ((rr3 = zsc_intr_hard(zsc))) { 342 /* Count up the interrupts. */ 343 rval |= rr3; 344 zsc->zsc_intrcnt.ev_count++; 345 } 346 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 347 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 348 zsc->zsc_softintr) { 349 softintr_schedule(zsc->zsc_softintr); 350 } 351 return (rval); 352 } 353 354 int 355 zscheckintr(arg) 356 void *arg; 357 { 358 struct zsc_softc *zsc; 359 int unit, rval; 360 361 rval = 0; 362 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 363 364 zsc = zs_cd.cd_devs[unit]; 365 if (zsc == NULL) 366 continue; 367 rval = (zshard((void *)zsc) || rval); 368 } 369 return (rval); 370 } 371 372 373 /* 374 * We need this only for TTY_DEBUG purposes. 375 */ 376 static void 377 zssoft(arg) 378 void *arg; 379 { 380 struct zsc_softc *zsc = (struct zsc_softc *)arg; 381 int s; 382 383 /* Make sure we call the tty layer at spltty. */ 384 s = spltty(); 385 (void)zsc_intr_soft(zsc); 386 #ifdef TTY_DEBUG 387 { 388 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 389 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 390 if (zst0->zst_overflows || zst1->zst_overflows ) { 391 struct trapframe *frame = (struct trapframe *)arg; 392 393 printf("zs silo overflow from %p\n", 394 (long)frame->tf_pc); 395 } 396 } 397 #endif 398 splx(s); 399 } 400 401 402 /* 403 * Compute the current baud rate given a ZS channel. 404 */ 405 static int 406 zs_get_speed(cs) 407 struct zs_chanstate *cs; 408 { 409 int tconst; 410 411 tconst = zs_read_reg(cs, 12); 412 tconst |= zs_read_reg(cs, 13) << 8; 413 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 414 } 415 416 /* 417 * MD functions for setting the baud rate and control modes. 418 */ 419 int 420 zs_set_speed(cs, bps) 421 struct zs_chanstate *cs; 422 int bps; /* bits per second */ 423 { 424 int tconst, real_bps; 425 426 if (bps == 0) 427 return (0); 428 429 #ifdef DIAGNOSTIC 430 if (cs->cs_brg_clk == 0) 431 panic("zs_set_speed"); 432 #endif 433 434 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 435 if (tconst < 0) 436 return (EINVAL); 437 438 /* Convert back to make sure we can do it. */ 439 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 440 441 /* XXX - Allow some tolerance here? */ 442 if (real_bps != bps) 443 return (EINVAL); 444 445 cs->cs_preg[12] = tconst; 446 cs->cs_preg[13] = tconst >> 8; 447 448 /* Caller will stuff the pending registers. */ 449 return (0); 450 } 451 452 int 453 zs_set_modes(cs, cflag) 454 struct zs_chanstate *cs; 455 int cflag; /* bits per second */ 456 { 457 int s; 458 459 /* 460 * Output hardware flow control on the chip is horrendous: 461 * if carrier detect drops, the receiver is disabled, and if 462 * CTS drops, the transmitter is stoped IN MID CHARACTER! 463 * Therefore, NEVER set the HFC bit, and instead use the 464 * status interrupt to detect CTS changes. 465 */ 466 s = splzs(); 467 cs->cs_rr0_pps = 0; 468 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 469 cs->cs_rr0_dcd = 0; 470 if ((cflag & MDMBUF) == 0) 471 cs->cs_rr0_pps = ZSRR0_DCD; 472 } else 473 cs->cs_rr0_dcd = ZSRR0_DCD; 474 if ((cflag & CRTSCTS) != 0) { 475 cs->cs_wr5_dtr = ZSWR5_DTR; 476 cs->cs_wr5_rts = ZSWR5_RTS; 477 cs->cs_rr0_cts = ZSRR0_CTS; 478 } else if ((cflag & CDTRCTS) != 0) { 479 cs->cs_wr5_dtr = 0; 480 cs->cs_wr5_rts = ZSWR5_DTR; 481 cs->cs_rr0_cts = ZSRR0_CTS; 482 } else if ((cflag & MDMBUF) != 0) { 483 cs->cs_wr5_dtr = 0; 484 cs->cs_wr5_rts = ZSWR5_DTR; 485 cs->cs_rr0_cts = ZSRR0_DCD; 486 } else { 487 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 488 cs->cs_wr5_rts = 0; 489 cs->cs_rr0_cts = 0; 490 } 491 splx(s); 492 493 /* Caller will stuff the pending registers. */ 494 return (0); 495 } 496 497 498 /* 499 * Read or write the chip with suitable delays. 500 */ 501 502 u_char 503 zs_read_reg(cs, reg) 504 struct zs_chanstate *cs; 505 u_char reg; 506 { 507 u_char val; 508 509 *cs->cs_reg_csr = reg; 510 ZS_DELAY(); 511 val = *cs->cs_reg_csr; 512 ZS_DELAY(); 513 return (val); 514 } 515 516 void 517 zs_write_reg(cs, reg, val) 518 struct zs_chanstate *cs; 519 u_char reg, val; 520 { 521 *cs->cs_reg_csr = reg; 522 ZS_DELAY(); 523 *cs->cs_reg_csr = val; 524 ZS_DELAY(); 525 } 526 527 u_char 528 zs_read_csr(cs) 529 struct zs_chanstate *cs; 530 { 531 u_char val; 532 533 val = *cs->cs_reg_csr; 534 ZS_DELAY(); 535 return (val); 536 } 537 538 void zs_write_csr(cs, val) 539 struct zs_chanstate *cs; 540 u_char val; 541 { 542 *cs->cs_reg_csr = val; 543 ZS_DELAY(); 544 } 545 546 u_char zs_read_data(cs) 547 struct zs_chanstate *cs; 548 { 549 u_char val; 550 551 val = *cs->cs_reg_data; 552 ZS_DELAY(); 553 return (val); 554 } 555 556 void zs_write_data(cs, val) 557 struct zs_chanstate *cs; 558 u_char val; 559 { 560 *cs->cs_reg_data = val; 561 ZS_DELAY(); 562 } 563 564 /**************************************************************** 565 * Console support functions (Sun specific!) 566 * Note: this code is allowed to know about the layout of 567 * the chip registers, and uses that to keep things simple. 568 * XXX - I think I like the mvme167 code better. -gwr 569 ****************************************************************/ 570 571 extern void Debugger __P((void)); 572 573 /* 574 * Handle user request to enter kernel debugger. 575 */ 576 void 577 zs_abort(cs) 578 struct zs_chanstate *cs; 579 { 580 volatile struct zschan *zc = zs_conschan_get; 581 int rr0; 582 583 /* Wait for end of break to avoid PROM abort. */ 584 /* XXX - Limit the wait? */ 585 do { 586 rr0 = zc->zc_csr; 587 ZS_DELAY(); 588 } while (rr0 & ZSRR0_BREAK); 589 590 #if defined(KGDB) 591 zskgdb(cs); 592 #elif defined(DDB) 593 { 594 extern int db_active; 595 596 if (!db_active) 597 Debugger(); 598 else 599 /* Debugger is probably hozed */ 600 callrom(); 601 } 602 #else 603 printf("stopping on keyboard abort\n"); 604 callrom(); 605 #endif 606 } 607 608 609 /* 610 * Polled input char. 611 */ 612 int 613 zs_getc(arg) 614 void *arg; 615 { 616 volatile struct zschan *zc = arg; 617 int s, c, rr0; 618 619 s = splhigh(); 620 /* Wait for a character to arrive. */ 621 do { 622 rr0 = zc->zc_csr; 623 ZS_DELAY(); 624 } while ((rr0 & ZSRR0_RX_READY) == 0); 625 626 c = zc->zc_data; 627 ZS_DELAY(); 628 splx(s); 629 630 /* 631 * This is used by the kd driver to read scan codes, 632 * so don't translate '\r' ==> '\n' here... 633 */ 634 return (c); 635 } 636 637 /* 638 * Polled output char. 639 */ 640 void 641 zs_putc(arg, c) 642 void *arg; 643 int c; 644 { 645 volatile struct zschan *zc = arg; 646 int s, rr0; 647 648 s = splhigh(); 649 650 /* Wait for transmitter to become ready. */ 651 do { 652 rr0 = zc->zc_csr; 653 ZS_DELAY(); 654 } while ((rr0 & ZSRR0_TX_READY) == 0); 655 656 /* 657 * Send the next character. 658 * Now you'd think that this could be followed by a ZS_DELAY() 659 * just like all the other chip accesses, but it turns out that 660 * the `transmit-ready' interrupt isn't de-asserted until 661 * some period of time after the register write completes 662 * (more than a couple instructions). So to avoid stray 663 * interrupts we put in the 2us delay regardless of cpu model. 664 */ 665 zc->zc_data = c; 666 delay(2); 667 668 splx(s); 669 } 670 671 /*****************************************************************/ 672 673 674 675 676 /* 677 * Polled console input putchar. 678 */ 679 static int 680 zscngetc(dev) 681 dev_t dev; 682 { 683 return (zs_getc(zs_conschan_get)); 684 } 685 686 /* 687 * Polled console output putchar. 688 */ 689 static void 690 zscnputc(dev, c) 691 dev_t dev; 692 int c; 693 { 694 zs_putc(zs_conschan_put, c); 695 } 696 697 int swallow_zsintrs; 698 699 static void 700 zscnpollc(dev, on) 701 dev_t dev; 702 int on; 703 { 704 /* 705 * Need to tell zs driver to acknowledge all interrupts or we get 706 * annoying spurious interrupt messages. This is because mucking 707 * with spl() levels during polling does not prevent interrupts from 708 * being generated. 709 */ 710 711 if (on) swallow_zsintrs++; 712 else swallow_zsintrs--; 713 } 714 715
Indexes created Thu Sep 25 06:09:39 GMT 2025