zs.c revision 1.7
1 /* $NetBSD: zs.c,v 1.7 2003/01/28 12:35:37 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kgdb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/kernel.h> 57 #include <sys/proc.h> 58 #include <sys/tty.h> 59 #include <sys/time.h> 60 #include <sys/syslog.h> 61 62 #include <machine/autoconf.h> 63 #include <machine/promlib.h> 64 #include <machine/cpu.h> 65 #include <machine/eeprom.h> 66 #include <machine/psl.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/cons.h> 70 #include <dev/ic/z8530reg.h> 71 #include <dev/sun/kbd_ms_ttyvar.h> 72 #include <ddb/db_output.h> 73 74 #include <sun2/dev/cons.h> 75 76 #include "kbd.h" /* NKBD */ 77 #include "ms.h" /* NMS */ 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 86 /* ZS channel used as the console device (if any) */ 87 void *zs_conschan_get, *zs_conschan_put; 88 89 static u_char zs_init_reg[16] = { 90 0, /* 0: CMD (reset, etc.) */ 91 0, /* 1: No interrupts yet. */ 92 #ifdef ZS_INIT_IVECT 93 ZS_INIT_IVECT, /* 2: IVECT */ 94 #else 95 0, /* 2: IVECT */ 96 #endif 97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 100 0, /* 6: TXSYNC/SYNCLO */ 101 0, /* 7: RXSYNC/SYNCHI */ 102 0, /* 8: alias for data port */ 103 #ifdef ZS_INIT_IVECT 104 ZSWR9_MASTER_IE, 105 #else 106 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 107 #endif 108 0, /*10: Misc. TX/RX control bits */ 109 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 110 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 111 0, /*13: BAUDHI (default=9600) */ 112 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 113 ZSWR15_BREAK_IE, 114 }; 115 116 /* Console ops */ 117 static int zscngetc __P((dev_t)); 118 static void zscnputc __P((dev_t, int)); 119 static void zscnpollc __P((dev_t, int)); 120 121 struct consdev zs_consdev = { 122 NULL, 123 NULL, 124 zscngetc, 125 zscnputc, 126 zscnpollc, 127 NULL, 128 }; 129 130 131 /**************************************************************** 132 * Autoconfig 133 ****************************************************************/ 134 135 static int zs_print __P((void *, const char *name)); 136 137 extern struct cfdriver zs_cd; 138 139 /* Interrupt handlers. */ 140 int zscheckintr __P((void *)); 141 static int zshard __P((void *)); 142 static void zssoft __P((void *)); 143 144 static int zs_get_speed __P((struct zs_chanstate *)); 145 146 /* 147 * Attach a found zs. 148 * 149 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 150 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 151 */ 152 void 153 zs_attach(zsc, zsd, pri) 154 struct zsc_softc *zsc; 155 struct zsdevice *zsd; 156 int pri; 157 { 158 struct zsc_attach_args zsc_args; 159 struct zs_chanstate *cs; 160 int s, channel, softpri = IPL_SOFTSERIAL; 161 162 if (zsd == NULL) { 163 printf("configuration incomplete\n"); 164 return; 165 } 166 167 printf(" softpri %d\n", softpri); 168 169 /* 170 * Initialize software state for each channel. 171 */ 172 for (channel = 0; channel < 2; channel++) { 173 struct zschan *zc; 174 struct device *child; 175 176 zsc_args.channel = channel; 177 cs = &zsc->zsc_cs_store[channel]; 178 zsc->zsc_cs[channel] = cs; 179 180 simple_lock_init(&cs->cs_lock); 181 cs->cs_channel = channel; 182 cs->cs_private = NULL; 183 cs->cs_ops = &zsops_null; 184 cs->cs_brg_clk = PCLK / 16; 185 186 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 187 188 zsc_args.consdev = NULL; 189 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 190 zsc->zsc_node, 191 channel); 192 193 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 194 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 195 zsc_args.consdev = &zs_consdev; 196 } 197 198 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 199 zs_conschan_get = zc; 200 } 201 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 202 zs_conschan_put = zc; 203 } 204 205 /* Children need to set cn_dev, etc */ 206 cs->cs_reg_csr = &zc->zc_csr; 207 cs->cs_reg_data = &zc->zc_data; 208 209 memcpy(cs->cs_creg, zs_init_reg, 16); 210 memcpy(cs->cs_preg, zs_init_reg, 16); 211 212 /* XXX: Consult PROM properties for this?! */ 213 cs->cs_defspeed = zs_get_speed(cs); 214 cs->cs_defcflag = zs_def_cflag; 215 216 /* Make these correspond to cs_defcflag (-crtscts) */ 217 cs->cs_rr0_dcd = ZSRR0_DCD; 218 cs->cs_rr0_cts = 0; 219 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 220 cs->cs_wr5_rts = 0; 221 222 /* 223 * Clear the master interrupt enable. 224 * The INTENA is common to both channels, 225 * so just do it on the A channel. 226 */ 227 if (channel == 0) { 228 zs_write_reg(cs, 9, 0); 229 } 230 231 /* 232 * Look for a child driver for this channel. 233 * The child attach will setup the hardware. 234 */ 235 if (!(child = 236 config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print))) { 237 /* No sub-driver. Just reset it. */ 238 u_char reset = (channel == 0) ? 239 ZSWR9_A_RESET : ZSWR9_B_RESET; 240 s = splzs(); 241 zs_write_reg(cs, 9, reset); 242 splx(s); 243 } 244 #if (NKBD > 0) || (NMS > 0) 245 /* 246 * If this was a zstty it has a keyboard 247 * property on it we need to attach the 248 * sunkbd and sunms line disciplines. 249 */ 250 if (child 251 && (!strcmp(child->dv_cfdata->cf_name, 252 "zstty"))) { 253 struct kbd_ms_tty_attach_args kma; 254 struct zstty_softc { 255 /* The following are the only fields we need here */ 256 struct device zst_dev; 257 struct tty *zst_tty; 258 struct zs_chanstate *zst_cs; 259 } *zst = (struct zstty_softc *)child; 260 struct tty *tp; 261 262 kma.kmta_tp = tp = zst->zst_tty; 263 if (tp != NULL) { 264 kma.kmta_dev = tp->t_dev; 265 kma.kmta_consdev = zsc_args.consdev; 266 267 /* Attach 'em if we got 'em. */ 268 switch(zs_peripheral_type(zsc->zsc_promunit, 269 zsc->zsc_node, 270 channel)) { 271 case ZS_PERIPHERAL_SUNKBD: 272 #if (NKBD > 0) 273 kma.kmta_name = "keyboard"; 274 config_found(child, (void *)&kma, NULL); 275 #endif 276 break; 277 case ZS_PERIPHERAL_SUNMS: 278 #if (NMS > 0) 279 kma.kmta_name = "mouse"; 280 config_found(child, (void *)&kma, NULL); 281 #endif 282 break; 283 default: 284 break; 285 } 286 } 287 } 288 #endif 289 } 290 291 /* 292 * Now safe to install interrupt handlers. Note the arguments 293 * to the interrupt handlers aren't used. Note, we only do this 294 * once since both SCCs interrupt at the same level and vector. 295 */ 296 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc); 297 if (!(zsc->zsc_softintr = softintr_establish(softpri, zssoft, zsc))) 298 panic("zsattach: could not establish soft interrupt"); 299 300 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 301 zsc->zsc_dev.dv_xname, "intr"); 302 303 304 /* 305 * Set the master interrupt enable and interrupt vector. 306 * (common to both channels, do it on A) 307 */ 308 cs = zsc->zsc_cs[0]; 309 s = splhigh(); 310 /* interrupt vector */ 311 zs_write_reg(cs, 2, zs_init_reg[2]); 312 /* master interrupt control (enable) */ 313 zs_write_reg(cs, 9, zs_init_reg[9]); 314 splx(s); 315 316 } 317 318 static int 319 zs_print(aux, name) 320 void *aux; 321 const char *name; 322 { 323 struct zsc_attach_args *args = aux; 324 325 if (name != NULL) 326 aprint_normal("%s: ", name); 327 328 if (args->channel != -1) 329 aprint_normal(" channel %d", args->channel); 330 331 return (UNCONF); 332 } 333 334 static int 335 zshard(arg) 336 void *arg; 337 { 338 struct zsc_softc *zsc = (struct zsc_softc *)arg; 339 int rr3, rval; 340 341 rval = 0; 342 while ((rr3 = zsc_intr_hard(zsc))) { 343 /* Count up the interrupts. */ 344 rval |= rr3; 345 zsc->zsc_intrcnt.ev_count++; 346 } 347 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 348 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 349 zsc->zsc_softintr) { 350 softintr_schedule(zsc->zsc_softintr); 351 } 352 return (rval); 353 } 354 355 int 356 zscheckintr(arg) 357 void *arg; 358 { 359 struct zsc_softc *zsc; 360 int unit, rval; 361 362 rval = 0; 363 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 364 365 zsc = zs_cd.cd_devs[unit]; 366 if (zsc == NULL) 367 continue; 368 rval = (zshard((void *)zsc) || rval); 369 } 370 return (rval); 371 } 372 373 374 /* 375 * We need this only for TTY_DEBUG purposes. 376 */ 377 static void 378 zssoft(arg) 379 void *arg; 380 { 381 struct zsc_softc *zsc = (struct zsc_softc *)arg; 382 int s; 383 384 /* Make sure we call the tty layer at spltty. */ 385 s = spltty(); 386 (void)zsc_intr_soft(zsc); 387 #ifdef TTY_DEBUG 388 { 389 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 390 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 391 if (zst0->zst_overflows || zst1->zst_overflows ) { 392 struct trapframe *frame = (struct trapframe *)arg; 393 394 printf("zs silo overflow from %p\n", 395 (long)frame->tf_pc); 396 } 397 } 398 #endif 399 splx(s); 400 } 401 402 403 /* 404 * Compute the current baud rate given a ZS channel. 405 */ 406 static int 407 zs_get_speed(cs) 408 struct zs_chanstate *cs; 409 { 410 int tconst; 411 412 tconst = zs_read_reg(cs, 12); 413 tconst |= zs_read_reg(cs, 13) << 8; 414 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 415 } 416 417 /* 418 * MD functions for setting the baud rate and control modes. 419 */ 420 int 421 zs_set_speed(cs, bps) 422 struct zs_chanstate *cs; 423 int bps; /* bits per second */ 424 { 425 int tconst, real_bps; 426 427 if (bps == 0) 428 return (0); 429 430 #ifdef DIAGNOSTIC 431 if (cs->cs_brg_clk == 0) 432 panic("zs_set_speed"); 433 #endif 434 435 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 436 if (tconst < 0) 437 return (EINVAL); 438 439 /* Convert back to make sure we can do it. */ 440 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 441 442 /* XXX - Allow some tolerance here? */ 443 if (real_bps != bps) 444 return (EINVAL); 445 446 cs->cs_preg[12] = tconst; 447 cs->cs_preg[13] = tconst >> 8; 448 449 /* Caller will stuff the pending registers. */ 450 return (0); 451 } 452 453 int 454 zs_set_modes(cs, cflag) 455 struct zs_chanstate *cs; 456 int cflag; /* bits per second */ 457 { 458 int s; 459 460 /* 461 * Output hardware flow control on the chip is horrendous: 462 * if carrier detect drops, the receiver is disabled, and if 463 * CTS drops, the transmitter is stoped IN MID CHARACTER! 464 * Therefore, NEVER set the HFC bit, and instead use the 465 * status interrupt to detect CTS changes. 466 */ 467 s = splzs(); 468 cs->cs_rr0_pps = 0; 469 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 470 cs->cs_rr0_dcd = 0; 471 if ((cflag & MDMBUF) == 0) 472 cs->cs_rr0_pps = ZSRR0_DCD; 473 } else 474 cs->cs_rr0_dcd = ZSRR0_DCD; 475 if ((cflag & CRTSCTS) != 0) { 476 cs->cs_wr5_dtr = ZSWR5_DTR; 477 cs->cs_wr5_rts = ZSWR5_RTS; 478 cs->cs_rr0_cts = ZSRR0_CTS; 479 } else if ((cflag & CDTRCTS) != 0) { 480 cs->cs_wr5_dtr = 0; 481 cs->cs_wr5_rts = ZSWR5_DTR; 482 cs->cs_rr0_cts = ZSRR0_CTS; 483 } else if ((cflag & MDMBUF) != 0) { 484 cs->cs_wr5_dtr = 0; 485 cs->cs_wr5_rts = ZSWR5_DTR; 486 cs->cs_rr0_cts = ZSRR0_DCD; 487 } else { 488 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 489 cs->cs_wr5_rts = 0; 490 cs->cs_rr0_cts = 0; 491 } 492 splx(s); 493 494 /* Caller will stuff the pending registers. */ 495 return (0); 496 } 497 498 499 /* 500 * Read or write the chip with suitable delays. 501 */ 502 503 u_char 504 zs_read_reg(cs, reg) 505 struct zs_chanstate *cs; 506 u_char reg; 507 { 508 u_char val; 509 510 *cs->cs_reg_csr = reg; 511 ZS_DELAY(); 512 val = *cs->cs_reg_csr; 513 ZS_DELAY(); 514 return (val); 515 } 516 517 void 518 zs_write_reg(cs, reg, val) 519 struct zs_chanstate *cs; 520 u_char reg, val; 521 { 522 *cs->cs_reg_csr = reg; 523 ZS_DELAY(); 524 *cs->cs_reg_csr = val; 525 ZS_DELAY(); 526 } 527 528 u_char 529 zs_read_csr(cs) 530 struct zs_chanstate *cs; 531 { 532 u_char val; 533 534 val = *cs->cs_reg_csr; 535 ZS_DELAY(); 536 return (val); 537 } 538 539 void zs_write_csr(cs, val) 540 struct zs_chanstate *cs; 541 u_char val; 542 { 543 *cs->cs_reg_csr = val; 544 ZS_DELAY(); 545 } 546 547 u_char zs_read_data(cs) 548 struct zs_chanstate *cs; 549 { 550 u_char val; 551 552 val = *cs->cs_reg_data; 553 ZS_DELAY(); 554 return (val); 555 } 556 557 void zs_write_data(cs, val) 558 struct zs_chanstate *cs; 559 u_char val; 560 { 561 *cs->cs_reg_data = val; 562 ZS_DELAY(); 563 } 564 565 /**************************************************************** 566 * Console support functions (Sun specific!) 567 * Note: this code is allowed to know about the layout of 568 * the chip registers, and uses that to keep things simple. 569 * XXX - I think I like the mvme167 code better. -gwr 570 ****************************************************************/ 571 572 extern void Debugger __P((void)); 573 574 /* 575 * Handle user request to enter kernel debugger. 576 */ 577 void 578 zs_abort(cs) 579 struct zs_chanstate *cs; 580 { 581 volatile struct zschan *zc = zs_conschan_get; 582 int rr0; 583 584 /* Wait for end of break to avoid PROM abort. */ 585 /* XXX - Limit the wait? */ 586 do { 587 rr0 = zc->zc_csr; 588 ZS_DELAY(); 589 } while (rr0 & ZSRR0_BREAK); 590 591 #if defined(KGDB) 592 zskgdb(cs); 593 #elif defined(DDB) 594 { 595 extern int db_active; 596 597 if (!db_active) 598 Debugger(); 599 else 600 /* Debugger is probably hozed */ 601 callrom(); 602 } 603 #else 604 printf("stopping on keyboard abort\n"); 605 callrom(); 606 #endif 607 } 608 609 610 /* 611 * Polled input char. 612 */ 613 int 614 zs_getc(arg) 615 void *arg; 616 { 617 volatile struct zschan *zc = arg; 618 int s, c, rr0; 619 620 s = splhigh(); 621 /* Wait for a character to arrive. */ 622 do { 623 rr0 = zc->zc_csr; 624 ZS_DELAY(); 625 } while ((rr0 & ZSRR0_RX_READY) == 0); 626 627 c = zc->zc_data; 628 ZS_DELAY(); 629 splx(s); 630 631 /* 632 * This is used by the kd driver to read scan codes, 633 * so don't translate '\r' ==> '\n' here... 634 */ 635 return (c); 636 } 637 638 /* 639 * Polled output char. 640 */ 641 void 642 zs_putc(arg, c) 643 void *arg; 644 int c; 645 { 646 volatile struct zschan *zc = arg; 647 int s, rr0; 648 649 s = splhigh(); 650 651 /* Wait for transmitter to become ready. */ 652 do { 653 rr0 = zc->zc_csr; 654 ZS_DELAY(); 655 } while ((rr0 & ZSRR0_TX_READY) == 0); 656 657 /* 658 * Send the next character. 659 * Now you'd think that this could be followed by a ZS_DELAY() 660 * just like all the other chip accesses, but it turns out that 661 * the `transmit-ready' interrupt isn't de-asserted until 662 * some period of time after the register write completes 663 * (more than a couple instructions). So to avoid stray 664 * interrupts we put in the 2us delay regardless of cpu model. 665 */ 666 zc->zc_data = c; 667 delay(2); 668 669 splx(s); 670 } 671 672 /*****************************************************************/ 673 674 675 676 677 /* 678 * Polled console input putchar. 679 */ 680 static int 681 zscngetc(dev) 682 dev_t dev; 683 { 684 return (zs_getc(zs_conschan_get)); 685 } 686 687 /* 688 * Polled console output putchar. 689 */ 690 static void 691 zscnputc(dev, c) 692 dev_t dev; 693 int c; 694 { 695 zs_putc(zs_conschan_put, c); 696 } 697 698 int swallow_zsintrs; 699 700 static void 701 zscnpollc(dev, on) 702 dev_t dev; 703 int on; 704 { 705 /* 706 * Need to tell zs driver to acknowledge all interrupts or we get 707 * annoying spurious interrupt messages. This is because mucking 708 * with spl() levels during polling does not prevent interrupts from 709 * being generated. 710 */ 711 712 if (on) swallow_zsintrs++; 713 else swallow_zsintrs--; 714 } 715 716
Indexes created Thu Sep 25 16:09:42 GMT 2025