zs.c revision 1.9
1 /* $NetBSD: zs.c,v 1.9 2004/02/13 11:36:19 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.9 2004/02/13 11:36:19 wiz Exp $"); 49 50 #include "opt_ddb.h" 51 #include "opt_kgdb.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/conf.h> 56 #include <sys/device.h> 57 #include <sys/file.h> 58 #include <sys/ioctl.h> 59 #include <sys/kernel.h> 60 #include <sys/proc.h> 61 #include <sys/tty.h> 62 #include <sys/time.h> 63 #include <sys/syslog.h> 64 65 #include <machine/autoconf.h> 66 #include <machine/promlib.h> 67 #include <machine/cpu.h> 68 #include <machine/eeprom.h> 69 #include <machine/psl.h> 70 #include <machine/z8530var.h> 71 72 #include <dev/cons.h> 73 #include <dev/ic/z8530reg.h> 74 #include <dev/sun/kbd_ms_ttyvar.h> 75 #include <ddb/db_output.h> 76 77 #include <sun2/dev/cons.h> 78 79 #include "kbd.h" /* NKBD */ 80 #include "ms.h" /* NMS */ 81 82 /* 83 * Some warts needed by z8530tty.c - 84 * The default parity REALLY needs to be the same as the PROM uses, 85 * or you can not see messages done with printf during boot-up... 86 */ 87 int zs_def_cflag = (CREAD | CS8 | HUPCL); 88 89 /* ZS channel used as the console device (if any) */ 90 void *zs_conschan_get, *zs_conschan_put; 91 92 static u_char zs_init_reg[16] = { 93 0, /* 0: CMD (reset, etc.) */ 94 0, /* 1: No interrupts yet. */ 95 #ifdef ZS_INIT_IVECT 96 ZS_INIT_IVECT, /* 2: IVECT */ 97 #else 98 0, /* 2: IVECT */ 99 #endif 100 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 101 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 102 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 103 0, /* 6: TXSYNC/SYNCLO */ 104 0, /* 7: RXSYNC/SYNCHI */ 105 0, /* 8: alias for data port */ 106 #ifdef ZS_INIT_IVECT 107 ZSWR9_MASTER_IE, 108 #else 109 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 110 #endif 111 0, /*10: Misc. TX/RX control bits */ 112 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 113 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 114 0, /*13: BAUDHI (default=9600) */ 115 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 116 ZSWR15_BREAK_IE, 117 }; 118 119 /* Console ops */ 120 static int zscngetc __P((dev_t)); 121 static void zscnputc __P((dev_t, int)); 122 static void zscnpollc __P((dev_t, int)); 123 124 struct consdev zs_consdev = { 125 NULL, 126 NULL, 127 zscngetc, 128 zscnputc, 129 zscnpollc, 130 NULL, 131 }; 132 133 134 /**************************************************************** 135 * Autoconfig 136 ****************************************************************/ 137 138 static int zs_print __P((void *, const char *name)); 139 140 extern struct cfdriver zs_cd; 141 142 /* Interrupt handlers. */ 143 int zscheckintr __P((void *)); 144 static int zshard __P((void *)); 145 static void zssoft __P((void *)); 146 147 static int zs_get_speed __P((struct zs_chanstate *)); 148 149 /* 150 * Attach a found zs. 151 * 152 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 153 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 154 */ 155 void 156 zs_attach(zsc, zsd, pri) 157 struct zsc_softc *zsc; 158 struct zsdevice *zsd; 159 int pri; 160 { 161 struct zsc_attach_args zsc_args; 162 struct zs_chanstate *cs; 163 int s, channel, softpri = IPL_SOFTSERIAL; 164 165 if (zsd == NULL) { 166 printf("configuration incomplete\n"); 167 return; 168 } 169 170 printf(" softpri %d\n", softpri); 171 172 /* 173 * Initialize software state for each channel. 174 */ 175 for (channel = 0; channel < 2; channel++) { 176 struct zschan *zc; 177 struct device *child; 178 179 zsc_args.channel = channel; 180 cs = &zsc->zsc_cs_store[channel]; 181 zsc->zsc_cs[channel] = cs; 182 183 simple_lock_init(&cs->cs_lock); 184 cs->cs_channel = channel; 185 cs->cs_private = NULL; 186 cs->cs_ops = &zsops_null; 187 cs->cs_brg_clk = PCLK / 16; 188 189 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 190 191 zsc_args.consdev = NULL; 192 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 193 zsc->zsc_node, 194 channel); 195 196 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 197 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 198 zsc_args.consdev = &zs_consdev; 199 } 200 201 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 202 zs_conschan_get = zc; 203 } 204 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 205 zs_conschan_put = zc; 206 } 207 208 /* Children need to set cn_dev, etc */ 209 cs->cs_reg_csr = &zc->zc_csr; 210 cs->cs_reg_data = &zc->zc_data; 211 212 memcpy(cs->cs_creg, zs_init_reg, 16); 213 memcpy(cs->cs_preg, zs_init_reg, 16); 214 215 /* XXX: Consult PROM properties for this?! */ 216 cs->cs_defspeed = zs_get_speed(cs); 217 cs->cs_defcflag = zs_def_cflag; 218 219 /* Make these correspond to cs_defcflag (-crtscts) */ 220 cs->cs_rr0_dcd = ZSRR0_DCD; 221 cs->cs_rr0_cts = 0; 222 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 223 cs->cs_wr5_rts = 0; 224 225 /* 226 * Clear the master interrupt enable. 227 * The INTENA is common to both channels, 228 * so just do it on the A channel. 229 */ 230 if (channel == 0) { 231 zs_write_reg(cs, 9, 0); 232 } 233 234 /* 235 * Look for a child driver for this channel. 236 * The child attach will setup the hardware. 237 */ 238 if (!(child = 239 config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print))) { 240 /* No sub-driver. Just reset it. */ 241 u_char reset = (channel == 0) ? 242 ZSWR9_A_RESET : ZSWR9_B_RESET; 243 s = splzs(); 244 zs_write_reg(cs, 9, reset); 245 splx(s); 246 } 247 #if (NKBD > 0) || (NMS > 0) 248 /* 249 * If this was a zstty it has a keyboard 250 * property on it we need to attach the 251 * sunkbd and sunms line disciplines. 252 */ 253 if (child 254 && (!strcmp(child->dv_cfdata->cf_name, 255 "zstty"))) { 256 struct kbd_ms_tty_attach_args kma; 257 struct zstty_softc { 258 /* The following are the only fields we need here */ 259 struct device zst_dev; 260 struct tty *zst_tty; 261 struct zs_chanstate *zst_cs; 262 } *zst = (struct zstty_softc *)child; 263 struct tty *tp; 264 265 kma.kmta_tp = tp = zst->zst_tty; 266 if (tp != NULL) { 267 kma.kmta_dev = tp->t_dev; 268 kma.kmta_consdev = zsc_args.consdev; 269 270 /* Attach 'em if we got 'em. */ 271 switch(zs_peripheral_type(zsc->zsc_promunit, 272 zsc->zsc_node, 273 channel)) { 274 case ZS_PERIPHERAL_SUNKBD: 275 #if (NKBD > 0) 276 kma.kmta_name = "keyboard"; 277 config_found(child, (void *)&kma, NULL); 278 #endif 279 break; 280 case ZS_PERIPHERAL_SUNMS: 281 #if (NMS > 0) 282 kma.kmta_name = "mouse"; 283 config_found(child, (void *)&kma, NULL); 284 #endif 285 break; 286 default: 287 break; 288 } 289 } 290 } 291 #endif 292 } 293 294 /* 295 * Now safe to install interrupt handlers. Note the arguments 296 * to the interrupt handlers aren't used. Note, we only do this 297 * once since both SCCs interrupt at the same level and vector. 298 */ 299 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc); 300 if (!(zsc->zsc_softintr = softintr_establish(softpri, zssoft, zsc))) 301 panic("zsattach: could not establish soft interrupt"); 302 303 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 304 zsc->zsc_dev.dv_xname, "intr"); 305 306 307 /* 308 * Set the master interrupt enable and interrupt vector. 309 * (common to both channels, do it on A) 310 */ 311 cs = zsc->zsc_cs[0]; 312 s = splhigh(); 313 /* interrupt vector */ 314 zs_write_reg(cs, 2, zs_init_reg[2]); 315 /* master interrupt control (enable) */ 316 zs_write_reg(cs, 9, zs_init_reg[9]); 317 splx(s); 318 319 } 320 321 static int 322 zs_print(aux, name) 323 void *aux; 324 const char *name; 325 { 326 struct zsc_attach_args *args = aux; 327 328 if (name != NULL) 329 aprint_normal("%s: ", name); 330 331 if (args->channel != -1) 332 aprint_normal(" channel %d", args->channel); 333 334 return (UNCONF); 335 } 336 337 static int 338 zshard(arg) 339 void *arg; 340 { 341 struct zsc_softc *zsc = (struct zsc_softc *)arg; 342 int rr3, rval; 343 344 rval = 0; 345 while ((rr3 = zsc_intr_hard(zsc))) { 346 /* Count up the interrupts. */ 347 rval |= rr3; 348 zsc->zsc_intrcnt.ev_count++; 349 } 350 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 351 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 352 zsc->zsc_softintr) { 353 softintr_schedule(zsc->zsc_softintr); 354 } 355 return (rval); 356 } 357 358 int 359 zscheckintr(arg) 360 void *arg; 361 { 362 struct zsc_softc *zsc; 363 int unit, rval; 364 365 rval = 0; 366 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 367 368 zsc = zs_cd.cd_devs[unit]; 369 if (zsc == NULL) 370 continue; 371 rval = (zshard((void *)zsc) || rval); 372 } 373 return (rval); 374 } 375 376 377 /* 378 * We need this only for TTY_DEBUG purposes. 379 */ 380 static void 381 zssoft(arg) 382 void *arg; 383 { 384 struct zsc_softc *zsc = (struct zsc_softc *)arg; 385 int s; 386 387 /* Make sure we call the tty layer at spltty. */ 388 s = spltty(); 389 (void)zsc_intr_soft(zsc); 390 #ifdef TTY_DEBUG 391 { 392 struct zstty_softc *zst0 = zsc->zsc_cs[0]->cs_private; 393 struct zstty_softc *zst1 = zsc->zsc_cs[1]->cs_private; 394 if (zst0->zst_overflows || zst1->zst_overflows ) { 395 struct trapframe *frame = (struct trapframe *)arg; 396 397 printf("zs silo overflow from %p\n", 398 (long)frame->tf_pc); 399 } 400 } 401 #endif 402 splx(s); 403 } 404 405 406 /* 407 * Compute the current baud rate given a ZS channel. 408 */ 409 static int 410 zs_get_speed(cs) 411 struct zs_chanstate *cs; 412 { 413 int tconst; 414 415 tconst = zs_read_reg(cs, 12); 416 tconst |= zs_read_reg(cs, 13) << 8; 417 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 418 } 419 420 /* 421 * MD functions for setting the baud rate and control modes. 422 */ 423 int 424 zs_set_speed(cs, bps) 425 struct zs_chanstate *cs; 426 int bps; /* bits per second */ 427 { 428 int tconst, real_bps; 429 430 if (bps == 0) 431 return (0); 432 433 #ifdef DIAGNOSTIC 434 if (cs->cs_brg_clk == 0) 435 panic("zs_set_speed"); 436 #endif 437 438 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 439 if (tconst < 0) 440 return (EINVAL); 441 442 /* Convert back to make sure we can do it. */ 443 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 444 445 /* XXX - Allow some tolerance here? */ 446 if (real_bps != bps) 447 return (EINVAL); 448 449 cs->cs_preg[12] = tconst; 450 cs->cs_preg[13] = tconst >> 8; 451 452 /* Caller will stuff the pending registers. */ 453 return (0); 454 } 455 456 int 457 zs_set_modes(cs, cflag) 458 struct zs_chanstate *cs; 459 int cflag; /* bits per second */ 460 { 461 int s; 462 463 /* 464 * Output hardware flow control on the chip is horrendous: 465 * if carrier detect drops, the receiver is disabled, and if 466 * CTS drops, the transmitter is stoped IN MID CHARACTER! 467 * Therefore, NEVER set the HFC bit, and instead use the 468 * status interrupt to detect CTS changes. 469 */ 470 s = splzs(); 471 cs->cs_rr0_pps = 0; 472 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 473 cs->cs_rr0_dcd = 0; 474 if ((cflag & MDMBUF) == 0) 475 cs->cs_rr0_pps = ZSRR0_DCD; 476 } else 477 cs->cs_rr0_dcd = ZSRR0_DCD; 478 if ((cflag & CRTSCTS) != 0) { 479 cs->cs_wr5_dtr = ZSWR5_DTR; 480 cs->cs_wr5_rts = ZSWR5_RTS; 481 cs->cs_rr0_cts = ZSRR0_CTS; 482 } else if ((cflag & CDTRCTS) != 0) { 483 cs->cs_wr5_dtr = 0; 484 cs->cs_wr5_rts = ZSWR5_DTR; 485 cs->cs_rr0_cts = ZSRR0_CTS; 486 } else if ((cflag & MDMBUF) != 0) { 487 cs->cs_wr5_dtr = 0; 488 cs->cs_wr5_rts = ZSWR5_DTR; 489 cs->cs_rr0_cts = ZSRR0_DCD; 490 } else { 491 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 492 cs->cs_wr5_rts = 0; 493 cs->cs_rr0_cts = 0; 494 } 495 splx(s); 496 497 /* Caller will stuff the pending registers. */ 498 return (0); 499 } 500 501 502 /* 503 * Read or write the chip with suitable delays. 504 */ 505 506 u_char 507 zs_read_reg(cs, reg) 508 struct zs_chanstate *cs; 509 u_char reg; 510 { 511 u_char val; 512 513 *cs->cs_reg_csr = reg; 514 ZS_DELAY(); 515 val = *cs->cs_reg_csr; 516 ZS_DELAY(); 517 return (val); 518 } 519 520 void 521 zs_write_reg(cs, reg, val) 522 struct zs_chanstate *cs; 523 u_char reg, val; 524 { 525 *cs->cs_reg_csr = reg; 526 ZS_DELAY(); 527 *cs->cs_reg_csr = val; 528 ZS_DELAY(); 529 } 530 531 u_char 532 zs_read_csr(cs) 533 struct zs_chanstate *cs; 534 { 535 u_char val; 536 537 val = *cs->cs_reg_csr; 538 ZS_DELAY(); 539 return (val); 540 } 541 542 void zs_write_csr(cs, val) 543 struct zs_chanstate *cs; 544 u_char val; 545 { 546 *cs->cs_reg_csr = val; 547 ZS_DELAY(); 548 } 549 550 u_char zs_read_data(cs) 551 struct zs_chanstate *cs; 552 { 553 u_char val; 554 555 val = *cs->cs_reg_data; 556 ZS_DELAY(); 557 return (val); 558 } 559 560 void zs_write_data(cs, val) 561 struct zs_chanstate *cs; 562 u_char val; 563 { 564 *cs->cs_reg_data = val; 565 ZS_DELAY(); 566 } 567 568 /**************************************************************** 569 * Console support functions (Sun specific!) 570 * Note: this code is allowed to know about the layout of 571 * the chip registers, and uses that to keep things simple. 572 * XXX - I think I like the mvme167 code better. -gwr 573 ****************************************************************/ 574 575 extern void Debugger __P((void)); 576 577 /* 578 * Handle user request to enter kernel debugger. 579 */ 580 void 581 zs_abort(cs) 582 struct zs_chanstate *cs; 583 { 584 volatile struct zschan *zc = zs_conschan_get; 585 int rr0; 586 587 /* Wait for end of break to avoid PROM abort. */ 588 /* XXX - Limit the wait? */ 589 do { 590 rr0 = zc->zc_csr; 591 ZS_DELAY(); 592 } while (rr0 & ZSRR0_BREAK); 593 594 #if defined(KGDB) 595 zskgdb(cs); 596 #elif defined(DDB) 597 { 598 extern int db_active; 599 600 if (!db_active) 601 Debugger(); 602 else 603 /* Debugger is probably hozed */ 604 callrom(); 605 } 606 #else 607 printf("stopping on keyboard abort\n"); 608 callrom(); 609 #endif 610 } 611 612 613 /* 614 * Polled input char. 615 */ 616 int 617 zs_getc(arg) 618 void *arg; 619 { 620 volatile struct zschan *zc = arg; 621 int s, c, rr0; 622 623 s = splhigh(); 624 /* Wait for a character to arrive. */ 625 do { 626 rr0 = zc->zc_csr; 627 ZS_DELAY(); 628 } while ((rr0 & ZSRR0_RX_READY) == 0); 629 630 c = zc->zc_data; 631 ZS_DELAY(); 632 splx(s); 633 634 /* 635 * This is used by the kd driver to read scan codes, 636 * so don't translate '\r' ==> '\n' here... 637 */ 638 return (c); 639 } 640 641 /* 642 * Polled output char. 643 */ 644 void 645 zs_putc(arg, c) 646 void *arg; 647 int c; 648 { 649 volatile struct zschan *zc = arg; 650 int s, rr0; 651 652 s = splhigh(); 653 654 /* Wait for transmitter to become ready. */ 655 do { 656 rr0 = zc->zc_csr; 657 ZS_DELAY(); 658 } while ((rr0 & ZSRR0_TX_READY) == 0); 659 660 /* 661 * Send the next character. 662 * Now you'd think that this could be followed by a ZS_DELAY() 663 * just like all the other chip accesses, but it turns out that 664 * the `transmit-ready' interrupt isn't de-asserted until 665 * some period of time after the register write completes 666 * (more than a couple instructions). So to avoid stray 667 * interrupts we put in the 2us delay regardless of CPU model. 668 */ 669 zc->zc_data = c; 670 delay(2); 671 672 splx(s); 673 } 674 675 /*****************************************************************/ 676 677 678 679 680 /* 681 * Polled console input putchar. 682 */ 683 static int 684 zscngetc(dev) 685 dev_t dev; 686 { 687 return (zs_getc(zs_conschan_get)); 688 } 689 690 /* 691 * Polled console output putchar. 692 */ 693 static void 694 zscnputc(dev, c) 695 dev_t dev; 696 int c; 697 { 698 zs_putc(zs_conschan_put, c); 699 } 700 701 int swallow_zsintrs; 702 703 static void 704 zscnpollc(dev, on) 705 dev_t dev; 706 int on; 707 { 708 /* 709 * Need to tell zs driver to acknowledge all interrupts or we get 710 * annoying spurious interrupt messages. This is because mucking 711 * with spl() levels during polling does not prevent interrupts from 712 * being generated. 713 */ 714 715 if (on) swallow_zsintrs++; 716 else swallow_zsintrs--; 717 } 718 719
Indexes created Thu Sep 25 06:09:39 GMT 2025