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cg4.c revision 1.39.40.1
      1  1.39.40.1       tls /*	$NetBSD: cg4.c,v 1.39.40.1 2014/08/20 00:03:26 tls Exp $	*/
      2        1.1       gwr 
      3        1.1       gwr /*
      4        1.1       gwr  * Copyright (c) 1992, 1993
      5        1.1       gwr  *	The Regents of the University of California.  All rights reserved.
      6        1.1       gwr  *
      7        1.1       gwr  * This software was developed by the Computer Systems Engineering group
      8        1.1       gwr  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
      9        1.1       gwr  * contributed to Berkeley.
     10        1.1       gwr  *
     11        1.1       gwr  * All advertising materials mentioning features or use of this software
     12        1.1       gwr  * must display the following acknowledgement:
     13        1.1       gwr  *	This product includes software developed by the University of
     14        1.1       gwr  *	California, Lawrence Berkeley Laboratory.
     15        1.1       gwr  *
     16        1.1       gwr  * Redistribution and use in source and binary forms, with or without
     17        1.1       gwr  * modification, are permitted provided that the following conditions
     18        1.1       gwr  * are met:
     19        1.1       gwr  * 1. Redistributions of source code must retain the above copyright
     20        1.1       gwr  *    notice, this list of conditions and the following disclaimer.
     21        1.1       gwr  * 2. Redistributions in binary form must reproduce the above copyright
     22        1.1       gwr  *    notice, this list of conditions and the following disclaimer in the
     23        1.1       gwr  *    documentation and/or other materials provided with the distribution.
     24       1.31       agc  * 3. Neither the name of the University nor the names of its contributors
     25        1.1       gwr  *    may be used to endorse or promote products derived from this software
     26        1.1       gwr  *    without specific prior written permission.
     27        1.1       gwr  *
     28        1.1       gwr  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29        1.1       gwr  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30        1.1       gwr  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31        1.1       gwr  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32        1.1       gwr  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33        1.1       gwr  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34        1.1       gwr  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35        1.1       gwr  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36        1.1       gwr  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37        1.1       gwr  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38        1.1       gwr  * SUCH DAMAGE.
     39        1.1       gwr  *
     40        1.1       gwr  *	from: @(#)cgthree.c	8.2 (Berkeley) 10/30/93
     41        1.1       gwr  */
     42        1.1       gwr 
     43        1.1       gwr /*
     44        1.1       gwr  * color display (cg4) driver.
     45        1.1       gwr  *
     46       1.11       gwr  * Credits, history:
     47       1.11       gwr  * Gordon Ross created this driver based on the cg3 driver from
     48       1.11       gwr  * the sparc port as distributed in BSD 4.4 Lite, but included
     49       1.11       gwr  * support for only the "type B" adapter (Brooktree DACs).
     50       1.11       gwr  * Ezra Story added support for the "type A" (AMD DACs).
     51        1.1       gwr  *
     52       1.11       gwr  * Todo:
     53       1.11       gwr  * Make this driver handle video interrupts.
     54       1.11       gwr  * Defer colormap updates to vertical retrace interrupts.
     55        1.1       gwr  */
     56       1.30     lukem 
     57       1.30     lukem #include <sys/cdefs.h>
     58  1.39.40.1       tls __KERNEL_RCSID(0, "$NetBSD: cg4.c,v 1.39.40.1 2014/08/20 00:03:26 tls Exp $");
     59        1.1       gwr 
     60        1.1       gwr #include <sys/param.h>
     61       1.11       gwr #include <sys/systm.h>
     62       1.12       gwr #include <sys/conf.h>
     63        1.1       gwr #include <sys/device.h>
     64        1.1       gwr #include <sys/ioctl.h>
     65        1.1       gwr #include <sys/malloc.h>
     66        1.1       gwr #include <sys/mman.h>
     67       1.12       gwr #include <sys/proc.h>
     68        1.1       gwr #include <sys/tty.h>
     69        1.1       gwr 
     70       1.21       mrg #include <uvm/uvm_extern.h>
     71        1.1       gwr 
     72       1.12       gwr #include <machine/autoconf.h>
     73        1.2       gwr #include <machine/cpu.h>
     74       1.23   thorpej #include <dev/sun/fbio.h>
     75       1.12       gwr #include <machine/idprom.h>
     76        1.1       gwr #include <machine/pmap.h>
     77        1.1       gwr 
     78       1.15       gwr #include <sun3/dev/fbvar.h>
     79       1.15       gwr #include <sun3/dev/btreg.h>
     80       1.15       gwr #include <sun3/dev/cg4reg.h>
     81       1.15       gwr #include <sun3/dev/p4reg.h>
     82       1.15       gwr 
     83       1.39   tsutsui #include "ioconf.h"
     84       1.39   tsutsui 
     85       1.18       gwr union bt_cmap_u {
     86       1.39   tsutsui 	uint8_t  btcm_char[256 * 3];		/* raw data */
     87       1.39   tsutsui 	uint8_t  btcm_rgb[256][3];		/* 256 R/G/B entries */
     88       1.18       gwr 	u_int   btcm_int[256 * 3 / 4];	/* the way the chip gets loaded */
     89       1.18       gwr };
     90       1.18       gwr 
     91       1.15       gwr #define CG4_TYPE_A 0	/* AMD DACs */
     92       1.15       gwr #define CG4_TYPE_B 1	/* Brooktree DACs */
     93        1.1       gwr 
     94       1.11       gwr #define	CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE)
     95       1.11       gwr 
     96       1.11       gwr #define CMAP_SIZE 256
     97       1.11       gwr struct soft_cmap {
     98       1.39   tsutsui 	uint8_t r[CMAP_SIZE];
     99       1.39   tsutsui 	uint8_t g[CMAP_SIZE];
    100       1.39   tsutsui 	uint8_t b[CMAP_SIZE];
    101       1.11       gwr };
    102       1.11       gwr 
    103        1.1       gwr /* per-display variables */
    104        1.1       gwr struct cg4_softc {
    105       1.39   tsutsui 	device_t sc_dev;		/* base device */
    106        1.1       gwr 	struct	fbdevice sc_fb;		/* frame buffer device */
    107       1.11       gwr 	int 	sc_cg4type;		/* A or B */
    108       1.11       gwr 	int 	sc_pa_overlay;		/* phys. addr. of overlay plane */
    109       1.11       gwr 	int 	sc_pa_enable;		/* phys. addr. of enable plane */
    110       1.11       gwr 	int 	sc_pa_pixmap;		/* phys. addr. of color plane */
    111       1.14       gwr 	int 	sc_video_on;		/* zero if blanked */
    112       1.14       gwr 	void	*sc_va_cmap;		/* Colormap h/w (mapped KVA) */
    113       1.14       gwr 	void	*sc_btcm;		/* Soft cmap, Brooktree format */
    114       1.32       chs 	void	(*sc_ldcmap)(struct cg4_softc *);
    115       1.14       gwr 	struct soft_cmap sc_cmap;	/* Soft cmap, user format */
    116        1.1       gwr };
    117        1.1       gwr 
    118        1.1       gwr /* autoconfiguration driver */
    119       1.39   tsutsui static int	cg4match(device_t, cfdata_t, void *);
    120       1.39   tsutsui static void	cg4attach(device_t, device_t, void *);
    121        1.1       gwr 
    122       1.39   tsutsui CFATTACH_DECL_NEW(cgfour, sizeof(struct cg4_softc),
    123       1.28   thorpej     cg4match, cg4attach, NULL, NULL);
    124        1.7   thorpej 
    125       1.25   gehenna dev_type_open(cg4open);
    126       1.25   gehenna dev_type_ioctl(cg4ioctl);
    127       1.25   gehenna dev_type_mmap(cg4mmap);
    128       1.25   gehenna 
    129       1.25   gehenna const struct cdevsw cgfour_cdevsw = {
    130  1.39.40.1       tls 	.d_open = cg4open,
    131  1.39.40.1       tls 	.d_close = nullclose,
    132  1.39.40.1       tls 	.d_read = noread,
    133  1.39.40.1       tls 	.d_write = nowrite,
    134  1.39.40.1       tls 	.d_ioctl = cg4ioctl,
    135  1.39.40.1       tls 	.d_stop = nostop,
    136  1.39.40.1       tls 	.d_tty = notty,
    137  1.39.40.1       tls 	.d_poll = nopoll,
    138  1.39.40.1       tls 	.d_mmap = cg4mmap,
    139  1.39.40.1       tls 	.d_kqfilter = nokqfilter,
    140  1.39.40.1       tls 	.d_discard = nodiscard,
    141  1.39.40.1       tls 	.d_flag = 0
    142       1.25   gehenna };
    143       1.25   gehenna 
    144       1.32       chs static int	cg4gattr  (struct fbdevice *, void *);
    145       1.32       chs static int	cg4gvideo (struct fbdevice *, void *);
    146       1.32       chs static int	cg4svideo (struct fbdevice *, void *);
    147       1.32       chs static int	cg4getcmap(struct fbdevice *, void *);
    148       1.32       chs static int	cg4putcmap(struct fbdevice *, void *);
    149        1.1       gwr 
    150       1.18       gwr #ifdef	_SUN3_
    151       1.32       chs static void	cg4a_init  (struct cg4_softc *);
    152       1.32       chs static void	cg4a_ldcmap(struct cg4_softc *);
    153       1.18       gwr #endif	/* SUN3 */
    154       1.11       gwr 
    155       1.32       chs static void	cg4b_init  (struct cg4_softc *);
    156       1.32       chs static void	cg4b_ldcmap(struct cg4_softc *);
    157       1.11       gwr 
    158       1.11       gwr static struct fbdriver cg4_fbdriver = {
    159       1.29  jdolecek 	cg4open, nullclose, cg4mmap, nokqfilter, cg4gattr,
    160        1.1       gwr 	cg4gvideo, cg4svideo,
    161        1.1       gwr 	cg4getcmap, cg4putcmap };
    162        1.1       gwr 
    163        1.1       gwr /*
    164        1.1       gwr  * Match a cg4.
    165        1.1       gwr  */
    166       1.32       chs static int
    167       1.39   tsutsui cg4match(device_t parent, cfdata_t cf, void *args)
    168        1.1       gwr {
    169        1.1       gwr 	struct confargs *ca = args;
    170       1.17       gwr 	int mid, p4id, peekval, tmp;
    171       1.15       gwr 	void *p4reg;
    172       1.15       gwr 
    173       1.15       gwr 	/* No default address support. */
    174       1.15       gwr 	if (ca->ca_paddr == -1)
    175       1.39   tsutsui 		return 0;
    176       1.15       gwr 
    177       1.15       gwr 	/*
    178       1.15       gwr 	 * Slight hack here:  The low four bits of the
    179       1.15       gwr 	 * config flags, if set, restrict the match to
    180       1.15       gwr 	 * that machine "implementation" only.
    181       1.15       gwr 	 */
    182       1.15       gwr 	mid = cf->cf_flags & IDM_IMPL_MASK;
    183       1.15       gwr 	if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK)))
    184       1.39   tsutsui 		return 0;
    185        1.2       gwr 
    186       1.15       gwr 	/*
    187       1.15       gwr 	 * The config flag 0x10 if set means we are
    188       1.17       gwr 	 * looking for a Type A board (3/110).
    189       1.15       gwr 	 */
    190       1.17       gwr 	if (cf->cf_flags & 0x10) {
    191       1.15       gwr #ifdef	_SUN3_
    192       1.17       gwr 		/* Type A: Check for AMD RAMDACs in control space. */
    193       1.11       gwr 		if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1)
    194       1.39   tsutsui 			return 0;
    195       1.17       gwr 		/* Check for the overlay plane. */
    196       1.17       gwr 		tmp = ca->ca_paddr + CG4A_OFF_OVERLAY;
    197       1.17       gwr 		if (bus_peek(ca->ca_bustype, tmp, 1) == -1)
    198       1.39   tsutsui 			return 0;
    199       1.17       gwr 		/* OK, it looks like a Type A. */
    200       1.39   tsutsui 		return 1;
    201       1.17       gwr #else	/* SUN3 */
    202       1.17       gwr 		/* Only the Sun3/110 ever has a type A. */
    203       1.39   tsutsui 		return 0;
    204       1.17       gwr #endif	/* SUN3 */
    205       1.15       gwr 	}
    206       1.11       gwr 
    207       1.15       gwr 	/*
    208       1.17       gwr 	 * From here on, it is a type B or nothing.
    209       1.17       gwr 	 * The config flag 0x20 if set means there
    210       1.17       gwr 	 * is no P4 register.  (bus error)
    211       1.15       gwr 	 */
    212       1.17       gwr 	if ((cf->cf_flags & 0x20) == 0) {
    213       1.17       gwr 		p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr);
    214       1.17       gwr 		peekval = peek_long(p4reg);
    215       1.17       gwr 		p4id = (peekval == -1) ?
    216       1.17       gwr 			P4_NOTFOUND : fb_pfour_id(p4reg);
    217       1.17       gwr 		bus_tmapout(p4reg);
    218       1.17       gwr 		if (peekval == -1)
    219       1.17       gwr 			return (0);
    220       1.17       gwr 		if (p4id != P4_ID_COLOR8P1) {
    221       1.15       gwr #ifdef	DEBUG
    222       1.39   tsutsui 			aprint_debug("cgfour at 0x%lx match p4id=0x%x fails\n",
    223       1.39   tsutsui 			    ca->ca_paddr, p4id & 0xFF);
    224       1.15       gwr #endif
    225       1.39   tsutsui 			return 0;
    226       1.17       gwr 		}
    227        1.2       gwr 	}
    228        1.1       gwr 
    229       1.17       gwr 	/*
    230       1.17       gwr 	 * Check for CMAP hardware and overlay plane.
    231       1.17       gwr 	 */
    232       1.17       gwr 	tmp = ca->ca_paddr + CG4B_OFF_CMAP;
    233       1.17       gwr 	if (bus_peek(ca->ca_bustype, tmp, 4) == -1)
    234       1.39   tsutsui 		return 0;
    235       1.17       gwr 	tmp = ca->ca_paddr + CG4B_OFF_OVERLAY;
    236       1.17       gwr 	if (bus_peek(ca->ca_bustype, tmp, 1) == -1)
    237       1.39   tsutsui 		return 0;
    238       1.17       gwr 
    239       1.39   tsutsui 	return 1;
    240        1.1       gwr }
    241        1.1       gwr 
    242        1.1       gwr /*
    243        1.1       gwr  * Attach a display.  We need to notice if it is the console, too.
    244        1.1       gwr  */
    245       1.32       chs static void
    246       1.39   tsutsui cg4attach(device_t parent, device_t self, void *args)
    247        1.1       gwr {
    248       1.38   tsutsui 	struct cg4_softc *sc = device_private(self);
    249        1.1       gwr 	struct fbdevice *fb = &sc->sc_fb;
    250        1.1       gwr 	struct confargs *ca = args;
    251        1.1       gwr 	struct fbtype *fbt;
    252       1.17       gwr 	int tmp;
    253        1.1       gwr 
    254       1.39   tsutsui 	sc->sc_dev = self;
    255       1.39   tsutsui 
    256        1.1       gwr 	fbt = &fb->fb_fbtype;
    257        1.1       gwr 	fbt->fb_type = FBTYPE_SUN4COLOR;
    258       1.15       gwr 	fbt->fb_width = 1152;	/* default - see below */
    259       1.15       gwr 	fbt->fb_height = 900;	/* default - see below */
    260        1.1       gwr 	fbt->fb_depth = 8;
    261        1.1       gwr 	fbt->fb_cmsize = 256;
    262       1.15       gwr 	fbt->fb_size = CG4_MMAP_SIZE;
    263       1.15       gwr 	fb->fb_driver = &cg4_fbdriver;
    264       1.15       gwr 	fb->fb_private = sc;
    265       1.39   tsutsui 	fb->fb_name  = device_xname(self);
    266       1.39   tsutsui 	fb->fb_flags = device_cfdata(self)->cf_flags;
    267        1.1       gwr 
    268       1.15       gwr 	/*
    269       1.15       gwr 	 * The config flag 0x10 if set means we are
    270       1.15       gwr 	 * attaching a Type A (3/110) which has the
    271       1.15       gwr 	 * AMD RAMDACs in control space, and no P4.
    272       1.15       gwr 	 */
    273       1.15       gwr 	if (fb->fb_flags & 0x10) {
    274       1.15       gwr #ifdef	_SUN3_
    275       1.15       gwr 		sc->sc_cg4type = CG4_TYPE_A;
    276       1.15       gwr 		sc->sc_ldcmap  = cg4a_ldcmap;
    277       1.11       gwr 		sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY;
    278       1.11       gwr 		sc->sc_pa_enable  = ca->ca_paddr + CG4A_OFF_ENABLE;
    279       1.11       gwr 		sc->sc_pa_pixmap  = ca->ca_paddr + CG4A_OFF_PIXMAP;
    280       1.16       gwr 		sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP,
    281       1.16       gwr 		                           sizeof(struct amd_regs));
    282       1.11       gwr 		cg4a_init(sc);
    283       1.15       gwr #else	/* SUN3 */
    284       1.15       gwr 		panic("cgfour flags 0x10");
    285       1.15       gwr #endif	/* SUN3 */
    286       1.15       gwr 	} else {
    287       1.15       gwr 		sc->sc_cg4type = CG4_TYPE_B;
    288       1.15       gwr 		sc->sc_ldcmap  = cg4b_ldcmap;
    289       1.11       gwr 		sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY;
    290       1.11       gwr 		sc->sc_pa_enable  = ca->ca_paddr + CG4B_OFF_ENABLE;
    291       1.11       gwr 		sc->sc_pa_pixmap  = ca->ca_paddr + CG4B_OFF_PIXMAP;
    292       1.17       gwr 		tmp               = ca->ca_paddr + CG4B_OFF_CMAP;
    293       1.16       gwr 		sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp,
    294       1.16       gwr 		                           sizeof(struct bt_regs));
    295       1.11       gwr 		cg4b_init(sc);
    296       1.17       gwr 	}
    297       1.15       gwr 
    298       1.17       gwr 	if ((fb->fb_flags & 0x20) == 0) {
    299       1.17       gwr 		/* It is supposed to have a P4 register. */
    300       1.17       gwr 		fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4);
    301       1.11       gwr 	}
    302        1.1       gwr 
    303       1.15       gwr 	/*
    304       1.15       gwr 	 * Determine width and height as follows:
    305       1.15       gwr 	 * If it has a P4 register, use that;
    306       1.15       gwr 	 * else if unit==0, use the EEPROM size,
    307       1.15       gwr 	 * else make our best guess.
    308       1.15       gwr 	 */
    309       1.15       gwr 	if (fb->fb_pfour)
    310       1.15       gwr 		fb_pfour_setsize(fb);
    311       1.34   thorpej 	/* XXX device_unit() abuse */
    312       1.39   tsutsui 	else if (device_unit(self) == 0)
    313       1.15       gwr 		fb_eeprom_setsize(fb);
    314       1.15       gwr 	else {
    315       1.15       gwr 		/* Guess based on machine ID. */
    316       1.15       gwr 		switch (cpu_machine_id) {
    317       1.15       gwr 		default:
    318       1.15       gwr 			/* Leave the defaults set above. */
    319       1.15       gwr 			break;
    320       1.15       gwr 		}
    321       1.15       gwr 	}
    322       1.39   tsutsui 	aprint_normal(" (%dx%d)\n", fbt->fb_width, fbt->fb_height);
    323       1.15       gwr 
    324       1.15       gwr 	/*
    325       1.15       gwr 	 * Make sure video is on.  This driver uses a
    326       1.15       gwr 	 * black colormap to blank the screen, so if
    327       1.15       gwr 	 * there is any global enable, set it here.
    328       1.15       gwr 	 */
    329       1.15       gwr 	tmp = 1;
    330       1.15       gwr 	cg4svideo(fb, &tmp);
    331       1.15       gwr 	if (fb->fb_pfour)
    332       1.15       gwr 		fb_pfour_set_video(fb, 1);
    333       1.15       gwr 	else
    334       1.15       gwr 		enable_video(1);
    335       1.15       gwr 
    336       1.15       gwr 	/* Let /dev/fb know we are here. */
    337        1.2       gwr 	fb_attach(fb, 4);
    338        1.1       gwr }
    339        1.1       gwr 
    340       1.32       chs int
    341       1.33  christos cg4open(dev_t dev, int flags, int mode, struct lwp *l)
    342        1.1       gwr {
    343       1.38   tsutsui 	struct cg4_softc *sc;
    344        1.1       gwr 	int unit = minor(dev);
    345        1.1       gwr 
    346       1.38   tsutsui 	sc = device_lookup_private(&cgfour_cd, unit);
    347       1.38   tsutsui 	if (sc == NULL)
    348       1.39   tsutsui 		return ENXIO;
    349       1.39   tsutsui 	return 0;
    350        1.1       gwr }
    351        1.1       gwr 
    352       1.32       chs int
    353       1.36  christos cg4ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
    354        1.1       gwr {
    355       1.38   tsutsui 	struct cg4_softc *sc = device_lookup_private(&cgfour_cd, minor(dev));
    356        1.1       gwr 
    357       1.39   tsutsui 	return fbioctlfb(&sc->sc_fb, cmd, data);
    358        1.1       gwr }
    359        1.1       gwr 
    360        1.1       gwr /*
    361        1.1       gwr  * Return the address that would map the given device at the given
    362        1.1       gwr  * offset, allowing for the given protection, or return -1 for error.
    363        1.1       gwr  *
    364        1.1       gwr  * X11 expects its mmap'd region to look like this:
    365       1.11       gwr  * 	128k overlay data memory
    366       1.11       gwr  * 	128k overlay enable bitmap
    367        1.1       gwr  * 	1024k color memory
    368       1.15       gwr  *
    369       1.15       gwr  * The hardware looks completely different.
    370        1.1       gwr  */
    371       1.32       chs paddr_t
    372       1.32       chs cg4mmap(dev_t dev, off_t off, int prot)
    373        1.1       gwr {
    374       1.38   tsutsui 	struct cg4_softc *sc = device_lookup_private(&cgfour_cd, minor(dev));
    375       1.22   tsutsui 	int physbase;
    376        1.1       gwr 
    377        1.1       gwr 	if (off & PGOFSET)
    378       1.39   tsutsui 		panic("%s: bad offset", __func__);
    379        1.1       gwr 
    380       1.14       gwr 	if ((off < 0) || (off >= CG4_MMAP_SIZE))
    381       1.39   tsutsui 		return -1;
    382        1.2       gwr 
    383        1.2       gwr 	if (off < 0x40000) {
    384        1.2       gwr 		if (off < 0x20000) {
    385       1.11       gwr 			physbase = sc->sc_pa_overlay;
    386        1.2       gwr 		} else {
    387        1.2       gwr 			/* enable plane */
    388        1.2       gwr 			off -= 0x20000;
    389       1.11       gwr 			physbase = sc->sc_pa_enable;
    390        1.2       gwr 		}
    391        1.2       gwr 	} else {
    392        1.2       gwr 		/* pixel map */
    393        1.2       gwr 		off -= 0x40000;
    394       1.11       gwr 		physbase = sc->sc_pa_pixmap;
    395        1.1       gwr 	}
    396        1.1       gwr 
    397        1.1       gwr 	/*
    398        1.1       gwr 	 * I turned on PMAP_NC here to disable the cache as I was
    399       1.15       gwr 	 * getting horribly broken behaviour without it.
    400        1.1       gwr 	 */
    401       1.39   tsutsui 	return (physbase + off) | PMAP_NC;
    402        1.1       gwr }
    403        1.1       gwr 
    404        1.1       gwr /*
    405        1.1       gwr  * Internal ioctl functions.
    406        1.1       gwr  */
    407        1.1       gwr 
    408        1.1       gwr /* FBIOGATTR: */
    409       1.32       chs static int
    410       1.32       chs cg4gattr(struct fbdevice *fb, void *data)
    411        1.1       gwr {
    412       1.12       gwr 	struct fbgattr *fba = data;
    413        1.1       gwr 
    414        1.1       gwr 	fba->real_type = fb->fb_fbtype.fb_type;
    415        1.1       gwr 	fba->owner = 0;		/* XXX - TIOCCONS stuff? */
    416        1.1       gwr 	fba->fbtype = fb->fb_fbtype;
    417        1.1       gwr 	fba->sattr.flags = 0;
    418        1.1       gwr 	fba->sattr.emu_type = fb->fb_fbtype.fb_type;
    419        1.1       gwr 	fba->sattr.dev_specific[0] = -1;
    420        1.1       gwr 	fba->emu_types[0] = fb->fb_fbtype.fb_type;
    421        1.1       gwr 	fba->emu_types[1] = -1;
    422       1.39   tsutsui 	return 0;
    423        1.1       gwr }
    424        1.1       gwr 
    425        1.1       gwr /* FBIOGVIDEO: */
    426       1.32       chs static int
    427       1.32       chs cg4gvideo(struct fbdevice *fb, void *data)
    428        1.1       gwr {
    429       1.14       gwr 	struct cg4_softc *sc = fb->fb_private;
    430       1.12       gwr 	int *on = data;
    431        1.1       gwr 
    432       1.14       gwr 	*on = sc->sc_video_on;
    433       1.39   tsutsui 	return 0;
    434        1.1       gwr }
    435        1.1       gwr 
    436        1.1       gwr /* FBIOSVIDEO: */
    437       1.32       chs static int
    438       1.32       chs cg4svideo(struct fbdevice *fb, void *data)
    439        1.1       gwr {
    440       1.14       gwr 	struct cg4_softc *sc = fb->fb_private;
    441       1.12       gwr 	int *on = data;
    442       1.11       gwr 
    443       1.14       gwr 	if (sc->sc_video_on == *on)
    444       1.39   tsutsui 		return 0;
    445       1.14       gwr 	sc->sc_video_on = *on;
    446       1.14       gwr 
    447       1.15       gwr 	(*sc->sc_ldcmap)(sc);
    448       1.39   tsutsui 	return 0;
    449       1.11       gwr }
    450       1.11       gwr 
    451       1.11       gwr /*
    452       1.11       gwr  * FBIOGETCMAP:
    453       1.11       gwr  * Copy current colormap out to user space.
    454       1.11       gwr  */
    455       1.32       chs static int
    456       1.32       chs cg4getcmap(struct fbdevice *fb, void *data)
    457       1.11       gwr {
    458       1.11       gwr 	struct cg4_softc *sc = fb->fb_private;
    459       1.11       gwr 	struct soft_cmap *cm = &sc->sc_cmap;
    460       1.14       gwr 	struct fbcmap *fbcm = data;
    461       1.24    itojun 	u_int start, count;
    462       1.24    itojun 	int error;
    463       1.11       gwr 
    464       1.11       gwr 	start = fbcm->index;
    465       1.11       gwr 	count = fbcm->count;
    466       1.24    itojun 	if (start >= CMAP_SIZE || count > CMAP_SIZE - start)
    467       1.39   tsutsui 		return EINVAL;
    468       1.11       gwr 
    469       1.11       gwr 	if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0)
    470       1.39   tsutsui 		return error;
    471       1.11       gwr 
    472       1.11       gwr 	if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0)
    473       1.39   tsutsui 		return error;
    474       1.11       gwr 
    475       1.11       gwr 	if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0)
    476       1.39   tsutsui 		return error;
    477       1.11       gwr 
    478       1.39   tsutsui 	return 0;
    479       1.11       gwr }
    480       1.11       gwr 
    481       1.11       gwr /*
    482       1.11       gwr  * FBIOPUTCMAP:
    483       1.11       gwr  * Copy new colormap from user space and load.
    484       1.11       gwr  */
    485       1.32       chs static int
    486       1.32       chs cg4putcmap(struct fbdevice *fb, void *data)
    487       1.11       gwr {
    488       1.11       gwr 	struct cg4_softc *sc = fb->fb_private;
    489       1.11       gwr 	struct soft_cmap *cm = &sc->sc_cmap;
    490       1.14       gwr 	struct fbcmap *fbcm = data;
    491       1.24    itojun 	u_int start, count;
    492       1.24    itojun 	int error;
    493       1.11       gwr 
    494       1.11       gwr 	start = fbcm->index;
    495       1.11       gwr 	count = fbcm->count;
    496       1.24    itojun 	if (start >= CMAP_SIZE || count > CMAP_SIZE - start)
    497       1.39   tsutsui 		return EINVAL;
    498       1.11       gwr 
    499       1.11       gwr 	if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0)
    500       1.39   tsutsui 		return error;
    501       1.11       gwr 
    502       1.11       gwr 	if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0)
    503       1.39   tsutsui 		return error;
    504       1.11       gwr 
    505       1.11       gwr 	if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0)
    506       1.39   tsutsui 		return error;
    507       1.11       gwr 
    508       1.15       gwr 	(*sc->sc_ldcmap)(sc);
    509       1.39   tsutsui 	return 0;
    510       1.11       gwr }
    511       1.11       gwr 
    512       1.11       gwr /****************************************************************
    513       1.11       gwr  * Routines for the "Type A" hardware
    514       1.11       gwr  ****************************************************************/
    515       1.15       gwr #ifdef	_SUN3_
    516       1.11       gwr 
    517       1.32       chs static void
    518       1.32       chs cg4a_init(struct cg4_softc *sc)
    519       1.11       gwr {
    520       1.11       gwr 	volatile struct amd_regs *ar = sc->sc_va_cmap;
    521       1.11       gwr 	struct soft_cmap *cm = &sc->sc_cmap;
    522       1.11       gwr 	int i;
    523       1.11       gwr 
    524       1.14       gwr 	/* Grab initial (current) color map. */
    525       1.11       gwr 	for(i = 0; i < 256; i++) {
    526       1.11       gwr 		cm->r[i] = ar->r[i];
    527       1.11       gwr 		cm->g[i] = ar->g[i];
    528       1.11       gwr 		cm->b[i] = ar->b[i];
    529       1.11       gwr 	}
    530       1.11       gwr }
    531       1.11       gwr 
    532       1.32       chs static void
    533       1.32       chs cg4a_ldcmap(struct cg4_softc *sc)
    534       1.11       gwr {
    535       1.11       gwr 	volatile struct amd_regs *ar = sc->sc_va_cmap;
    536       1.11       gwr 	struct soft_cmap *cm = &sc->sc_cmap;
    537       1.11       gwr 	int i;
    538       1.11       gwr 
    539       1.11       gwr 	/*
    540       1.11       gwr 	 * Now blast them into the chip!
    541       1.11       gwr 	 * XXX Should use retrace interrupt!
    542       1.11       gwr 	 * Just set a "need load" bit and let the
    543       1.11       gwr 	 * retrace interrupt handler do the work.
    544       1.11       gwr 	 */
    545       1.14       gwr 	if (sc->sc_video_on) {
    546       1.14       gwr 		/* Update H/W colormap. */
    547       1.14       gwr 		for (i = 0; i < 256; i++) {
    548       1.14       gwr 			ar->r[i] = cm->r[i];
    549       1.14       gwr 			ar->g[i] = cm->g[i];
    550       1.14       gwr 			ar->b[i] = cm->b[i];
    551       1.14       gwr 		}
    552       1.14       gwr 	} else {
    553       1.14       gwr 		/* Clear H/W colormap. */
    554       1.11       gwr 		for (i = 0; i < 256; i++) {
    555       1.11       gwr 			ar->r[i] = 0;
    556       1.11       gwr 			ar->g[i] = 0;
    557       1.11       gwr 			ar->b[i] = 0;
    558       1.11       gwr 		}
    559        1.1       gwr 	}
    560       1.11       gwr }
    561       1.15       gwr #endif	/* SUN3 */
    562       1.11       gwr 
    563       1.11       gwr /****************************************************************
    564       1.11       gwr  * Routines for the "Type B" hardware
    565       1.11       gwr  ****************************************************************/
    566        1.1       gwr 
    567       1.32       chs static void
    568       1.32       chs cg4b_init(struct cg4_softc *sc)
    569       1.11       gwr {
    570       1.11       gwr 	volatile struct bt_regs *bt = sc->sc_va_cmap;
    571       1.11       gwr 	struct soft_cmap *cm = &sc->sc_cmap;
    572       1.18       gwr 	union bt_cmap_u *btcm;
    573       1.11       gwr 	int i;
    574       1.11       gwr 
    575       1.14       gwr 	/* Need a buffer for colormap format translation. */
    576       1.15       gwr 	btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK);
    577       1.14       gwr 	sc->sc_btcm = btcm;
    578       1.14       gwr 
    579       1.11       gwr 	/*
    580       1.11       gwr 	 * BT458 chip initialization as described in Brooktree's
    581       1.11       gwr 	 * 1993 Graphics and Imaging Product Databook (DB004-1/93).
    582       1.18       gwr 	 *
    583       1.18       gwr 	 * It appears that the 3/60 uses the low byte, and the 3/80
    584       1.18       gwr 	 * uses the high byte, while both ignore the other bytes.
    585       1.18       gwr 	 * Writing same value to all bytes works on both.
    586       1.18       gwr 	 */
    587       1.18       gwr 	bt->bt_addr = 0x04040404;	/* select read mask register */
    588       1.18       gwr 	bt->bt_ctrl = ~0;       	/* all planes on */
    589       1.18       gwr 	bt->bt_addr = 0x05050505;	/* select blink mask register */
    590       1.18       gwr 	bt->bt_ctrl = 0;        	/* all planes non-blinking */
    591       1.18       gwr 	bt->bt_addr = 0x06060606;	/* select command register */
    592       1.39   tsutsui 	bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */
    593       1.18       gwr 	bt->bt_addr = 0x07070707;	/* select test register */
    594       1.18       gwr 	bt->bt_ctrl = 0;        	/* not test mode */
    595       1.11       gwr 
    596       1.11       gwr 	/* grab initial (current) color map */
    597       1.11       gwr 	bt->bt_addr = 0;
    598       1.18       gwr #ifdef	_SUN3_
    599       1.18       gwr 	/* Sun3/60 wants 32-bit access, packed. */
    600       1.18       gwr 	for (i = 0; i < (256 * 3 / 4); i++)
    601       1.18       gwr 		btcm->btcm_int[i] = bt->bt_cmap;
    602       1.18       gwr #else	/* SUN3 */
    603       1.18       gwr 	/* Sun3/80 wants 8-bits in the high byte. */
    604       1.18       gwr 	for (i = 0; i < (256 * 3); i++)
    605       1.18       gwr 		btcm->btcm_char[i] = bt->bt_cmap >> 24;
    606       1.18       gwr #endif	/* SUN3 */
    607        1.1       gwr 
    608       1.14       gwr 	/* Transpose into H/W cmap into S/W form. */
    609       1.11       gwr 	for (i = 0; i < 256; i++) {
    610       1.18       gwr 		cm->r[i] = btcm->btcm_rgb[i][0];
    611       1.18       gwr 		cm->g[i] = btcm->btcm_rgb[i][1];
    612       1.18       gwr 		cm->b[i] = btcm->btcm_rgb[i][2];
    613        1.1       gwr 	}
    614        1.1       gwr }
    615        1.1       gwr 
    616       1.32       chs static void
    617       1.32       chs cg4b_ldcmap(struct cg4_softc *sc)
    618        1.1       gwr {
    619       1.11       gwr 	volatile struct bt_regs *bt = sc->sc_va_cmap;
    620       1.11       gwr 	struct soft_cmap *cm = &sc->sc_cmap;
    621       1.18       gwr 	union bt_cmap_u *btcm = sc->sc_btcm;
    622       1.11       gwr 	int i;
    623        1.1       gwr 
    624       1.14       gwr 	/* Transpose S/W cmap into H/W form. */
    625       1.14       gwr 	for (i = 0; i < 256; i++) {
    626       1.18       gwr 		btcm->btcm_rgb[i][0] = cm->r[i];
    627       1.18       gwr 		btcm->btcm_rgb[i][1] = cm->g[i];
    628       1.18       gwr 		btcm->btcm_rgb[i][2] = cm->b[i];
    629       1.14       gwr 	}
    630       1.14       gwr 
    631       1.11       gwr 	/*
    632       1.11       gwr 	 * Now blast them into the chip!
    633       1.11       gwr 	 * XXX Should use retrace interrupt!
    634       1.11       gwr 	 * Just set a "need load" bit and let the
    635       1.11       gwr 	 * retrace interrupt handler do the work.
    636       1.11       gwr 	 */
    637       1.11       gwr 	bt->bt_addr = 0;
    638       1.19       gwr 
    639       1.19       gwr #ifdef	_SUN3_
    640       1.19       gwr 	/* Sun3/60 wants 32-bit access, packed. */
    641       1.14       gwr 	if (sc->sc_video_on) {
    642       1.14       gwr 		/* Update H/W colormap. */
    643       1.14       gwr 		for (i = 0; i < (256 * 3 / 4); i++)
    644       1.18       gwr 			bt->bt_cmap = btcm->btcm_int[i];
    645       1.19       gwr 	} else {
    646       1.19       gwr 		/* Clear H/W colormap. */
    647       1.19       gwr 		for (i = 0; i < (256 * 3 / 4); i++)
    648       1.19       gwr 			bt->bt_cmap = 0;
    649       1.19       gwr 	}
    650       1.18       gwr #else	/* SUN3 */
    651       1.19       gwr 	/* Sun3/80 wants 8-bits in the high byte. */
    652       1.19       gwr 	if (sc->sc_video_on) {
    653       1.19       gwr 		/* Update H/W colormap. */
    654       1.18       gwr 		for (i = 0; i < (256 * 3); i++)
    655       1.18       gwr 			bt->bt_cmap = btcm->btcm_char[i] << 24;
    656       1.14       gwr 	} else {
    657       1.14       gwr 		/* Clear H/W colormap. */
    658       1.18       gwr 		for (i = 0; i < (256 * 3); i++)
    659       1.18       gwr 			bt->bt_cmap = 0;
    660       1.19       gwr 	}
    661       1.18       gwr #endif	/* SUN3 */
    662        1.1       gwr }
    663