cg4.c revision 1.21.4.3
1 /* $NetBSD: cg4.c,v 1.21.4.3 2002/06/28 08:22:32 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93 45 */ 46 47 /* 48 * color display (cg4) driver. 49 * 50 * Credits, history: 51 * Gordon Ross created this driver based on the cg3 driver from 52 * the sparc port as distributed in BSD 4.4 Lite, but included 53 * support for only the "type B" adapter (Brooktree DACs). 54 * Ezra Story added support for the "type A" (AMD DACs). 55 * 56 * Todo: 57 * Make this driver handle video interrupts. 58 * Defer colormap updates to vertical retrace interrupts. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/conf.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/malloc.h> 67 #include <sys/mman.h> 68 #include <sys/proc.h> 69 #include <sys/tty.h> 70 71 #include <uvm/uvm_extern.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/cpu.h> 75 #include <dev/sun/fbio.h> 76 #include <machine/idprom.h> 77 #include <machine/pmap.h> 78 79 #include <sun3/dev/fbvar.h> 80 #include <sun3/dev/btreg.h> 81 #include <sun3/dev/cg4reg.h> 82 #include <sun3/dev/p4reg.h> 83 84 union bt_cmap_u { 85 u_char btcm_char[256 * 3]; /* raw data */ 86 u_char btcm_rgb[256][3]; /* 256 R/G/B entries */ 87 u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */ 88 }; 89 90 #define CG4_TYPE_A 0 /* AMD DACs */ 91 #define CG4_TYPE_B 1 /* Brooktree DACs */ 92 93 cdev_decl(cg4); 94 95 #define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE) 96 97 #define CMAP_SIZE 256 98 struct soft_cmap { 99 u_char r[CMAP_SIZE]; 100 u_char g[CMAP_SIZE]; 101 u_char b[CMAP_SIZE]; 102 }; 103 104 /* per-display variables */ 105 struct cg4_softc { 106 struct device sc_dev; /* base device */ 107 struct fbdevice sc_fb; /* frame buffer device */ 108 int sc_cg4type; /* A or B */ 109 int sc_pa_overlay; /* phys. addr. of overlay plane */ 110 int sc_pa_enable; /* phys. addr. of enable plane */ 111 int sc_pa_pixmap; /* phys. addr. of color plane */ 112 int sc_video_on; /* zero if blanked */ 113 void *sc_va_cmap; /* Colormap h/w (mapped KVA) */ 114 void *sc_btcm; /* Soft cmap, Brooktree format */ 115 void (*sc_ldcmap) __P((struct cg4_softc *)); 116 struct soft_cmap sc_cmap; /* Soft cmap, user format */ 117 }; 118 119 /* autoconfiguration driver */ 120 static void cg4attach __P((struct device *, struct device *, void *)); 121 static int cg4match __P((struct device *, struct cfdata *, void *)); 122 123 struct cfattach cgfour_ca = { 124 sizeof(struct cg4_softc), cg4match, cg4attach 125 }; 126 127 extern struct cfdriver cgfour_cd; 128 129 static int cg4gattr __P((struct fbdevice *, void *)); 130 static int cg4gvideo __P((struct fbdevice *, void *)); 131 static int cg4svideo __P((struct fbdevice *, void *)); 132 static int cg4getcmap __P((struct fbdevice *, void *)); 133 static int cg4putcmap __P((struct fbdevice *, void *)); 134 135 #ifdef _SUN3_ 136 static void cg4a_init __P((struct cg4_softc *)); 137 static void cg4a_ldcmap __P((struct cg4_softc *)); 138 #endif /* SUN3 */ 139 140 static void cg4b_init __P((struct cg4_softc *)); 141 static void cg4b_ldcmap __P((struct cg4_softc *)); 142 143 static struct fbdriver cg4_fbdriver = { 144 cg4open, cg4close, cg4mmap, cg4kqfilter, cg4gattr, 145 cg4gvideo, cg4svideo, 146 cg4getcmap, cg4putcmap }; 147 148 /* 149 * Match a cg4. 150 */ 151 static int 152 cg4match(parent, cf, args) 153 struct device *parent; 154 struct cfdata *cf; 155 void *args; 156 { 157 struct confargs *ca = args; 158 int mid, p4id, peekval, tmp; 159 void *p4reg; 160 161 /* No default address support. */ 162 if (ca->ca_paddr == -1) 163 return (0); 164 165 /* 166 * Slight hack here: The low four bits of the 167 * config flags, if set, restrict the match to 168 * that machine "implementation" only. 169 */ 170 mid = cf->cf_flags & IDM_IMPL_MASK; 171 if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK))) 172 return (0); 173 174 /* 175 * The config flag 0x10 if set means we are 176 * looking for a Type A board (3/110). 177 */ 178 if (cf->cf_flags & 0x10) { 179 #ifdef _SUN3_ 180 /* Type A: Check for AMD RAMDACs in control space. */ 181 if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1) 182 return (0); 183 /* Check for the overlay plane. */ 184 tmp = ca->ca_paddr + CG4A_OFF_OVERLAY; 185 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 186 return (0); 187 /* OK, it looks like a Type A. */ 188 return (1); 189 #else /* SUN3 */ 190 /* Only the Sun3/110 ever has a type A. */ 191 return (0); 192 #endif /* SUN3 */ 193 } 194 195 /* 196 * From here on, it is a type B or nothing. 197 * The config flag 0x20 if set means there 198 * is no P4 register. (bus error) 199 */ 200 if ((cf->cf_flags & 0x20) == 0) { 201 p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr); 202 peekval = peek_long(p4reg); 203 p4id = (peekval == -1) ? 204 P4_NOTFOUND : fb_pfour_id(p4reg); 205 bus_tmapout(p4reg); 206 if (peekval == -1) 207 return (0); 208 if (p4id != P4_ID_COLOR8P1) { 209 #ifdef DEBUG 210 printf("cgfour at 0x%x match p4id=0x%x fails\n", 211 ca->ca_paddr, p4id & 0xFF); 212 #endif 213 return (0); 214 } 215 } 216 217 /* 218 * Check for CMAP hardware and overlay plane. 219 */ 220 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 221 if (bus_peek(ca->ca_bustype, tmp, 4) == -1) 222 return (0); 223 tmp = ca->ca_paddr + CG4B_OFF_OVERLAY; 224 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 225 return (0); 226 227 return (1); 228 } 229 230 /* 231 * Attach a display. We need to notice if it is the console, too. 232 */ 233 static void 234 cg4attach(parent, self, args) 235 struct device *parent, *self; 236 void *args; 237 { 238 struct cg4_softc *sc = (struct cg4_softc *)self; 239 struct fbdevice *fb = &sc->sc_fb; 240 struct confargs *ca = args; 241 struct fbtype *fbt; 242 int tmp; 243 244 fbt = &fb->fb_fbtype; 245 fbt->fb_type = FBTYPE_SUN4COLOR; 246 fbt->fb_width = 1152; /* default - see below */ 247 fbt->fb_height = 900; /* default - see below */ 248 fbt->fb_depth = 8; 249 fbt->fb_cmsize = 256; 250 fbt->fb_size = CG4_MMAP_SIZE; 251 fb->fb_driver = &cg4_fbdriver; 252 fb->fb_private = sc; 253 fb->fb_name = sc->sc_dev.dv_xname; 254 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags; 255 256 /* 257 * The config flag 0x10 if set means we are 258 * attaching a Type A (3/110) which has the 259 * AMD RAMDACs in control space, and no P4. 260 */ 261 if (fb->fb_flags & 0x10) { 262 #ifdef _SUN3_ 263 sc->sc_cg4type = CG4_TYPE_A; 264 sc->sc_ldcmap = cg4a_ldcmap; 265 sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY; 266 sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE; 267 sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP; 268 sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP, 269 sizeof(struct amd_regs)); 270 cg4a_init(sc); 271 #else /* SUN3 */ 272 panic("cgfour flags 0x10"); 273 #endif /* SUN3 */ 274 } else { 275 sc->sc_cg4type = CG4_TYPE_B; 276 sc->sc_ldcmap = cg4b_ldcmap; 277 sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY; 278 sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE; 279 sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP; 280 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 281 sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp, 282 sizeof(struct bt_regs)); 283 cg4b_init(sc); 284 } 285 286 if ((fb->fb_flags & 0x20) == 0) { 287 /* It is supposed to have a P4 register. */ 288 fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4); 289 } 290 291 /* 292 * Determine width and height as follows: 293 * If it has a P4 register, use that; 294 * else if unit==0, use the EEPROM size, 295 * else make our best guess. 296 */ 297 if (fb->fb_pfour) 298 fb_pfour_setsize(fb); 299 else if (sc->sc_dev.dv_unit == 0) 300 fb_eeprom_setsize(fb); 301 else { 302 /* Guess based on machine ID. */ 303 switch (cpu_machine_id) { 304 default: 305 /* Leave the defaults set above. */ 306 break; 307 } 308 } 309 printf(" (%dx%d)\n", fbt->fb_width, fbt->fb_height); 310 311 /* 312 * Make sure video is on. This driver uses a 313 * black colormap to blank the screen, so if 314 * there is any global enable, set it here. 315 */ 316 tmp = 1; 317 cg4svideo(fb, &tmp); 318 if (fb->fb_pfour) 319 fb_pfour_set_video(fb, 1); 320 else 321 enable_video(1); 322 323 /* Let /dev/fb know we are here. */ 324 fb_attach(fb, 4); 325 } 326 327 int 328 cg4open(dev, flags, mode, p) 329 dev_t dev; 330 int flags, mode; 331 struct proc *p; 332 { 333 int unit = minor(dev); 334 335 if (unit >= cgfour_cd.cd_ndevs || cgfour_cd.cd_devs[unit] == NULL) 336 return (ENXIO); 337 return (0); 338 } 339 340 int 341 cg4close(dev, flags, mode, p) 342 dev_t dev; 343 int flags, mode; 344 struct proc *p; 345 { 346 347 return (0); 348 } 349 350 int 351 cg4ioctl(dev, cmd, data, flags, p) 352 dev_t dev; 353 u_long cmd; 354 caddr_t data; 355 int flags; 356 struct proc *p; 357 { 358 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 359 360 return (fbioctlfb(&sc->sc_fb, cmd, data)); 361 } 362 363 /* 364 * Return the address that would map the given device at the given 365 * offset, allowing for the given protection, or return -1 for error. 366 * 367 * X11 expects its mmap'd region to look like this: 368 * 128k overlay data memory 369 * 128k overlay enable bitmap 370 * 1024k color memory 371 * 372 * The hardware looks completely different. 373 */ 374 paddr_t 375 cg4mmap(dev, off, prot) 376 dev_t dev; 377 off_t off; 378 int prot; 379 { 380 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 381 int physbase; 382 383 if (off & PGOFSET) 384 panic("cg4mmap"); 385 386 if ((off < 0) || (off >= CG4_MMAP_SIZE)) 387 return (-1); 388 389 if (off < 0x40000) { 390 if (off < 0x20000) { 391 physbase = sc->sc_pa_overlay; 392 } else { 393 /* enable plane */ 394 off -= 0x20000; 395 physbase = sc->sc_pa_enable; 396 } 397 } else { 398 /* pixel map */ 399 off -= 0x40000; 400 physbase = sc->sc_pa_pixmap; 401 } 402 403 /* 404 * I turned on PMAP_NC here to disable the cache as I was 405 * getting horribly broken behaviour without it. 406 */ 407 return ((physbase + off) | PMAP_NC); 408 } 409 410 static void 411 filt_cg4detach(struct knote *kn) 412 { 413 /* Nothing to do */ 414 } 415 416 static const struct filterops cg4_filtops = 417 { 1, NULL, filt_cg4detach, filt_seltrue }; 418 419 int 420 cg4kqfilter(dev_t dev, struct knote *kn) 421 { 422 switch (kn->kn_filter) { 423 case EVFILT_READ: 424 case EVFILT_WRITE: 425 kn->kn_fop = &cg4_filtops; 426 break; 427 default: 428 return (1); 429 } 430 431 /* Nothing more to do */ 432 return (0); 433 } 434 435 /* 436 * Internal ioctl functions. 437 */ 438 439 /* FBIOGATTR: */ 440 static int cg4gattr(fb, data) 441 struct fbdevice *fb; 442 void *data; 443 { 444 struct fbgattr *fba = data; 445 446 fba->real_type = fb->fb_fbtype.fb_type; 447 fba->owner = 0; /* XXX - TIOCCONS stuff? */ 448 fba->fbtype = fb->fb_fbtype; 449 fba->sattr.flags = 0; 450 fba->sattr.emu_type = fb->fb_fbtype.fb_type; 451 fba->sattr.dev_specific[0] = -1; 452 fba->emu_types[0] = fb->fb_fbtype.fb_type; 453 fba->emu_types[1] = -1; 454 return (0); 455 } 456 457 /* FBIOGVIDEO: */ 458 static int cg4gvideo(fb, data) 459 struct fbdevice *fb; 460 void *data; 461 { 462 struct cg4_softc *sc = fb->fb_private; 463 int *on = data; 464 465 *on = sc->sc_video_on; 466 return (0); 467 } 468 469 /* FBIOSVIDEO: */ 470 static int cg4svideo(fb, data) 471 struct fbdevice *fb; 472 void *data; 473 { 474 struct cg4_softc *sc = fb->fb_private; 475 int *on = data; 476 477 if (sc->sc_video_on == *on) 478 return (0); 479 sc->sc_video_on = *on; 480 481 (*sc->sc_ldcmap)(sc); 482 return (0); 483 } 484 485 /* 486 * FBIOGETCMAP: 487 * Copy current colormap out to user space. 488 */ 489 static int cg4getcmap(fb, data) 490 struct fbdevice *fb; 491 void *data; 492 { 493 struct cg4_softc *sc = fb->fb_private; 494 struct soft_cmap *cm = &sc->sc_cmap; 495 struct fbcmap *fbcm = data; 496 int error, start, count; 497 498 start = fbcm->index; 499 count = fbcm->count; 500 if ((start < 0) || (start >= CMAP_SIZE) || 501 (count < 0) || (start + count > CMAP_SIZE) ) 502 return (EINVAL); 503 504 if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0) 505 return (error); 506 507 if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0) 508 return (error); 509 510 if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0) 511 return (error); 512 513 return (0); 514 } 515 516 /* 517 * FBIOPUTCMAP: 518 * Copy new colormap from user space and load. 519 */ 520 static int cg4putcmap(fb, data) 521 struct fbdevice *fb; 522 void *data; 523 { 524 struct cg4_softc *sc = fb->fb_private; 525 struct soft_cmap *cm = &sc->sc_cmap; 526 struct fbcmap *fbcm = data; 527 int error, start, count; 528 529 start = fbcm->index; 530 count = fbcm->count; 531 if ((start < 0) || (start >= CMAP_SIZE) || 532 (count < 0) || (start + count > CMAP_SIZE) ) 533 return (EINVAL); 534 535 if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0) 536 return (error); 537 538 if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0) 539 return (error); 540 541 if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0) 542 return (error); 543 544 (*sc->sc_ldcmap)(sc); 545 return (0); 546 } 547 548 /**************************************************************** 549 * Routines for the "Type A" hardware 550 ****************************************************************/ 551 #ifdef _SUN3_ 552 553 static void 554 cg4a_init(sc) 555 struct cg4_softc *sc; 556 { 557 volatile struct amd_regs *ar = sc->sc_va_cmap; 558 struct soft_cmap *cm = &sc->sc_cmap; 559 int i; 560 561 /* Grab initial (current) color map. */ 562 for(i = 0; i < 256; i++) { 563 cm->r[i] = ar->r[i]; 564 cm->g[i] = ar->g[i]; 565 cm->b[i] = ar->b[i]; 566 } 567 } 568 569 static void 570 cg4a_ldcmap(sc) 571 struct cg4_softc *sc; 572 { 573 volatile struct amd_regs *ar = sc->sc_va_cmap; 574 struct soft_cmap *cm = &sc->sc_cmap; 575 int i; 576 577 /* 578 * Now blast them into the chip! 579 * XXX Should use retrace interrupt! 580 * Just set a "need load" bit and let the 581 * retrace interrupt handler do the work. 582 */ 583 if (sc->sc_video_on) { 584 /* Update H/W colormap. */ 585 for (i = 0; i < 256; i++) { 586 ar->r[i] = cm->r[i]; 587 ar->g[i] = cm->g[i]; 588 ar->b[i] = cm->b[i]; 589 } 590 } else { 591 /* Clear H/W colormap. */ 592 for (i = 0; i < 256; i++) { 593 ar->r[i] = 0; 594 ar->g[i] = 0; 595 ar->b[i] = 0; 596 } 597 } 598 } 599 #endif /* SUN3 */ 600 601 /**************************************************************** 602 * Routines for the "Type B" hardware 603 ****************************************************************/ 604 605 static void 606 cg4b_init(sc) 607 struct cg4_softc *sc; 608 { 609 volatile struct bt_regs *bt = sc->sc_va_cmap; 610 struct soft_cmap *cm = &sc->sc_cmap; 611 union bt_cmap_u *btcm; 612 int i; 613 614 /* Need a buffer for colormap format translation. */ 615 btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK); 616 sc->sc_btcm = btcm; 617 618 /* 619 * BT458 chip initialization as described in Brooktree's 620 * 1993 Graphics and Imaging Product Databook (DB004-1/93). 621 * 622 * It appears that the 3/60 uses the low byte, and the 3/80 623 * uses the high byte, while both ignore the other bytes. 624 * Writing same value to all bytes works on both. 625 */ 626 bt->bt_addr = 0x04040404; /* select read mask register */ 627 bt->bt_ctrl = ~0; /* all planes on */ 628 bt->bt_addr = 0x05050505; /* select blink mask register */ 629 bt->bt_ctrl = 0; /* all planes non-blinking */ 630 bt->bt_addr = 0x06060606; /* select command register */ 631 bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */ 632 bt->bt_addr = 0x07070707; /* select test register */ 633 bt->bt_ctrl = 0; /* not test mode */ 634 635 /* grab initial (current) color map */ 636 bt->bt_addr = 0; 637 #ifdef _SUN3_ 638 /* Sun3/60 wants 32-bit access, packed. */ 639 for (i = 0; i < (256 * 3 / 4); i++) 640 btcm->btcm_int[i] = bt->bt_cmap; 641 #else /* SUN3 */ 642 /* Sun3/80 wants 8-bits in the high byte. */ 643 for (i = 0; i < (256 * 3); i++) 644 btcm->btcm_char[i] = bt->bt_cmap >> 24; 645 #endif /* SUN3 */ 646 647 /* Transpose into H/W cmap into S/W form. */ 648 for (i = 0; i < 256; i++) { 649 cm->r[i] = btcm->btcm_rgb[i][0]; 650 cm->g[i] = btcm->btcm_rgb[i][1]; 651 cm->b[i] = btcm->btcm_rgb[i][2]; 652 } 653 } 654 655 static void 656 cg4b_ldcmap(sc) 657 struct cg4_softc *sc; 658 { 659 volatile struct bt_regs *bt = sc->sc_va_cmap; 660 struct soft_cmap *cm = &sc->sc_cmap; 661 union bt_cmap_u *btcm = sc->sc_btcm; 662 int i; 663 664 /* Transpose S/W cmap into H/W form. */ 665 for (i = 0; i < 256; i++) { 666 btcm->btcm_rgb[i][0] = cm->r[i]; 667 btcm->btcm_rgb[i][1] = cm->g[i]; 668 btcm->btcm_rgb[i][2] = cm->b[i]; 669 } 670 671 /* 672 * Now blast them into the chip! 673 * XXX Should use retrace interrupt! 674 * Just set a "need load" bit and let the 675 * retrace interrupt handler do the work. 676 */ 677 bt->bt_addr = 0; 678 679 #ifdef _SUN3_ 680 /* Sun3/60 wants 32-bit access, packed. */ 681 if (sc->sc_video_on) { 682 /* Update H/W colormap. */ 683 for (i = 0; i < (256 * 3 / 4); i++) 684 bt->bt_cmap = btcm->btcm_int[i]; 685 } else { 686 /* Clear H/W colormap. */ 687 for (i = 0; i < (256 * 3 / 4); i++) 688 bt->bt_cmap = 0; 689 } 690 #else /* SUN3 */ 691 /* Sun3/80 wants 8-bits in the high byte. */ 692 if (sc->sc_video_on) { 693 /* Update H/W colormap. */ 694 for (i = 0; i < (256 * 3); i++) 695 bt->bt_cmap = btcm->btcm_char[i] << 24; 696 } else { 697 /* Clear H/W colormap. */ 698 for (i = 0; i < (256 * 3); i++) 699 bt->bt_cmap = 0; 700 } 701 #endif /* SUN3 */ 702 } 703 704
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