cg4.c revision 1.22.2.2
1 /* $NetBSD: cg4.c,v 1.22.2.2 2001/10/10 11:56:37 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93 45 */ 46 47 /* 48 * color display (cg4) driver. 49 * 50 * Credits, history: 51 * Gordon Ross created this driver based on the cg3 driver from 52 * the sparc port as distributed in BSD 4.4 Lite, but included 53 * support for only the "type B" adapter (Brooktree DACs). 54 * Ezra Story added support for the "type A" (AMD DACs). 55 * 56 * Todo: 57 * Make this driver handle video interrupts. 58 * Defer colormap updates to vertical retrace interrupts. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/conf.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/malloc.h> 67 #include <sys/mman.h> 68 #include <sys/proc.h> 69 #include <sys/tty.h> 70 #include <sys/vnode.h> 71 72 #include <uvm/uvm_extern.h> 73 74 #include <machine/autoconf.h> 75 #include <machine/cpu.h> 76 #include <dev/sun/fbio.h> 77 #include <machine/idprom.h> 78 #include <machine/pmap.h> 79 80 #include <sun3/dev/fbvar.h> 81 #include <sun3/dev/btreg.h> 82 #include <sun3/dev/cg4reg.h> 83 #include <sun3/dev/p4reg.h> 84 85 union bt_cmap_u { 86 u_char btcm_char[256 * 3]; /* raw data */ 87 u_char btcm_rgb[256][3]; /* 256 R/G/B entries */ 88 u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */ 89 }; 90 91 #define CG4_TYPE_A 0 /* AMD DACs */ 92 #define CG4_TYPE_B 1 /* Brooktree DACs */ 93 94 cdev_decl(cg4); 95 96 #define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE) 97 98 #define CMAP_SIZE 256 99 struct soft_cmap { 100 u_char r[CMAP_SIZE]; 101 u_char g[CMAP_SIZE]; 102 u_char b[CMAP_SIZE]; 103 }; 104 105 /* per-display variables */ 106 struct cg4_softc { 107 struct device sc_dev; /* base device */ 108 struct fbdevice sc_fb; /* frame buffer device */ 109 int sc_cg4type; /* A or B */ 110 int sc_pa_overlay; /* phys. addr. of overlay plane */ 111 int sc_pa_enable; /* phys. addr. of enable plane */ 112 int sc_pa_pixmap; /* phys. addr. of color plane */ 113 int sc_video_on; /* zero if blanked */ 114 void *sc_va_cmap; /* Colormap h/w (mapped KVA) */ 115 void *sc_btcm; /* Soft cmap, Brooktree format */ 116 void (*sc_ldcmap) __P((struct cg4_softc *)); 117 struct soft_cmap sc_cmap; /* Soft cmap, user format */ 118 }; 119 120 /* autoconfiguration driver */ 121 static void cg4attach __P((struct device *, struct device *, void *)); 122 static int cg4match __P((struct device *, struct cfdata *, void *)); 123 124 struct cfattach cgfour_ca = { 125 sizeof(struct cg4_softc), cg4match, cg4attach 126 }; 127 128 extern struct cfdriver cgfour_cd; 129 130 static int cg4gattr __P((struct fbdevice *, void *)); 131 static int cg4gvideo __P((struct fbdevice *, void *)); 132 static int cg4svideo __P((struct fbdevice *, void *)); 133 static int cg4getcmap __P((struct fbdevice *, void *)); 134 static int cg4putcmap __P((struct fbdevice *, void *)); 135 136 #ifdef _SUN3_ 137 static void cg4a_init __P((struct cg4_softc *)); 138 static void cg4a_ldcmap __P((struct cg4_softc *)); 139 #endif /* SUN3 */ 140 141 static void cg4b_init __P((struct cg4_softc *)); 142 static void cg4b_ldcmap __P((struct cg4_softc *)); 143 144 static struct fbdriver cg4_fbdriver = { 145 cg4open, cg4close, cg4mmap, cg4gattr, 146 cg4gvideo, cg4svideo, 147 cg4getcmap, cg4putcmap }; 148 149 /* 150 * Match a cg4. 151 */ 152 static int 153 cg4match(parent, cf, args) 154 struct device *parent; 155 struct cfdata *cf; 156 void *args; 157 { 158 struct confargs *ca = args; 159 int mid, p4id, peekval, tmp; 160 void *p4reg; 161 162 /* No default address support. */ 163 if (ca->ca_paddr == -1) 164 return (0); 165 166 /* 167 * Slight hack here: The low four bits of the 168 * config flags, if set, restrict the match to 169 * that machine "implementation" only. 170 */ 171 mid = cf->cf_flags & IDM_IMPL_MASK; 172 if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK))) 173 return (0); 174 175 /* 176 * The config flag 0x10 if set means we are 177 * looking for a Type A board (3/110). 178 */ 179 if (cf->cf_flags & 0x10) { 180 #ifdef _SUN3_ 181 /* Type A: Check for AMD RAMDACs in control space. */ 182 if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1) 183 return (0); 184 /* Check for the overlay plane. */ 185 tmp = ca->ca_paddr + CG4A_OFF_OVERLAY; 186 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 187 return (0); 188 /* OK, it looks like a Type A. */ 189 return (1); 190 #else /* SUN3 */ 191 /* Only the Sun3/110 ever has a type A. */ 192 return (0); 193 #endif /* SUN3 */ 194 } 195 196 /* 197 * From here on, it is a type B or nothing. 198 * The config flag 0x20 if set means there 199 * is no P4 register. (bus error) 200 */ 201 if ((cf->cf_flags & 0x20) == 0) { 202 p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr); 203 peekval = peek_long(p4reg); 204 p4id = (peekval == -1) ? 205 P4_NOTFOUND : fb_pfour_id(p4reg); 206 bus_tmapout(p4reg); 207 if (peekval == -1) 208 return (0); 209 if (p4id != P4_ID_COLOR8P1) { 210 #ifdef DEBUG 211 printf("cgfour at 0x%x match p4id=0x%x fails\n", 212 ca->ca_paddr, p4id & 0xFF); 213 #endif 214 return (0); 215 } 216 } 217 218 /* 219 * Check for CMAP hardware and overlay plane. 220 */ 221 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 222 if (bus_peek(ca->ca_bustype, tmp, 4) == -1) 223 return (0); 224 tmp = ca->ca_paddr + CG4B_OFF_OVERLAY; 225 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 226 return (0); 227 228 return (1); 229 } 230 231 /* 232 * Attach a display. We need to notice if it is the console, too. 233 */ 234 static void 235 cg4attach(parent, self, args) 236 struct device *parent, *self; 237 void *args; 238 { 239 struct cg4_softc *sc = (struct cg4_softc *)self; 240 struct fbdevice *fb = &sc->sc_fb; 241 struct confargs *ca = args; 242 struct fbtype *fbt; 243 int tmp; 244 245 fbt = &fb->fb_fbtype; 246 fbt->fb_type = FBTYPE_SUN4COLOR; 247 fbt->fb_width = 1152; /* default - see below */ 248 fbt->fb_height = 900; /* default - see below */ 249 fbt->fb_depth = 8; 250 fbt->fb_cmsize = 256; 251 fbt->fb_size = CG4_MMAP_SIZE; 252 fb->fb_driver = &cg4_fbdriver; 253 fb->fb_private = sc; 254 fb->fb_name = sc->sc_dev.dv_xname; 255 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags; 256 257 /* 258 * The config flag 0x10 if set means we are 259 * attaching a Type A (3/110) which has the 260 * AMD RAMDACs in control space, and no P4. 261 */ 262 if (fb->fb_flags & 0x10) { 263 #ifdef _SUN3_ 264 sc->sc_cg4type = CG4_TYPE_A; 265 sc->sc_ldcmap = cg4a_ldcmap; 266 sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY; 267 sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE; 268 sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP; 269 sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP, 270 sizeof(struct amd_regs)); 271 cg4a_init(sc); 272 #else /* SUN3 */ 273 panic("cgfour flags 0x10"); 274 #endif /* SUN3 */ 275 } else { 276 sc->sc_cg4type = CG4_TYPE_B; 277 sc->sc_ldcmap = cg4b_ldcmap; 278 sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY; 279 sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE; 280 sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP; 281 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 282 sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp, 283 sizeof(struct bt_regs)); 284 cg4b_init(sc); 285 } 286 287 if ((fb->fb_flags & 0x20) == 0) { 288 /* It is supposed to have a P4 register. */ 289 fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4); 290 } 291 292 /* 293 * Determine width and height as follows: 294 * If it has a P4 register, use that; 295 * else if unit==0, use the EEPROM size, 296 * else make our best guess. 297 */ 298 if (fb->fb_pfour) 299 fb_pfour_setsize(fb); 300 else if (sc->sc_dev.dv_unit == 0) 301 fb_eeprom_setsize(fb); 302 else { 303 /* Guess based on machine ID. */ 304 switch (cpu_machine_id) { 305 default: 306 /* Leave the defaults set above. */ 307 break; 308 } 309 } 310 printf(" (%dx%d)\n", fbt->fb_width, fbt->fb_height); 311 312 /* 313 * Make sure video is on. This driver uses a 314 * black colormap to blank the screen, so if 315 * there is any global enable, set it here. 316 */ 317 tmp = 1; 318 cg4svideo(fb, &tmp); 319 if (fb->fb_pfour) 320 fb_pfour_set_video(fb, 1); 321 else 322 enable_video(1); 323 324 /* Let /dev/fb know we are here. */ 325 fb_attach(fb, 4); 326 } 327 328 int 329 cg4open(devvp, flags, mode, p) 330 struct vnode *devvp; 331 int flags, mode; 332 struct proc *p; 333 { 334 dev_t dev = vdev_rdev(devvp); 335 int unit = minor(dev); 336 337 if (unit >= cgfour_cd.cd_ndevs || cgfour_cd.cd_devs[unit] == NULL) 338 return (ENXIO); 339 vdev_setprivdata(devvp, cgfour_cd.cd_devs[unit]); 340 return (0); 341 } 342 343 int 344 cg4close(devvp, flags, mode, p) 345 struct vnode *devvp; 346 int flags, mode; 347 struct proc *p; 348 { 349 350 return (0); 351 } 352 353 int 354 cg4ioctl(devvp, cmd, data, flags, p) 355 struct vnode *devvp; 356 u_long cmd; 357 caddr_t data; 358 int flags; 359 struct proc *p; 360 { 361 struct cg4_softc *sc = vdev_privdata(devvp); 362 363 return (fbioctlfb(&sc->sc_fb, cmd, data)); 364 } 365 366 /* 367 * Return the address that would map the given device at the given 368 * offset, allowing for the given protection, or return -1 for error. 369 * 370 * X11 expects its mmap'd region to look like this: 371 * 128k overlay data memory 372 * 128k overlay enable bitmap 373 * 1024k color memory 374 * 375 * The hardware looks completely different. 376 */ 377 paddr_t 378 cg4mmap(devvp, off, prot) 379 struct vnode *devvp; 380 off_t off; 381 int prot; 382 { 383 struct cg4_softc *sc = vdev_privdata(devvp); 384 int physbase; 385 386 if (off & PGOFSET) 387 panic("cg4mmap"); 388 389 if ((off < 0) || (off >= CG4_MMAP_SIZE)) 390 return (-1); 391 392 if (off < 0x40000) { 393 if (off < 0x20000) { 394 physbase = sc->sc_pa_overlay; 395 } else { 396 /* enable plane */ 397 off -= 0x20000; 398 physbase = sc->sc_pa_enable; 399 } 400 } else { 401 /* pixel map */ 402 off -= 0x40000; 403 physbase = sc->sc_pa_pixmap; 404 } 405 406 /* 407 * I turned on PMAP_NC here to disable the cache as I was 408 * getting horribly broken behaviour without it. 409 */ 410 return ((physbase + off) | PMAP_NC); 411 } 412 413 /* 414 * Internal ioctl functions. 415 */ 416 417 /* FBIOGATTR: */ 418 static int cg4gattr(fb, data) 419 struct fbdevice *fb; 420 void *data; 421 { 422 struct fbgattr *fba = data; 423 424 fba->real_type = fb->fb_fbtype.fb_type; 425 fba->owner = 0; /* XXX - TIOCCONS stuff? */ 426 fba->fbtype = fb->fb_fbtype; 427 fba->sattr.flags = 0; 428 fba->sattr.emu_type = fb->fb_fbtype.fb_type; 429 fba->sattr.dev_specific[0] = -1; 430 fba->emu_types[0] = fb->fb_fbtype.fb_type; 431 fba->emu_types[1] = -1; 432 return (0); 433 } 434 435 /* FBIOGVIDEO: */ 436 static int cg4gvideo(fb, data) 437 struct fbdevice *fb; 438 void *data; 439 { 440 struct cg4_softc *sc = fb->fb_private; 441 int *on = data; 442 443 *on = sc->sc_video_on; 444 return (0); 445 } 446 447 /* FBIOSVIDEO: */ 448 static int cg4svideo(fb, data) 449 struct fbdevice *fb; 450 void *data; 451 { 452 struct cg4_softc *sc = fb->fb_private; 453 int *on = data; 454 455 if (sc->sc_video_on == *on) 456 return (0); 457 sc->sc_video_on = *on; 458 459 (*sc->sc_ldcmap)(sc); 460 return (0); 461 } 462 463 /* 464 * FBIOGETCMAP: 465 * Copy current colormap out to user space. 466 */ 467 static int cg4getcmap(fb, data) 468 struct fbdevice *fb; 469 void *data; 470 { 471 struct cg4_softc *sc = fb->fb_private; 472 struct soft_cmap *cm = &sc->sc_cmap; 473 struct fbcmap *fbcm = data; 474 int error, start, count; 475 476 start = fbcm->index; 477 count = fbcm->count; 478 if ((start < 0) || (start >= CMAP_SIZE) || 479 (count < 0) || (start + count > CMAP_SIZE) ) 480 return (EINVAL); 481 482 if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0) 483 return (error); 484 485 if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0) 486 return (error); 487 488 if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0) 489 return (error); 490 491 return (0); 492 } 493 494 /* 495 * FBIOPUTCMAP: 496 * Copy new colormap from user space and load. 497 */ 498 static int cg4putcmap(fb, data) 499 struct fbdevice *fb; 500 void *data; 501 { 502 struct cg4_softc *sc = fb->fb_private; 503 struct soft_cmap *cm = &sc->sc_cmap; 504 struct fbcmap *fbcm = data; 505 int error, start, count; 506 507 start = fbcm->index; 508 count = fbcm->count; 509 if ((start < 0) || (start >= CMAP_SIZE) || 510 (count < 0) || (start + count > CMAP_SIZE) ) 511 return (EINVAL); 512 513 if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0) 514 return (error); 515 516 if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0) 517 return (error); 518 519 if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0) 520 return (error); 521 522 (*sc->sc_ldcmap)(sc); 523 return (0); 524 } 525 526 /**************************************************************** 527 * Routines for the "Type A" hardware 528 ****************************************************************/ 529 #ifdef _SUN3_ 530 531 static void 532 cg4a_init(sc) 533 struct cg4_softc *sc; 534 { 535 volatile struct amd_regs *ar = sc->sc_va_cmap; 536 struct soft_cmap *cm = &sc->sc_cmap; 537 int i; 538 539 /* Grab initial (current) color map. */ 540 for(i = 0; i < 256; i++) { 541 cm->r[i] = ar->r[i]; 542 cm->g[i] = ar->g[i]; 543 cm->b[i] = ar->b[i]; 544 } 545 } 546 547 static void 548 cg4a_ldcmap(sc) 549 struct cg4_softc *sc; 550 { 551 volatile struct amd_regs *ar = sc->sc_va_cmap; 552 struct soft_cmap *cm = &sc->sc_cmap; 553 int i; 554 555 /* 556 * Now blast them into the chip! 557 * XXX Should use retrace interrupt! 558 * Just set a "need load" bit and let the 559 * retrace interrupt handler do the work. 560 */ 561 if (sc->sc_video_on) { 562 /* Update H/W colormap. */ 563 for (i = 0; i < 256; i++) { 564 ar->r[i] = cm->r[i]; 565 ar->g[i] = cm->g[i]; 566 ar->b[i] = cm->b[i]; 567 } 568 } else { 569 /* Clear H/W colormap. */ 570 for (i = 0; i < 256; i++) { 571 ar->r[i] = 0; 572 ar->g[i] = 0; 573 ar->b[i] = 0; 574 } 575 } 576 } 577 #endif /* SUN3 */ 578 579 /**************************************************************** 580 * Routines for the "Type B" hardware 581 ****************************************************************/ 582 583 static void 584 cg4b_init(sc) 585 struct cg4_softc *sc; 586 { 587 volatile struct bt_regs *bt = sc->sc_va_cmap; 588 struct soft_cmap *cm = &sc->sc_cmap; 589 union bt_cmap_u *btcm; 590 int i; 591 592 /* Need a buffer for colormap format translation. */ 593 btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK); 594 sc->sc_btcm = btcm; 595 596 /* 597 * BT458 chip initialization as described in Brooktree's 598 * 1993 Graphics and Imaging Product Databook (DB004-1/93). 599 * 600 * It appears that the 3/60 uses the low byte, and the 3/80 601 * uses the high byte, while both ignore the other bytes. 602 * Writing same value to all bytes works on both. 603 */ 604 bt->bt_addr = 0x04040404; /* select read mask register */ 605 bt->bt_ctrl = ~0; /* all planes on */ 606 bt->bt_addr = 0x05050505; /* select blink mask register */ 607 bt->bt_ctrl = 0; /* all planes non-blinking */ 608 bt->bt_addr = 0x06060606; /* select command register */ 609 bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */ 610 bt->bt_addr = 0x07070707; /* select test register */ 611 bt->bt_ctrl = 0; /* not test mode */ 612 613 /* grab initial (current) color map */ 614 bt->bt_addr = 0; 615 #ifdef _SUN3_ 616 /* Sun3/60 wants 32-bit access, packed. */ 617 for (i = 0; i < (256 * 3 / 4); i++) 618 btcm->btcm_int[i] = bt->bt_cmap; 619 #else /* SUN3 */ 620 /* Sun3/80 wants 8-bits in the high byte. */ 621 for (i = 0; i < (256 * 3); i++) 622 btcm->btcm_char[i] = bt->bt_cmap >> 24; 623 #endif /* SUN3 */ 624 625 /* Transpose into H/W cmap into S/W form. */ 626 for (i = 0; i < 256; i++) { 627 cm->r[i] = btcm->btcm_rgb[i][0]; 628 cm->g[i] = btcm->btcm_rgb[i][1]; 629 cm->b[i] = btcm->btcm_rgb[i][2]; 630 } 631 } 632 633 static void 634 cg4b_ldcmap(sc) 635 struct cg4_softc *sc; 636 { 637 volatile struct bt_regs *bt = sc->sc_va_cmap; 638 struct soft_cmap *cm = &sc->sc_cmap; 639 union bt_cmap_u *btcm = sc->sc_btcm; 640 int i; 641 642 /* Transpose S/W cmap into H/W form. */ 643 for (i = 0; i < 256; i++) { 644 btcm->btcm_rgb[i][0] = cm->r[i]; 645 btcm->btcm_rgb[i][1] = cm->g[i]; 646 btcm->btcm_rgb[i][2] = cm->b[i]; 647 } 648 649 /* 650 * Now blast them into the chip! 651 * XXX Should use retrace interrupt! 652 * Just set a "need load" bit and let the 653 * retrace interrupt handler do the work. 654 */ 655 bt->bt_addr = 0; 656 657 #ifdef _SUN3_ 658 /* Sun3/60 wants 32-bit access, packed. */ 659 if (sc->sc_video_on) { 660 /* Update H/W colormap. */ 661 for (i = 0; i < (256 * 3 / 4); i++) 662 bt->bt_cmap = btcm->btcm_int[i]; 663 } else { 664 /* Clear H/W colormap. */ 665 for (i = 0; i < (256 * 3 / 4); i++) 666 bt->bt_cmap = 0; 667 } 668 #else /* SUN3 */ 669 /* Sun3/80 wants 8-bits in the high byte. */ 670 if (sc->sc_video_on) { 671 /* Update H/W colormap. */ 672 for (i = 0; i < (256 * 3); i++) 673 bt->bt_cmap = btcm->btcm_char[i] << 24; 674 } else { 675 /* Clear H/W colormap. */ 676 for (i = 0; i < (256 * 3); i++) 677 bt->bt_cmap = 0; 678 } 679 #endif /* SUN3 */ 680 } 681 682
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