cg4.c revision 1.25
1 /* $NetBSD: cg4.c,v 1.25 2002/09/06 13:18:43 gehenna Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93 45 */ 46 47 /* 48 * color display (cg4) driver. 49 * 50 * Credits, history: 51 * Gordon Ross created this driver based on the cg3 driver from 52 * the sparc port as distributed in BSD 4.4 Lite, but included 53 * support for only the "type B" adapter (Brooktree DACs). 54 * Ezra Story added support for the "type A" (AMD DACs). 55 * 56 * Todo: 57 * Make this driver handle video interrupts. 58 * Defer colormap updates to vertical retrace interrupts. 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/conf.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/malloc.h> 67 #include <sys/mman.h> 68 #include <sys/proc.h> 69 #include <sys/tty.h> 70 71 #include <uvm/uvm_extern.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/cpu.h> 75 #include <dev/sun/fbio.h> 76 #include <machine/idprom.h> 77 #include <machine/pmap.h> 78 79 #include <sun3/dev/fbvar.h> 80 #include <sun3/dev/btreg.h> 81 #include <sun3/dev/cg4reg.h> 82 #include <sun3/dev/p4reg.h> 83 84 union bt_cmap_u { 85 u_char btcm_char[256 * 3]; /* raw data */ 86 u_char btcm_rgb[256][3]; /* 256 R/G/B entries */ 87 u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */ 88 }; 89 90 #define CG4_TYPE_A 0 /* AMD DACs */ 91 #define CG4_TYPE_B 1 /* Brooktree DACs */ 92 93 #define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE) 94 95 #define CMAP_SIZE 256 96 struct soft_cmap { 97 u_char r[CMAP_SIZE]; 98 u_char g[CMAP_SIZE]; 99 u_char b[CMAP_SIZE]; 100 }; 101 102 /* per-display variables */ 103 struct cg4_softc { 104 struct device sc_dev; /* base device */ 105 struct fbdevice sc_fb; /* frame buffer device */ 106 int sc_cg4type; /* A or B */ 107 int sc_pa_overlay; /* phys. addr. of overlay plane */ 108 int sc_pa_enable; /* phys. addr. of enable plane */ 109 int sc_pa_pixmap; /* phys. addr. of color plane */ 110 int sc_video_on; /* zero if blanked */ 111 void *sc_va_cmap; /* Colormap h/w (mapped KVA) */ 112 void *sc_btcm; /* Soft cmap, Brooktree format */ 113 void (*sc_ldcmap) __P((struct cg4_softc *)); 114 struct soft_cmap sc_cmap; /* Soft cmap, user format */ 115 }; 116 117 /* autoconfiguration driver */ 118 static void cg4attach __P((struct device *, struct device *, void *)); 119 static int cg4match __P((struct device *, struct cfdata *, void *)); 120 121 struct cfattach cgfour_ca = { 122 sizeof(struct cg4_softc), cg4match, cg4attach 123 }; 124 125 extern struct cfdriver cgfour_cd; 126 127 dev_type_open(cg4open); 128 dev_type_ioctl(cg4ioctl); 129 dev_type_mmap(cg4mmap); 130 131 const struct cdevsw cgfour_cdevsw = { 132 cg4open, nullclose, noread, nowrite, cg4ioctl, 133 nostop, notty, nopoll, cg4mmap, 134 }; 135 136 static int cg4gattr __P((struct fbdevice *, void *)); 137 static int cg4gvideo __P((struct fbdevice *, void *)); 138 static int cg4svideo __P((struct fbdevice *, void *)); 139 static int cg4getcmap __P((struct fbdevice *, void *)); 140 static int cg4putcmap __P((struct fbdevice *, void *)); 141 142 #ifdef _SUN3_ 143 static void cg4a_init __P((struct cg4_softc *)); 144 static void cg4a_ldcmap __P((struct cg4_softc *)); 145 #endif /* SUN3 */ 146 147 static void cg4b_init __P((struct cg4_softc *)); 148 static void cg4b_ldcmap __P((struct cg4_softc *)); 149 150 static struct fbdriver cg4_fbdriver = { 151 cg4open, nullclose, cg4mmap, cg4gattr, 152 cg4gvideo, cg4svideo, 153 cg4getcmap, cg4putcmap }; 154 155 /* 156 * Match a cg4. 157 */ 158 static int 159 cg4match(parent, cf, args) 160 struct device *parent; 161 struct cfdata *cf; 162 void *args; 163 { 164 struct confargs *ca = args; 165 int mid, p4id, peekval, tmp; 166 void *p4reg; 167 168 /* No default address support. */ 169 if (ca->ca_paddr == -1) 170 return (0); 171 172 /* 173 * Slight hack here: The low four bits of the 174 * config flags, if set, restrict the match to 175 * that machine "implementation" only. 176 */ 177 mid = cf->cf_flags & IDM_IMPL_MASK; 178 if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK))) 179 return (0); 180 181 /* 182 * The config flag 0x10 if set means we are 183 * looking for a Type A board (3/110). 184 */ 185 if (cf->cf_flags & 0x10) { 186 #ifdef _SUN3_ 187 /* Type A: Check for AMD RAMDACs in control space. */ 188 if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1) 189 return (0); 190 /* Check for the overlay plane. */ 191 tmp = ca->ca_paddr + CG4A_OFF_OVERLAY; 192 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 193 return (0); 194 /* OK, it looks like a Type A. */ 195 return (1); 196 #else /* SUN3 */ 197 /* Only the Sun3/110 ever has a type A. */ 198 return (0); 199 #endif /* SUN3 */ 200 } 201 202 /* 203 * From here on, it is a type B or nothing. 204 * The config flag 0x20 if set means there 205 * is no P4 register. (bus error) 206 */ 207 if ((cf->cf_flags & 0x20) == 0) { 208 p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr); 209 peekval = peek_long(p4reg); 210 p4id = (peekval == -1) ? 211 P4_NOTFOUND : fb_pfour_id(p4reg); 212 bus_tmapout(p4reg); 213 if (peekval == -1) 214 return (0); 215 if (p4id != P4_ID_COLOR8P1) { 216 #ifdef DEBUG 217 printf("cgfour at 0x%x match p4id=0x%x fails\n", 218 ca->ca_paddr, p4id & 0xFF); 219 #endif 220 return (0); 221 } 222 } 223 224 /* 225 * Check for CMAP hardware and overlay plane. 226 */ 227 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 228 if (bus_peek(ca->ca_bustype, tmp, 4) == -1) 229 return (0); 230 tmp = ca->ca_paddr + CG4B_OFF_OVERLAY; 231 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 232 return (0); 233 234 return (1); 235 } 236 237 /* 238 * Attach a display. We need to notice if it is the console, too. 239 */ 240 static void 241 cg4attach(parent, self, args) 242 struct device *parent, *self; 243 void *args; 244 { 245 struct cg4_softc *sc = (struct cg4_softc *)self; 246 struct fbdevice *fb = &sc->sc_fb; 247 struct confargs *ca = args; 248 struct fbtype *fbt; 249 int tmp; 250 251 fbt = &fb->fb_fbtype; 252 fbt->fb_type = FBTYPE_SUN4COLOR; 253 fbt->fb_width = 1152; /* default - see below */ 254 fbt->fb_height = 900; /* default - see below */ 255 fbt->fb_depth = 8; 256 fbt->fb_cmsize = 256; 257 fbt->fb_size = CG4_MMAP_SIZE; 258 fb->fb_driver = &cg4_fbdriver; 259 fb->fb_private = sc; 260 fb->fb_name = sc->sc_dev.dv_xname; 261 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags; 262 263 /* 264 * The config flag 0x10 if set means we are 265 * attaching a Type A (3/110) which has the 266 * AMD RAMDACs in control space, and no P4. 267 */ 268 if (fb->fb_flags & 0x10) { 269 #ifdef _SUN3_ 270 sc->sc_cg4type = CG4_TYPE_A; 271 sc->sc_ldcmap = cg4a_ldcmap; 272 sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY; 273 sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE; 274 sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP; 275 sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP, 276 sizeof(struct amd_regs)); 277 cg4a_init(sc); 278 #else /* SUN3 */ 279 panic("cgfour flags 0x10"); 280 #endif /* SUN3 */ 281 } else { 282 sc->sc_cg4type = CG4_TYPE_B; 283 sc->sc_ldcmap = cg4b_ldcmap; 284 sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY; 285 sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE; 286 sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP; 287 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 288 sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp, 289 sizeof(struct bt_regs)); 290 cg4b_init(sc); 291 } 292 293 if ((fb->fb_flags & 0x20) == 0) { 294 /* It is supposed to have a P4 register. */ 295 fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4); 296 } 297 298 /* 299 * Determine width and height as follows: 300 * If it has a P4 register, use that; 301 * else if unit==0, use the EEPROM size, 302 * else make our best guess. 303 */ 304 if (fb->fb_pfour) 305 fb_pfour_setsize(fb); 306 else if (sc->sc_dev.dv_unit == 0) 307 fb_eeprom_setsize(fb); 308 else { 309 /* Guess based on machine ID. */ 310 switch (cpu_machine_id) { 311 default: 312 /* Leave the defaults set above. */ 313 break; 314 } 315 } 316 printf(" (%dx%d)\n", fbt->fb_width, fbt->fb_height); 317 318 /* 319 * Make sure video is on. This driver uses a 320 * black colormap to blank the screen, so if 321 * there is any global enable, set it here. 322 */ 323 tmp = 1; 324 cg4svideo(fb, &tmp); 325 if (fb->fb_pfour) 326 fb_pfour_set_video(fb, 1); 327 else 328 enable_video(1); 329 330 /* Let /dev/fb know we are here. */ 331 fb_attach(fb, 4); 332 } 333 334 int 335 cg4open(dev, flags, mode, p) 336 dev_t dev; 337 int flags, mode; 338 struct proc *p; 339 { 340 int unit = minor(dev); 341 342 if (unit >= cgfour_cd.cd_ndevs || cgfour_cd.cd_devs[unit] == NULL) 343 return (ENXIO); 344 return (0); 345 } 346 347 int 348 cg4ioctl(dev, cmd, data, flags, p) 349 dev_t dev; 350 u_long cmd; 351 caddr_t data; 352 int flags; 353 struct proc *p; 354 { 355 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 356 357 return (fbioctlfb(&sc->sc_fb, cmd, data)); 358 } 359 360 /* 361 * Return the address that would map the given device at the given 362 * offset, allowing for the given protection, or return -1 for error. 363 * 364 * X11 expects its mmap'd region to look like this: 365 * 128k overlay data memory 366 * 128k overlay enable bitmap 367 * 1024k color memory 368 * 369 * The hardware looks completely different. 370 */ 371 paddr_t 372 cg4mmap(dev, off, prot) 373 dev_t dev; 374 off_t off; 375 int prot; 376 { 377 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 378 int physbase; 379 380 if (off & PGOFSET) 381 panic("cg4mmap"); 382 383 if ((off < 0) || (off >= CG4_MMAP_SIZE)) 384 return (-1); 385 386 if (off < 0x40000) { 387 if (off < 0x20000) { 388 physbase = sc->sc_pa_overlay; 389 } else { 390 /* enable plane */ 391 off -= 0x20000; 392 physbase = sc->sc_pa_enable; 393 } 394 } else { 395 /* pixel map */ 396 off -= 0x40000; 397 physbase = sc->sc_pa_pixmap; 398 } 399 400 /* 401 * I turned on PMAP_NC here to disable the cache as I was 402 * getting horribly broken behaviour without it. 403 */ 404 return ((physbase + off) | PMAP_NC); 405 } 406 407 /* 408 * Internal ioctl functions. 409 */ 410 411 /* FBIOGATTR: */ 412 static int cg4gattr(fb, data) 413 struct fbdevice *fb; 414 void *data; 415 { 416 struct fbgattr *fba = data; 417 418 fba->real_type = fb->fb_fbtype.fb_type; 419 fba->owner = 0; /* XXX - TIOCCONS stuff? */ 420 fba->fbtype = fb->fb_fbtype; 421 fba->sattr.flags = 0; 422 fba->sattr.emu_type = fb->fb_fbtype.fb_type; 423 fba->sattr.dev_specific[0] = -1; 424 fba->emu_types[0] = fb->fb_fbtype.fb_type; 425 fba->emu_types[1] = -1; 426 return (0); 427 } 428 429 /* FBIOGVIDEO: */ 430 static int cg4gvideo(fb, data) 431 struct fbdevice *fb; 432 void *data; 433 { 434 struct cg4_softc *sc = fb->fb_private; 435 int *on = data; 436 437 *on = sc->sc_video_on; 438 return (0); 439 } 440 441 /* FBIOSVIDEO: */ 442 static int cg4svideo(fb, data) 443 struct fbdevice *fb; 444 void *data; 445 { 446 struct cg4_softc *sc = fb->fb_private; 447 int *on = data; 448 449 if (sc->sc_video_on == *on) 450 return (0); 451 sc->sc_video_on = *on; 452 453 (*sc->sc_ldcmap)(sc); 454 return (0); 455 } 456 457 /* 458 * FBIOGETCMAP: 459 * Copy current colormap out to user space. 460 */ 461 static int cg4getcmap(fb, data) 462 struct fbdevice *fb; 463 void *data; 464 { 465 struct cg4_softc *sc = fb->fb_private; 466 struct soft_cmap *cm = &sc->sc_cmap; 467 struct fbcmap *fbcm = data; 468 u_int start, count; 469 int error; 470 471 start = fbcm->index; 472 count = fbcm->count; 473 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 474 return (EINVAL); 475 476 if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0) 477 return (error); 478 479 if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0) 480 return (error); 481 482 if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0) 483 return (error); 484 485 return (0); 486 } 487 488 /* 489 * FBIOPUTCMAP: 490 * Copy new colormap from user space and load. 491 */ 492 static int cg4putcmap(fb, data) 493 struct fbdevice *fb; 494 void *data; 495 { 496 struct cg4_softc *sc = fb->fb_private; 497 struct soft_cmap *cm = &sc->sc_cmap; 498 struct fbcmap *fbcm = data; 499 u_int start, count; 500 int error; 501 502 start = fbcm->index; 503 count = fbcm->count; 504 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 505 return (EINVAL); 506 507 if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0) 508 return (error); 509 510 if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0) 511 return (error); 512 513 if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0) 514 return (error); 515 516 (*sc->sc_ldcmap)(sc); 517 return (0); 518 } 519 520 /**************************************************************** 521 * Routines for the "Type A" hardware 522 ****************************************************************/ 523 #ifdef _SUN3_ 524 525 static void 526 cg4a_init(sc) 527 struct cg4_softc *sc; 528 { 529 volatile struct amd_regs *ar = sc->sc_va_cmap; 530 struct soft_cmap *cm = &sc->sc_cmap; 531 int i; 532 533 /* Grab initial (current) color map. */ 534 for(i = 0; i < 256; i++) { 535 cm->r[i] = ar->r[i]; 536 cm->g[i] = ar->g[i]; 537 cm->b[i] = ar->b[i]; 538 } 539 } 540 541 static void 542 cg4a_ldcmap(sc) 543 struct cg4_softc *sc; 544 { 545 volatile struct amd_regs *ar = sc->sc_va_cmap; 546 struct soft_cmap *cm = &sc->sc_cmap; 547 int i; 548 549 /* 550 * Now blast them into the chip! 551 * XXX Should use retrace interrupt! 552 * Just set a "need load" bit and let the 553 * retrace interrupt handler do the work. 554 */ 555 if (sc->sc_video_on) { 556 /* Update H/W colormap. */ 557 for (i = 0; i < 256; i++) { 558 ar->r[i] = cm->r[i]; 559 ar->g[i] = cm->g[i]; 560 ar->b[i] = cm->b[i]; 561 } 562 } else { 563 /* Clear H/W colormap. */ 564 for (i = 0; i < 256; i++) { 565 ar->r[i] = 0; 566 ar->g[i] = 0; 567 ar->b[i] = 0; 568 } 569 } 570 } 571 #endif /* SUN3 */ 572 573 /**************************************************************** 574 * Routines for the "Type B" hardware 575 ****************************************************************/ 576 577 static void 578 cg4b_init(sc) 579 struct cg4_softc *sc; 580 { 581 volatile struct bt_regs *bt = sc->sc_va_cmap; 582 struct soft_cmap *cm = &sc->sc_cmap; 583 union bt_cmap_u *btcm; 584 int i; 585 586 /* Need a buffer for colormap format translation. */ 587 btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK); 588 sc->sc_btcm = btcm; 589 590 /* 591 * BT458 chip initialization as described in Brooktree's 592 * 1993 Graphics and Imaging Product Databook (DB004-1/93). 593 * 594 * It appears that the 3/60 uses the low byte, and the 3/80 595 * uses the high byte, while both ignore the other bytes. 596 * Writing same value to all bytes works on both. 597 */ 598 bt->bt_addr = 0x04040404; /* select read mask register */ 599 bt->bt_ctrl = ~0; /* all planes on */ 600 bt->bt_addr = 0x05050505; /* select blink mask register */ 601 bt->bt_ctrl = 0; /* all planes non-blinking */ 602 bt->bt_addr = 0x06060606; /* select command register */ 603 bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */ 604 bt->bt_addr = 0x07070707; /* select test register */ 605 bt->bt_ctrl = 0; /* not test mode */ 606 607 /* grab initial (current) color map */ 608 bt->bt_addr = 0; 609 #ifdef _SUN3_ 610 /* Sun3/60 wants 32-bit access, packed. */ 611 for (i = 0; i < (256 * 3 / 4); i++) 612 btcm->btcm_int[i] = bt->bt_cmap; 613 #else /* SUN3 */ 614 /* Sun3/80 wants 8-bits in the high byte. */ 615 for (i = 0; i < (256 * 3); i++) 616 btcm->btcm_char[i] = bt->bt_cmap >> 24; 617 #endif /* SUN3 */ 618 619 /* Transpose into H/W cmap into S/W form. */ 620 for (i = 0; i < 256; i++) { 621 cm->r[i] = btcm->btcm_rgb[i][0]; 622 cm->g[i] = btcm->btcm_rgb[i][1]; 623 cm->b[i] = btcm->btcm_rgb[i][2]; 624 } 625 } 626 627 static void 628 cg4b_ldcmap(sc) 629 struct cg4_softc *sc; 630 { 631 volatile struct bt_regs *bt = sc->sc_va_cmap; 632 struct soft_cmap *cm = &sc->sc_cmap; 633 union bt_cmap_u *btcm = sc->sc_btcm; 634 int i; 635 636 /* Transpose S/W cmap into H/W form. */ 637 for (i = 0; i < 256; i++) { 638 btcm->btcm_rgb[i][0] = cm->r[i]; 639 btcm->btcm_rgb[i][1] = cm->g[i]; 640 btcm->btcm_rgb[i][2] = cm->b[i]; 641 } 642 643 /* 644 * Now blast them into the chip! 645 * XXX Should use retrace interrupt! 646 * Just set a "need load" bit and let the 647 * retrace interrupt handler do the work. 648 */ 649 bt->bt_addr = 0; 650 651 #ifdef _SUN3_ 652 /* Sun3/60 wants 32-bit access, packed. */ 653 if (sc->sc_video_on) { 654 /* Update H/W colormap. */ 655 for (i = 0; i < (256 * 3 / 4); i++) 656 bt->bt_cmap = btcm->btcm_int[i]; 657 } else { 658 /* Clear H/W colormap. */ 659 for (i = 0; i < (256 * 3 / 4); i++) 660 bt->bt_cmap = 0; 661 } 662 #else /* SUN3 */ 663 /* Sun3/80 wants 8-bits in the high byte. */ 664 if (sc->sc_video_on) { 665 /* Update H/W colormap. */ 666 for (i = 0; i < (256 * 3); i++) 667 bt->bt_cmap = btcm->btcm_char[i] << 24; 668 } else { 669 /* Clear H/W colormap. */ 670 for (i = 0; i < (256 * 3); i++) 671 bt->bt_cmap = 0; 672 } 673 #endif /* SUN3 */ 674 } 675 676
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