cg4.c revision 1.31
1 /* $NetBSD: cg4.c,v 1.31 2003/08/07 16:29:54 agc Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93 41 */ 42 43 /* 44 * color display (cg4) driver. 45 * 46 * Credits, history: 47 * Gordon Ross created this driver based on the cg3 driver from 48 * the sparc port as distributed in BSD 4.4 Lite, but included 49 * support for only the "type B" adapter (Brooktree DACs). 50 * Ezra Story added support for the "type A" (AMD DACs). 51 * 52 * Todo: 53 * Make this driver handle video interrupts. 54 * Defer colormap updates to vertical retrace interrupts. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: cg4.c,v 1.31 2003/08/07 16:29:54 agc Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/conf.h> 63 #include <sys/device.h> 64 #include <sys/ioctl.h> 65 #include <sys/malloc.h> 66 #include <sys/mman.h> 67 #include <sys/proc.h> 68 #include <sys/tty.h> 69 70 #include <uvm/uvm_extern.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/cpu.h> 74 #include <dev/sun/fbio.h> 75 #include <machine/idprom.h> 76 #include <machine/pmap.h> 77 78 #include <sun3/dev/fbvar.h> 79 #include <sun3/dev/btreg.h> 80 #include <sun3/dev/cg4reg.h> 81 #include <sun3/dev/p4reg.h> 82 83 union bt_cmap_u { 84 u_char btcm_char[256 * 3]; /* raw data */ 85 u_char btcm_rgb[256][3]; /* 256 R/G/B entries */ 86 u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */ 87 }; 88 89 #define CG4_TYPE_A 0 /* AMD DACs */ 90 #define CG4_TYPE_B 1 /* Brooktree DACs */ 91 92 #define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE) 93 94 #define CMAP_SIZE 256 95 struct soft_cmap { 96 u_char r[CMAP_SIZE]; 97 u_char g[CMAP_SIZE]; 98 u_char b[CMAP_SIZE]; 99 }; 100 101 /* per-display variables */ 102 struct cg4_softc { 103 struct device sc_dev; /* base device */ 104 struct fbdevice sc_fb; /* frame buffer device */ 105 int sc_cg4type; /* A or B */ 106 int sc_pa_overlay; /* phys. addr. of overlay plane */ 107 int sc_pa_enable; /* phys. addr. of enable plane */ 108 int sc_pa_pixmap; /* phys. addr. of color plane */ 109 int sc_video_on; /* zero if blanked */ 110 void *sc_va_cmap; /* Colormap h/w (mapped KVA) */ 111 void *sc_btcm; /* Soft cmap, Brooktree format */ 112 void (*sc_ldcmap) __P((struct cg4_softc *)); 113 struct soft_cmap sc_cmap; /* Soft cmap, user format */ 114 }; 115 116 /* autoconfiguration driver */ 117 static void cg4attach __P((struct device *, struct device *, void *)); 118 static int cg4match __P((struct device *, struct cfdata *, void *)); 119 120 CFATTACH_DECL(cgfour, sizeof(struct cg4_softc), 121 cg4match, cg4attach, NULL, NULL); 122 123 extern struct cfdriver cgfour_cd; 124 125 dev_type_open(cg4open); 126 dev_type_ioctl(cg4ioctl); 127 dev_type_mmap(cg4mmap); 128 129 const struct cdevsw cgfour_cdevsw = { 130 cg4open, nullclose, noread, nowrite, cg4ioctl, 131 nostop, notty, nopoll, cg4mmap, nokqfilter, 132 }; 133 134 static int cg4gattr __P((struct fbdevice *, void *)); 135 static int cg4gvideo __P((struct fbdevice *, void *)); 136 static int cg4svideo __P((struct fbdevice *, void *)); 137 static int cg4getcmap __P((struct fbdevice *, void *)); 138 static int cg4putcmap __P((struct fbdevice *, void *)); 139 140 #ifdef _SUN3_ 141 static void cg4a_init __P((struct cg4_softc *)); 142 static void cg4a_ldcmap __P((struct cg4_softc *)); 143 #endif /* SUN3 */ 144 145 static void cg4b_init __P((struct cg4_softc *)); 146 static void cg4b_ldcmap __P((struct cg4_softc *)); 147 148 static struct fbdriver cg4_fbdriver = { 149 cg4open, nullclose, cg4mmap, nokqfilter, cg4gattr, 150 cg4gvideo, cg4svideo, 151 cg4getcmap, cg4putcmap }; 152 153 /* 154 * Match a cg4. 155 */ 156 static int 157 cg4match(parent, cf, args) 158 struct device *parent; 159 struct cfdata *cf; 160 void *args; 161 { 162 struct confargs *ca = args; 163 int mid, p4id, peekval, tmp; 164 void *p4reg; 165 166 /* No default address support. */ 167 if (ca->ca_paddr == -1) 168 return (0); 169 170 /* 171 * Slight hack here: The low four bits of the 172 * config flags, if set, restrict the match to 173 * that machine "implementation" only. 174 */ 175 mid = cf->cf_flags & IDM_IMPL_MASK; 176 if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK))) 177 return (0); 178 179 /* 180 * The config flag 0x10 if set means we are 181 * looking for a Type A board (3/110). 182 */ 183 if (cf->cf_flags & 0x10) { 184 #ifdef _SUN3_ 185 /* Type A: Check for AMD RAMDACs in control space. */ 186 if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1) 187 return (0); 188 /* Check for the overlay plane. */ 189 tmp = ca->ca_paddr + CG4A_OFF_OVERLAY; 190 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 191 return (0); 192 /* OK, it looks like a Type A. */ 193 return (1); 194 #else /* SUN3 */ 195 /* Only the Sun3/110 ever has a type A. */ 196 return (0); 197 #endif /* SUN3 */ 198 } 199 200 /* 201 * From here on, it is a type B or nothing. 202 * The config flag 0x20 if set means there 203 * is no P4 register. (bus error) 204 */ 205 if ((cf->cf_flags & 0x20) == 0) { 206 p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr); 207 peekval = peek_long(p4reg); 208 p4id = (peekval == -1) ? 209 P4_NOTFOUND : fb_pfour_id(p4reg); 210 bus_tmapout(p4reg); 211 if (peekval == -1) 212 return (0); 213 if (p4id != P4_ID_COLOR8P1) { 214 #ifdef DEBUG 215 printf("cgfour at 0x%x match p4id=0x%x fails\n", 216 ca->ca_paddr, p4id & 0xFF); 217 #endif 218 return (0); 219 } 220 } 221 222 /* 223 * Check for CMAP hardware and overlay plane. 224 */ 225 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 226 if (bus_peek(ca->ca_bustype, tmp, 4) == -1) 227 return (0); 228 tmp = ca->ca_paddr + CG4B_OFF_OVERLAY; 229 if (bus_peek(ca->ca_bustype, tmp, 1) == -1) 230 return (0); 231 232 return (1); 233 } 234 235 /* 236 * Attach a display. We need to notice if it is the console, too. 237 */ 238 static void 239 cg4attach(parent, self, args) 240 struct device *parent, *self; 241 void *args; 242 { 243 struct cg4_softc *sc = (struct cg4_softc *)self; 244 struct fbdevice *fb = &sc->sc_fb; 245 struct confargs *ca = args; 246 struct fbtype *fbt; 247 int tmp; 248 249 fbt = &fb->fb_fbtype; 250 fbt->fb_type = FBTYPE_SUN4COLOR; 251 fbt->fb_width = 1152; /* default - see below */ 252 fbt->fb_height = 900; /* default - see below */ 253 fbt->fb_depth = 8; 254 fbt->fb_cmsize = 256; 255 fbt->fb_size = CG4_MMAP_SIZE; 256 fb->fb_driver = &cg4_fbdriver; 257 fb->fb_private = sc; 258 fb->fb_name = sc->sc_dev.dv_xname; 259 fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags; 260 261 /* 262 * The config flag 0x10 if set means we are 263 * attaching a Type A (3/110) which has the 264 * AMD RAMDACs in control space, and no P4. 265 */ 266 if (fb->fb_flags & 0x10) { 267 #ifdef _SUN3_ 268 sc->sc_cg4type = CG4_TYPE_A; 269 sc->sc_ldcmap = cg4a_ldcmap; 270 sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY; 271 sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE; 272 sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP; 273 sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP, 274 sizeof(struct amd_regs)); 275 cg4a_init(sc); 276 #else /* SUN3 */ 277 panic("cgfour flags 0x10"); 278 #endif /* SUN3 */ 279 } else { 280 sc->sc_cg4type = CG4_TYPE_B; 281 sc->sc_ldcmap = cg4b_ldcmap; 282 sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY; 283 sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE; 284 sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP; 285 tmp = ca->ca_paddr + CG4B_OFF_CMAP; 286 sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp, 287 sizeof(struct bt_regs)); 288 cg4b_init(sc); 289 } 290 291 if ((fb->fb_flags & 0x20) == 0) { 292 /* It is supposed to have a P4 register. */ 293 fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4); 294 } 295 296 /* 297 * Determine width and height as follows: 298 * If it has a P4 register, use that; 299 * else if unit==0, use the EEPROM size, 300 * else make our best guess. 301 */ 302 if (fb->fb_pfour) 303 fb_pfour_setsize(fb); 304 else if (sc->sc_dev.dv_unit == 0) 305 fb_eeprom_setsize(fb); 306 else { 307 /* Guess based on machine ID. */ 308 switch (cpu_machine_id) { 309 default: 310 /* Leave the defaults set above. */ 311 break; 312 } 313 } 314 printf(" (%dx%d)\n", fbt->fb_width, fbt->fb_height); 315 316 /* 317 * Make sure video is on. This driver uses a 318 * black colormap to blank the screen, so if 319 * there is any global enable, set it here. 320 */ 321 tmp = 1; 322 cg4svideo(fb, &tmp); 323 if (fb->fb_pfour) 324 fb_pfour_set_video(fb, 1); 325 else 326 enable_video(1); 327 328 /* Let /dev/fb know we are here. */ 329 fb_attach(fb, 4); 330 } 331 332 int 333 cg4open(dev, flags, mode, p) 334 dev_t dev; 335 int flags, mode; 336 struct proc *p; 337 { 338 int unit = minor(dev); 339 340 if (unit >= cgfour_cd.cd_ndevs || cgfour_cd.cd_devs[unit] == NULL) 341 return (ENXIO); 342 return (0); 343 } 344 345 int 346 cg4ioctl(dev, cmd, data, flags, p) 347 dev_t dev; 348 u_long cmd; 349 caddr_t data; 350 int flags; 351 struct proc *p; 352 { 353 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 354 355 return (fbioctlfb(&sc->sc_fb, cmd, data)); 356 } 357 358 /* 359 * Return the address that would map the given device at the given 360 * offset, allowing for the given protection, or return -1 for error. 361 * 362 * X11 expects its mmap'd region to look like this: 363 * 128k overlay data memory 364 * 128k overlay enable bitmap 365 * 1024k color memory 366 * 367 * The hardware looks completely different. 368 */ 369 paddr_t 370 cg4mmap(dev, off, prot) 371 dev_t dev; 372 off_t off; 373 int prot; 374 { 375 struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)]; 376 int physbase; 377 378 if (off & PGOFSET) 379 panic("cg4mmap"); 380 381 if ((off < 0) || (off >= CG4_MMAP_SIZE)) 382 return (-1); 383 384 if (off < 0x40000) { 385 if (off < 0x20000) { 386 physbase = sc->sc_pa_overlay; 387 } else { 388 /* enable plane */ 389 off -= 0x20000; 390 physbase = sc->sc_pa_enable; 391 } 392 } else { 393 /* pixel map */ 394 off -= 0x40000; 395 physbase = sc->sc_pa_pixmap; 396 } 397 398 /* 399 * I turned on PMAP_NC here to disable the cache as I was 400 * getting horribly broken behaviour without it. 401 */ 402 return ((physbase + off) | PMAP_NC); 403 } 404 405 /* 406 * Internal ioctl functions. 407 */ 408 409 /* FBIOGATTR: */ 410 static int cg4gattr(fb, data) 411 struct fbdevice *fb; 412 void *data; 413 { 414 struct fbgattr *fba = data; 415 416 fba->real_type = fb->fb_fbtype.fb_type; 417 fba->owner = 0; /* XXX - TIOCCONS stuff? */ 418 fba->fbtype = fb->fb_fbtype; 419 fba->sattr.flags = 0; 420 fba->sattr.emu_type = fb->fb_fbtype.fb_type; 421 fba->sattr.dev_specific[0] = -1; 422 fba->emu_types[0] = fb->fb_fbtype.fb_type; 423 fba->emu_types[1] = -1; 424 return (0); 425 } 426 427 /* FBIOGVIDEO: */ 428 static int cg4gvideo(fb, data) 429 struct fbdevice *fb; 430 void *data; 431 { 432 struct cg4_softc *sc = fb->fb_private; 433 int *on = data; 434 435 *on = sc->sc_video_on; 436 return (0); 437 } 438 439 /* FBIOSVIDEO: */ 440 static int cg4svideo(fb, data) 441 struct fbdevice *fb; 442 void *data; 443 { 444 struct cg4_softc *sc = fb->fb_private; 445 int *on = data; 446 447 if (sc->sc_video_on == *on) 448 return (0); 449 sc->sc_video_on = *on; 450 451 (*sc->sc_ldcmap)(sc); 452 return (0); 453 } 454 455 /* 456 * FBIOGETCMAP: 457 * Copy current colormap out to user space. 458 */ 459 static int cg4getcmap(fb, data) 460 struct fbdevice *fb; 461 void *data; 462 { 463 struct cg4_softc *sc = fb->fb_private; 464 struct soft_cmap *cm = &sc->sc_cmap; 465 struct fbcmap *fbcm = data; 466 u_int start, count; 467 int error; 468 469 start = fbcm->index; 470 count = fbcm->count; 471 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 472 return (EINVAL); 473 474 if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0) 475 return (error); 476 477 if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0) 478 return (error); 479 480 if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0) 481 return (error); 482 483 return (0); 484 } 485 486 /* 487 * FBIOPUTCMAP: 488 * Copy new colormap from user space and load. 489 */ 490 static int cg4putcmap(fb, data) 491 struct fbdevice *fb; 492 void *data; 493 { 494 struct cg4_softc *sc = fb->fb_private; 495 struct soft_cmap *cm = &sc->sc_cmap; 496 struct fbcmap *fbcm = data; 497 u_int start, count; 498 int error; 499 500 start = fbcm->index; 501 count = fbcm->count; 502 if (start >= CMAP_SIZE || count > CMAP_SIZE - start) 503 return (EINVAL); 504 505 if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0) 506 return (error); 507 508 if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0) 509 return (error); 510 511 if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0) 512 return (error); 513 514 (*sc->sc_ldcmap)(sc); 515 return (0); 516 } 517 518 /**************************************************************** 519 * Routines for the "Type A" hardware 520 ****************************************************************/ 521 #ifdef _SUN3_ 522 523 static void 524 cg4a_init(sc) 525 struct cg4_softc *sc; 526 { 527 volatile struct amd_regs *ar = sc->sc_va_cmap; 528 struct soft_cmap *cm = &sc->sc_cmap; 529 int i; 530 531 /* Grab initial (current) color map. */ 532 for(i = 0; i < 256; i++) { 533 cm->r[i] = ar->r[i]; 534 cm->g[i] = ar->g[i]; 535 cm->b[i] = ar->b[i]; 536 } 537 } 538 539 static void 540 cg4a_ldcmap(sc) 541 struct cg4_softc *sc; 542 { 543 volatile struct amd_regs *ar = sc->sc_va_cmap; 544 struct soft_cmap *cm = &sc->sc_cmap; 545 int i; 546 547 /* 548 * Now blast them into the chip! 549 * XXX Should use retrace interrupt! 550 * Just set a "need load" bit and let the 551 * retrace interrupt handler do the work. 552 */ 553 if (sc->sc_video_on) { 554 /* Update H/W colormap. */ 555 for (i = 0; i < 256; i++) { 556 ar->r[i] = cm->r[i]; 557 ar->g[i] = cm->g[i]; 558 ar->b[i] = cm->b[i]; 559 } 560 } else { 561 /* Clear H/W colormap. */ 562 for (i = 0; i < 256; i++) { 563 ar->r[i] = 0; 564 ar->g[i] = 0; 565 ar->b[i] = 0; 566 } 567 } 568 } 569 #endif /* SUN3 */ 570 571 /**************************************************************** 572 * Routines for the "Type B" hardware 573 ****************************************************************/ 574 575 static void 576 cg4b_init(sc) 577 struct cg4_softc *sc; 578 { 579 volatile struct bt_regs *bt = sc->sc_va_cmap; 580 struct soft_cmap *cm = &sc->sc_cmap; 581 union bt_cmap_u *btcm; 582 int i; 583 584 /* Need a buffer for colormap format translation. */ 585 btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK); 586 sc->sc_btcm = btcm; 587 588 /* 589 * BT458 chip initialization as described in Brooktree's 590 * 1993 Graphics and Imaging Product Databook (DB004-1/93). 591 * 592 * It appears that the 3/60 uses the low byte, and the 3/80 593 * uses the high byte, while both ignore the other bytes. 594 * Writing same value to all bytes works on both. 595 */ 596 bt->bt_addr = 0x04040404; /* select read mask register */ 597 bt->bt_ctrl = ~0; /* all planes on */ 598 bt->bt_addr = 0x05050505; /* select blink mask register */ 599 bt->bt_ctrl = 0; /* all planes non-blinking */ 600 bt->bt_addr = 0x06060606; /* select command register */ 601 bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */ 602 bt->bt_addr = 0x07070707; /* select test register */ 603 bt->bt_ctrl = 0; /* not test mode */ 604 605 /* grab initial (current) color map */ 606 bt->bt_addr = 0; 607 #ifdef _SUN3_ 608 /* Sun3/60 wants 32-bit access, packed. */ 609 for (i = 0; i < (256 * 3 / 4); i++) 610 btcm->btcm_int[i] = bt->bt_cmap; 611 #else /* SUN3 */ 612 /* Sun3/80 wants 8-bits in the high byte. */ 613 for (i = 0; i < (256 * 3); i++) 614 btcm->btcm_char[i] = bt->bt_cmap >> 24; 615 #endif /* SUN3 */ 616 617 /* Transpose into H/W cmap into S/W form. */ 618 for (i = 0; i < 256; i++) { 619 cm->r[i] = btcm->btcm_rgb[i][0]; 620 cm->g[i] = btcm->btcm_rgb[i][1]; 621 cm->b[i] = btcm->btcm_rgb[i][2]; 622 } 623 } 624 625 static void 626 cg4b_ldcmap(sc) 627 struct cg4_softc *sc; 628 { 629 volatile struct bt_regs *bt = sc->sc_va_cmap; 630 struct soft_cmap *cm = &sc->sc_cmap; 631 union bt_cmap_u *btcm = sc->sc_btcm; 632 int i; 633 634 /* Transpose S/W cmap into H/W form. */ 635 for (i = 0; i < 256; i++) { 636 btcm->btcm_rgb[i][0] = cm->r[i]; 637 btcm->btcm_rgb[i][1] = cm->g[i]; 638 btcm->btcm_rgb[i][2] = cm->b[i]; 639 } 640 641 /* 642 * Now blast them into the chip! 643 * XXX Should use retrace interrupt! 644 * Just set a "need load" bit and let the 645 * retrace interrupt handler do the work. 646 */ 647 bt->bt_addr = 0; 648 649 #ifdef _SUN3_ 650 /* Sun3/60 wants 32-bit access, packed. */ 651 if (sc->sc_video_on) { 652 /* Update H/W colormap. */ 653 for (i = 0; i < (256 * 3 / 4); i++) 654 bt->bt_cmap = btcm->btcm_int[i]; 655 } else { 656 /* Clear H/W colormap. */ 657 for (i = 0; i < (256 * 3 / 4); i++) 658 bt->bt_cmap = 0; 659 } 660 #else /* SUN3 */ 661 /* Sun3/80 wants 8-bits in the high byte. */ 662 if (sc->sc_video_on) { 663 /* Update H/W colormap. */ 664 for (i = 0; i < (256 * 3); i++) 665 bt->bt_cmap = btcm->btcm_char[i] << 24; 666 } else { 667 /* Clear H/W colormap. */ 668 for (i = 0; i < (256 * 3); i++) 669 bt->bt_cmap = 0; 670 } 671 #endif /* SUN3 */ 672 } 673 674
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