dma.c revision 1.10.2.2
1 1.10.2.2 gwr /* $NetBSD: dma.c,v 1.10.2.2 1999/04/08 04:46:42 gwr Exp $ */ 2 1.10.2.2 gwr 3 1.10.2.2 gwr /* 4 1.10.2.2 gwr * Copyright (c) 1994 Paul Kranenburg. All rights reserved. 5 1.10.2.2 gwr * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 1.10.2.2 gwr * 7 1.10.2.2 gwr * Redistribution and use in source and binary forms, with or without 8 1.10.2.2 gwr * modification, are permitted provided that the following conditions 9 1.10.2.2 gwr * are met: 10 1.10.2.2 gwr * 1. Redistributions of source code must retain the above copyright 11 1.10.2.2 gwr * notice, this list of conditions and the following disclaimer. 12 1.10.2.2 gwr * 2. Redistributions in binary form must reproduce the above copyright 13 1.10.2.2 gwr * notice, this list of conditions and the following disclaimer in the 14 1.10.2.2 gwr * documentation and/or other materials provided with the distribution. 15 1.10.2.2 gwr * 3. All advertising materials mentioning features or use of this software 16 1.10.2.2 gwr * must display the following acknowledgement: 17 1.10.2.2 gwr * This product includes software developed by Peter Galbavy. 18 1.10.2.2 gwr * 4. The name of the author may not be used to endorse or promote products 19 1.10.2.2 gwr * derived from this software without specific prior written permission. 20 1.10.2.2 gwr * 21 1.10.2.2 gwr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.10.2.2 gwr * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.10.2.2 gwr * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.10.2.2 gwr * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.10.2.2 gwr * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.10.2.2 gwr * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.10.2.2 gwr * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.10.2.2 gwr * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.10.2.2 gwr * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.10.2.2 gwr * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.10.2.2 gwr */ 32 1.10.2.2 gwr 33 1.10.2.2 gwr #include <sys/types.h> 34 1.10.2.2 gwr #include <sys/param.h> 35 1.10.2.2 gwr #include <sys/systm.h> 36 1.10.2.2 gwr #include <sys/kernel.h> 37 1.10.2.2 gwr #include <sys/errno.h> 38 1.10.2.2 gwr #include <sys/device.h> 39 1.10.2.2 gwr #include <sys/malloc.h> 40 1.10.2.2 gwr 41 1.10.2.2 gwr #include <machine/autoconf.h> 42 1.10.2.2 gwr #include <machine/dvma.h> 43 1.10.2.2 gwr 44 1.10.2.2 gwr #include <dev/scsipi/scsi_all.h> 45 1.10.2.2 gwr #include <dev/scsipi/scsipi_all.h> 46 1.10.2.2 gwr #include <dev/scsipi/scsiconf.h> 47 1.10.2.2 gwr 48 1.10.2.2 gwr #include <dev/ic/ncr53c9xreg.h> 49 1.10.2.2 gwr #include <dev/ic/ncr53c9xvar.h> 50 1.10.2.2 gwr 51 1.10.2.2 gwr #include <sun3/dev/dmareg.h> 52 1.10.2.2 gwr #include <sun3/dev/dmavar.h> 53 1.10.2.2 gwr 54 1.10.2.2 gwr #define MAX_DMA_SZ 0x01000000 /* 16MB */ 55 1.10.2.2 gwr 56 1.10.2.2 gwr static int dmamatch __P((struct device *, struct cfdata *, void *)); 57 1.10.2.2 gwr static void dmaattach __P((struct device *, struct device *, void *)); 58 1.10.2.2 gwr 59 1.10.2.2 gwr struct cfattach dma_ca = { 60 1.10.2.2 gwr sizeof(struct dma_softc), dmamatch, dmaattach 61 1.10.2.2 gwr }; 62 1.10.2.2 gwr 63 1.10.2.2 gwr extern struct cfdriver dma_cd; 64 1.10.2.2 gwr 65 1.10.2.2 gwr static int 66 1.10.2.2 gwr dmamatch(parent, cf, aux) 67 1.10.2.2 gwr struct device *parent; 68 1.10.2.2 gwr struct cfdata *cf; 69 1.10.2.2 gwr void *aux; 70 1.10.2.2 gwr { 71 1.10.2.2 gwr struct confargs *ca = aux; 72 1.10.2.2 gwr 73 1.10.2.2 gwr /* 74 1.10.2.2 gwr * Check for the DMA registers. 75 1.10.2.2 gwr */ 76 1.10.2.2 gwr if (bus_peek(ca->ca_bustype, ca->ca_paddr, 4) == -1) 77 1.10.2.2 gwr return (0); 78 1.10.2.2 gwr 79 1.10.2.2 gwr /* If default ipl, fill it in. */ 80 1.10.2.2 gwr if (ca->ca_intpri == -1) 81 1.10.2.2 gwr ca->ca_intpri = 2; 82 1.10.2.2 gwr 83 1.10.2.2 gwr return (1); 84 1.10.2.2 gwr } 85 1.10.2.2 gwr 86 1.10.2.2 gwr static void 87 1.10.2.2 gwr dmaattach(parent, self, aux) 88 1.10.2.2 gwr struct device *parent, *self; 89 1.10.2.2 gwr void *aux; 90 1.10.2.2 gwr { 91 1.10.2.2 gwr struct confargs *ca = aux; 92 1.10.2.2 gwr struct dma_softc *sc = (void *)self; 93 1.10.2.2 gwr int id; 94 1.10.2.2 gwr 95 1.10.2.2 gwr #if 0 96 1.10.2.2 gwr /* indirect functions */ 97 1.10.2.2 gwr sc->intr = espdmaintr; 98 1.10.2.2 gwr sc->setup = dma_setup; 99 1.10.2.2 gwr sc->reset = dma_reset; 100 1.10.2.2 gwr #endif 101 1.10.2.2 gwr 102 1.10.2.2 gwr /* 103 1.10.2.2 gwr * Map in the registers. 104 1.10.2.2 gwr */ 105 1.10.2.2 gwr sc->sc_regs = bus_mapin(ca->ca_bustype, ca->ca_paddr, 106 1.10.2.2 gwr sizeof(struct dma_regs)); 107 1.10.2.2 gwr sc->sc_rev = DMACSR(sc) & D_DEV_ID; 108 1.10.2.2 gwr id = (sc->sc_rev >> 28) & 0xf; 109 1.10.2.2 gwr printf(": rev %d\n", id); 110 1.10.2.2 gwr 111 1.10.2.2 gwr /* 112 1.10.2.2 gwr * Make sure the DMA chip is supported revision. 113 1.10.2.2 gwr * The Sun3/80 used only the old rev zero chip, 114 1.10.2.2 gwr * so the initialization has been simplified. 115 1.10.2.2 gwr */ 116 1.10.2.2 gwr switch (sc->sc_rev) { 117 1.10.2.2 gwr case DMAREV_0: 118 1.10.2.2 gwr case DMAREV_1: 119 1.10.2.2 gwr break; 120 1.10.2.2 gwr default: 121 1.10.2.2 gwr panic("unsupported dma rev"); 122 1.10.2.2 gwr } 123 1.10.2.2 gwr } 124 1.10.2.2 gwr 125 1.10.2.2 gwr /* 126 1.10.2.2 gwr * This is called by espattach to get our softc. 127 1.10.2.2 gwr */ 128 1.10.2.2 gwr struct dma_softc * 129 1.10.2.2 gwr espdmafind(int unit) 130 1.10.2.2 gwr { 131 1.10.2.2 gwr if (unit < 0 || unit >= dma_cd.cd_ndevs || 132 1.10.2.2 gwr dma_cd.cd_devs[unit] == NULL) 133 1.10.2.2 gwr panic("no dma"); 134 1.10.2.2 gwr return (dma_cd.cd_devs[unit]); 135 1.10.2.2 gwr } 136 1.10.2.2 gwr 137 1.10.2.2 gwr #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 138 1.10.2.2 gwr int count = 100000; \ 139 1.10.2.2 gwr while ((COND) && --count > 0) DELAY(5); \ 140 1.10.2.2 gwr if (count == 0) { \ 141 1.10.2.2 gwr printf("%s: line %d: CSR = 0x%x\n", \ 142 1.10.2.2 gwr __FILE__, __LINE__, DMACSR(SC)); \ 143 1.10.2.2 gwr if (DONTPANIC) \ 144 1.10.2.2 gwr printf(MSG); \ 145 1.10.2.2 gwr else \ 146 1.10.2.2 gwr panic(MSG); \ 147 1.10.2.2 gwr } \ 148 1.10.2.2 gwr } while (0) 149 1.10.2.2 gwr 150 1.10.2.2 gwr #define DMA_DRAIN(sc, dontpanic) do { \ 151 1.10.2.2 gwr /* \ 152 1.10.2.2 gwr * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 153 1.10.2.2 gwr * and "drain" bits while it is still thinking about a \ 154 1.10.2.2 gwr * request. \ 155 1.10.2.2 gwr * other revs: D_R_PEND bit reads as 0 \ 156 1.10.2.2 gwr */ \ 157 1.10.2.2 gwr DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic); \ 158 1.10.2.2 gwr /* \ 159 1.10.2.2 gwr * Select drain bit (always rev 0,1) \ 160 1.10.2.2 gwr * also clears errors and D_TC flag \ 161 1.10.2.2 gwr */ \ 162 1.10.2.2 gwr DMACSR(sc) |= D_DRAIN; \ 163 1.10.2.2 gwr /* \ 164 1.10.2.2 gwr * Wait for draining to finish \ 165 1.10.2.2 gwr */ \ 166 1.10.2.2 gwr DMAWAIT(sc, DMACSR(sc) & D_PACKCNT, "DRAINING", dontpanic); \ 167 1.10.2.2 gwr } while(0) 168 1.10.2.2 gwr 169 1.10.2.2 gwr #define DMA_FLUSH(sc, dontpanic) do { \ 170 1.10.2.2 gwr /* \ 171 1.10.2.2 gwr * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 172 1.10.2.2 gwr * and "drain" bits while it is still thinking about a \ 173 1.10.2.2 gwr * request. \ 174 1.10.2.2 gwr * other revs: D_R_PEND bit reads as 0 \ 175 1.10.2.2 gwr */ \ 176 1.10.2.2 gwr DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic); \ 177 1.10.2.2 gwr DMACSR(sc) &= ~(D_WRITE|D_EN_DMA); \ 178 1.10.2.2 gwr DMACSR(sc) |= D_FLUSH; \ 179 1.10.2.2 gwr } while(0) 180 1.10.2.2 gwr 181 1.10.2.2 gwr void 182 1.10.2.2 gwr dma_reset(sc) 183 1.10.2.2 gwr struct dma_softc *sc; 184 1.10.2.2 gwr { 185 1.10.2.2 gwr 186 1.10.2.2 gwr DMA_FLUSH(sc, 1); 187 1.10.2.2 gwr DMACSR(sc) |= D_RESET; /* reset DMA */ 188 1.10.2.2 gwr DELAY(200); /* what should this be ? */ 189 1.10.2.2 gwr /*DMAWAIT1(sc); why was this here? */ 190 1.10.2.2 gwr DMACSR(sc) &= ~D_RESET; /* de-assert reset line */ 191 1.10.2.2 gwr DELAY(5); /* allow a few ticks to settle */ 192 1.10.2.2 gwr 193 1.10.2.2 gwr /* 194 1.10.2.2 gwr * Get transfer burst size from (?) and plug it into the 195 1.10.2.2 gwr * controller registers. This is needed on the Sun4m... 196 1.10.2.2 gwr * Do we need it too? Apparently not, because the 3/80 197 1.10.2.2 gwr * always has the old, REV zero DMA chip. 198 1.10.2.2 gwr */ 199 1.10.2.2 gwr DMACSR(sc) |= D_INT_EN; /* enable interrupts */ 200 1.10.2.2 gwr 201 1.10.2.2 gwr sc->sc_active = 0; 202 1.10.2.2 gwr } 203 1.10.2.2 gwr 204 1.10.2.2 gwr 205 1.10.2.2 gwr #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 206 1.10.2.2 gwr 207 1.10.2.2 gwr /* 208 1.10.2.2 gwr * setup a dma transfer 209 1.10.2.2 gwr */ 210 1.10.2.2 gwr int 211 1.10.2.2 gwr dma_setup(sc, addr, len, datain, dmasize) 212 1.10.2.2 gwr struct dma_softc *sc; 213 1.10.2.2 gwr caddr_t *addr; 214 1.10.2.2 gwr size_t *len; 215 1.10.2.2 gwr int datain; 216 1.10.2.2 gwr size_t *dmasize; /* IN-OUT */ 217 1.10.2.2 gwr { 218 1.10.2.2 gwr u_int32_t csr; 219 1.10.2.2 gwr 220 1.10.2.2 gwr DMA_FLUSH(sc, 0); 221 1.10.2.2 gwr 222 1.10.2.2 gwr #if 0 223 1.10.2.2 gwr DMACSR(sc) &= ~D_INT_EN; 224 1.10.2.2 gwr #endif 225 1.10.2.2 gwr sc->sc_dmaaddr = addr; 226 1.10.2.2 gwr sc->sc_dmalen = len; 227 1.10.2.2 gwr 228 1.10.2.2 gwr NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 229 1.10.2.2 gwr *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 230 1.10.2.2 gwr 231 1.10.2.2 gwr /* 232 1.10.2.2 gwr * the rules say we cannot transfer more than the limit 233 1.10.2.2 gwr * of this DMA chip (64k for old and 16Mb for new), 234 1.10.2.2 gwr * and we cannot cross a 16Mb boundary. 235 1.10.2.2 gwr */ 236 1.10.2.2 gwr *dmasize = sc->sc_dmasize = 237 1.10.2.2 gwr min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 238 1.10.2.2 gwr 239 1.10.2.2 gwr NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize)); 240 1.10.2.2 gwr 241 1.10.2.2 gwr /* Program the DMA address */ 242 1.10.2.2 gwr if (sc->sc_dmasize) { 243 1.10.2.2 gwr /* 244 1.10.2.2 gwr * Use dvma mapin routines to map the buffer into DVMA space. 245 1.10.2.2 gwr */ 246 1.10.2.2 gwr sc->sc_dvmaaddr = *sc->sc_dmaaddr; 247 1.10.2.2 gwr sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr, 248 1.10.2.2 gwr sc->sc_dmasize, 0); 249 1.10.2.2 gwr if (sc->sc_dvmakaddr == NULL) 250 1.10.2.2 gwr panic("dma: cannot allocate DVMA address"); 251 1.10.2.2 gwr sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO); 252 1.10.2.2 gwr DMADDR(sc) = sc->sc_dmasaddr; 253 1.10.2.2 gwr } else { 254 1.10.2.2 gwr /* XXX: What is this about? -gwr */ 255 1.10.2.2 gwr DMADDR(sc) = (u_int32_t) *sc->sc_dmaaddr; 256 1.10.2.2 gwr } 257 1.10.2.2 gwr 258 1.10.2.2 gwr /* We never have DMAREV_ESC. */ 259 1.10.2.2 gwr 260 1.10.2.2 gwr /* Setup DMA control register */ 261 1.10.2.2 gwr csr = DMACSR(sc); 262 1.10.2.2 gwr if (datain) 263 1.10.2.2 gwr csr |= D_WRITE; 264 1.10.2.2 gwr else 265 1.10.2.2 gwr csr &= ~D_WRITE; 266 1.10.2.2 gwr csr |= D_INT_EN; 267 1.10.2.2 gwr DMACSR(sc) = csr; 268 1.10.2.2 gwr 269 1.10.2.2 gwr return 0; 270 1.10.2.2 gwr } 271 1.10.2.2 gwr 272 1.10.2.2 gwr /* 273 1.10.2.2 gwr * Pseudo (chained) interrupt from the esp driver to kick the 274 1.10.2.2 gwr * current running DMA transfer. I am relying on espintr() to 275 1.10.2.2 gwr * pickup and clean errors for now 276 1.10.2.2 gwr * 277 1.10.2.2 gwr * return 1 if it was a DMA continue. 278 1.10.2.2 gwr */ 279 1.10.2.2 gwr int 280 1.10.2.2 gwr espdmaintr(sc) 281 1.10.2.2 gwr struct dma_softc *sc; 282 1.10.2.2 gwr { 283 1.10.2.2 gwr struct ncr53c9x_softc *nsc = sc->sc_esp; 284 1.10.2.2 gwr char bits[64]; 285 1.10.2.2 gwr int trans, resid; 286 1.10.2.2 gwr u_int32_t csr; 287 1.10.2.2 gwr 288 1.10.2.2 gwr csr = DMACSR(sc); 289 1.10.2.2 gwr 290 1.10.2.2 gwr NCR_DMA(("%s: intr: addr 0x%x, csr %s\n", 291 1.10.2.2 gwr sc->sc_dev.dv_xname, DMADDR(sc), 292 1.10.2.2 gwr bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)))); 293 1.10.2.2 gwr 294 1.10.2.2 gwr if (csr & D_ERR_PEND) { 295 1.10.2.2 gwr DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 296 1.10.2.2 gwr DMACSR(sc) |= D_FLUSH; 297 1.10.2.2 gwr printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 298 1.10.2.2 gwr bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 299 1.10.2.2 gwr return (-1); 300 1.10.2.2 gwr } 301 1.10.2.2 gwr 302 1.10.2.2 gwr /* This is an "assertion" :) */ 303 1.10.2.2 gwr if (sc->sc_active == 0) 304 1.10.2.2 gwr panic("dmaintr: DMA wasn't active"); 305 1.10.2.2 gwr 306 1.10.2.2 gwr DMA_DRAIN(sc, 0); 307 1.10.2.2 gwr 308 1.10.2.2 gwr /* DMA has stopped */ 309 1.10.2.2 gwr DMACSR(sc) &= ~D_EN_DMA; 310 1.10.2.2 gwr sc->sc_active = 0; 311 1.10.2.2 gwr 312 1.10.2.2 gwr if (sc->sc_dmasize == 0) { 313 1.10.2.2 gwr /* A "Transfer Pad" operation completed */ 314 1.10.2.2 gwr NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 315 1.10.2.2 gwr NCR_READ_REG(nsc, NCR_TCL) | 316 1.10.2.2 gwr (NCR_READ_REG(nsc, NCR_TCM) << 8), 317 1.10.2.2 gwr NCR_READ_REG(nsc, NCR_TCL), 318 1.10.2.2 gwr NCR_READ_REG(nsc, NCR_TCM))); 319 1.10.2.2 gwr return 0; 320 1.10.2.2 gwr } 321 1.10.2.2 gwr 322 1.10.2.2 gwr resid = 0; 323 1.10.2.2 gwr /* 324 1.10.2.2 gwr * If a transfer onto the SCSI bus gets interrupted by the device 325 1.10.2.2 gwr * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 326 1.10.2.2 gwr * as residual since the ESP counter registers get decremented as 327 1.10.2.2 gwr * bytes are clocked into the FIFO. 328 1.10.2.2 gwr */ 329 1.10.2.2 gwr if (!(csr & D_WRITE) && 330 1.10.2.2 gwr (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 331 1.10.2.2 gwr NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 332 1.10.2.2 gwr } 333 1.10.2.2 gwr 334 1.10.2.2 gwr if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 335 1.10.2.2 gwr /* 336 1.10.2.2 gwr * `Terminal count' is off, so read the residue 337 1.10.2.2 gwr * out of the ESP counter registers. 338 1.10.2.2 gwr */ 339 1.10.2.2 gwr resid += (NCR_READ_REG(nsc, NCR_TCL) | 340 1.10.2.2 gwr (NCR_READ_REG(nsc, NCR_TCM) << 8) | 341 1.10.2.2 gwr ((nsc->sc_cfg2 & NCRCFG2_FE) 342 1.10.2.2 gwr ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 343 1.10.2.2 gwr : 0)); 344 1.10.2.2 gwr 345 1.10.2.2 gwr if (resid == 0 && sc->sc_dmasize == 65536 && 346 1.10.2.2 gwr (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 347 1.10.2.2 gwr /* A transfer of 64K is encoded as `TCL=TCM=0' */ 348 1.10.2.2 gwr resid = 65536; 349 1.10.2.2 gwr } 350 1.10.2.2 gwr 351 1.10.2.2 gwr trans = sc->sc_dmasize - resid; 352 1.10.2.2 gwr if (trans < 0) { /* transferred < 0 ? */ 353 1.10.2.2 gwr #if 0 354 1.10.2.2 gwr /* 355 1.10.2.2 gwr * This situation can happen in perfectly normal operation 356 1.10.2.2 gwr * if the ESP is reselected while using DMA to select 357 1.10.2.2 gwr * another target. As such, don't print the warning. 358 1.10.2.2 gwr */ 359 1.10.2.2 gwr printf("%s: xfer (%d) > req (%d)\n", 360 1.10.2.2 gwr sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 361 1.10.2.2 gwr #endif 362 1.10.2.2 gwr trans = sc->sc_dmasize; 363 1.10.2.2 gwr } 364 1.10.2.2 gwr 365 1.10.2.2 gwr NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 366 1.10.2.2 gwr NCR_READ_REG(nsc, NCR_TCL), 367 1.10.2.2 gwr NCR_READ_REG(nsc, NCR_TCM), 368 1.10.2.2 gwr (nsc->sc_cfg2 & NCRCFG2_FE) 369 1.10.2.2 gwr ? NCR_READ_REG(nsc, NCR_TCH) : 0, 370 1.10.2.2 gwr trans, resid)); 371 1.10.2.2 gwr 372 1.10.2.2 gwr #ifdef SUN3X_470_EVENTUALLY 373 1.10.2.2 gwr if (csr & D_WRITE) 374 1.10.2.2 gwr cache_flush(*sc->sc_dmaaddr, trans); 375 1.10.2.2 gwr #endif 376 1.10.2.2 gwr 377 1.10.2.2 gwr if (sc->sc_dvmakaddr) 378 1.10.2.2 gwr dvma_mapout(sc->sc_dvmakaddr, sc->sc_dmasize); 379 1.10.2.2 gwr 380 1.10.2.2 gwr *sc->sc_dmalen -= trans; 381 1.10.2.2 gwr *sc->sc_dmaaddr += trans; 382 1.10.2.2 gwr 383 1.10.2.2 gwr #if 0 /* this is not normal operation just yet */ 384 1.10.2.2 gwr if (*sc->sc_dmalen == 0 || 385 1.10.2.2 gwr nsc->sc_phase != nsc->sc_prevphase) 386 1.10.2.2 gwr return 0; 387 1.10.2.2 gwr 388 1.10.2.2 gwr /* and again */ 389 1.10.2.2 gwr dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 390 1.10.2.2 gwr return 1; 391 1.10.2.2 gwr #endif 392 1.10.2.2 gwr return 0; 393 1.10.2.2 gwr } 394
Indexes created Fri Oct 03 02:09:57 GMT 2025