dma.c revision 1.13
1 /* $NetBSD: dma.c,v 1.13 2002/10/02 16:02:25 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Paul Kranenburg. All rights reserved. 5 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Peter Galbavy. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 41 #include <machine/autoconf.h> 42 #include <machine/dvma.h> 43 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 48 #include <dev/ic/ncr53c9xreg.h> 49 #include <dev/ic/ncr53c9xvar.h> 50 51 #include <sun3/dev/dmareg.h> 52 #include <sun3/dev/dmavar.h> 53 54 #define MAX_DMA_SZ 0x01000000 /* 16MB */ 55 56 static int dmamatch __P((struct device *, struct cfdata *, void *)); 57 static void dmaattach __P((struct device *, struct device *, void *)); 58 59 CFATTACH_DECL(dma, sizeof(struct dma_softc), 60 dmamatch, dmaattach, NULL, NULL); 61 62 extern struct cfdriver dma_cd; 63 64 static int 65 dmamatch(parent, cf, aux) 66 struct device *parent; 67 struct cfdata *cf; 68 void *aux; 69 { 70 struct confargs *ca = aux; 71 72 /* 73 * Check for the DMA registers. 74 */ 75 if (bus_peek(ca->ca_bustype, ca->ca_paddr, 4) == -1) 76 return (0); 77 78 /* If default ipl, fill it in. */ 79 if (ca->ca_intpri == -1) 80 ca->ca_intpri = 2; 81 82 return (1); 83 } 84 85 static void 86 dmaattach(parent, self, aux) 87 struct device *parent, *self; 88 void *aux; 89 { 90 struct confargs *ca = aux; 91 struct dma_softc *sc = (void *)self; 92 int id; 93 94 #if 0 95 /* indirect functions */ 96 sc->intr = espdmaintr; 97 sc->setup = dma_setup; 98 sc->reset = dma_reset; 99 #endif 100 101 /* 102 * Map in the registers. 103 */ 104 sc->sc_regs = bus_mapin(ca->ca_bustype, ca->ca_paddr, 105 sizeof(struct dma_regs)); 106 sc->sc_rev = DMACSR(sc) & D_DEV_ID; 107 id = (sc->sc_rev >> 28) & 0xf; 108 printf(": rev %d\n", id); 109 110 /* 111 * Make sure the DMA chip is supported revision. 112 * The Sun3/80 used only the old rev zero chip, 113 * so the initialization has been simplified. 114 */ 115 switch (sc->sc_rev) { 116 case DMAREV_0: 117 case DMAREV_1: 118 break; 119 default: 120 panic("unsupported dma rev"); 121 } 122 } 123 124 /* 125 * This is called by espattach to get our softc. 126 */ 127 struct dma_softc * 128 espdmafind(int unit) 129 { 130 if (unit < 0 || unit >= dma_cd.cd_ndevs || 131 dma_cd.cd_devs[unit] == NULL) 132 panic("no dma"); 133 return (dma_cd.cd_devs[unit]); 134 } 135 136 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 137 int count = 100000; \ 138 while ((COND) && --count > 0) DELAY(5); \ 139 if (count == 0) { \ 140 printf("%s: line %d: CSR = 0x%x\n", \ 141 __FILE__, __LINE__, DMACSR(SC)); \ 142 if (DONTPANIC) \ 143 printf(MSG); \ 144 else \ 145 panic(MSG); \ 146 } \ 147 } while (0) 148 149 #define DMA_DRAIN(sc, dontpanic) do { \ 150 /* \ 151 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 152 * and "drain" bits while it is still thinking about a \ 153 * request. \ 154 * other revs: D_R_PEND bit reads as 0 \ 155 */ \ 156 DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic); \ 157 /* \ 158 * Select drain bit (always rev 0,1) \ 159 * also clears errors and D_TC flag \ 160 */ \ 161 DMACSR(sc) |= D_DRAIN; \ 162 /* \ 163 * Wait for draining to finish \ 164 */ \ 165 DMAWAIT(sc, DMACSR(sc) & D_PACKCNT, "DRAINING", dontpanic); \ 166 } while(0) 167 168 #define DMA_FLUSH(sc, dontpanic) do { \ 169 /* \ 170 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 171 * and "drain" bits while it is still thinking about a \ 172 * request. \ 173 * other revs: D_R_PEND bit reads as 0 \ 174 */ \ 175 DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic); \ 176 DMACSR(sc) &= ~(D_WRITE|D_EN_DMA); \ 177 DMACSR(sc) |= D_FLUSH; \ 178 } while(0) 179 180 void 181 dma_reset(sc) 182 struct dma_softc *sc; 183 { 184 185 DMA_FLUSH(sc, 1); 186 DMACSR(sc) |= D_RESET; /* reset DMA */ 187 DELAY(200); /* what should this be ? */ 188 /*DMAWAIT1(sc); why was this here? */ 189 DMACSR(sc) &= ~D_RESET; /* de-assert reset line */ 190 DELAY(5); /* allow a few ticks to settle */ 191 192 /* 193 * Get transfer burst size from (?) and plug it into the 194 * controller registers. This is needed on the Sun4m... 195 * Do we need it too? Apparently not, because the 3/80 196 * always has the old, REV zero DMA chip. 197 */ 198 DMACSR(sc) |= D_INT_EN; /* enable interrupts */ 199 200 sc->sc_active = 0; 201 } 202 203 204 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 205 206 /* 207 * setup a dma transfer 208 */ 209 int 210 dma_setup(sc, addr, len, datain, dmasize) 211 struct dma_softc *sc; 212 caddr_t *addr; 213 size_t *len; 214 int datain; 215 size_t *dmasize; /* IN-OUT */ 216 { 217 u_int32_t csr; 218 219 DMA_FLUSH(sc, 0); 220 221 #if 0 222 DMACSR(sc) &= ~D_INT_EN; 223 #endif 224 sc->sc_dmaaddr = addr; 225 sc->sc_dmalen = len; 226 227 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 228 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 229 230 /* 231 * the rules say we cannot transfer more than the limit 232 * of this DMA chip (64k for old and 16Mb for new), 233 * and we cannot cross a 16Mb boundary. 234 */ 235 *dmasize = sc->sc_dmasize = 236 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 237 238 NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize)); 239 240 /* Program the DMA address */ 241 if (sc->sc_dmasize) { 242 /* 243 * Use dvma mapin routines to map the buffer into DVMA space. 244 */ 245 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 246 sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr, 247 sc->sc_dmasize, 0); 248 if (sc->sc_dvmakaddr == NULL) 249 panic("dma: cannot allocate DVMA address"); 250 sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO); 251 DMADDR(sc) = sc->sc_dmasaddr; 252 } else { 253 /* XXX: What is this about? -gwr */ 254 DMADDR(sc) = (u_int32_t) *sc->sc_dmaaddr; 255 } 256 257 /* We never have DMAREV_ESC. */ 258 259 /* Setup DMA control register */ 260 csr = DMACSR(sc); 261 if (datain) 262 csr |= D_WRITE; 263 else 264 csr &= ~D_WRITE; 265 csr |= D_INT_EN; 266 DMACSR(sc) = csr; 267 268 return 0; 269 } 270 271 /* 272 * Pseudo (chained) interrupt from the esp driver to kick the 273 * current running DMA transfer. I am relying on espintr() to 274 * pickup and clean errors for now 275 * 276 * return 1 if it was a DMA continue. 277 */ 278 int 279 espdmaintr(sc) 280 struct dma_softc *sc; 281 { 282 struct ncr53c9x_softc *nsc = sc->sc_esp; 283 char bits[64]; 284 int trans, resid; 285 u_int32_t csr; 286 287 csr = DMACSR(sc); 288 289 NCR_DMA(("%s: intr: addr 0x%x, csr %s\n", 290 sc->sc_dev.dv_xname, DMADDR(sc), 291 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)))); 292 293 if (csr & D_ERR_PEND) { 294 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 295 DMACSR(sc) |= D_FLUSH; 296 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 297 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 298 return (-1); 299 } 300 301 /* This is an "assertion" :) */ 302 if (sc->sc_active == 0) 303 panic("dmaintr: DMA wasn't active"); 304 305 DMA_DRAIN(sc, 0); 306 307 /* DMA has stopped */ 308 DMACSR(sc) &= ~D_EN_DMA; 309 sc->sc_active = 0; 310 311 if (sc->sc_dmasize == 0) { 312 /* A "Transfer Pad" operation completed */ 313 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 314 NCR_READ_REG(nsc, NCR_TCL) | 315 (NCR_READ_REG(nsc, NCR_TCM) << 8), 316 NCR_READ_REG(nsc, NCR_TCL), 317 NCR_READ_REG(nsc, NCR_TCM))); 318 return 0; 319 } 320 321 resid = 0; 322 /* 323 * If a transfer onto the SCSI bus gets interrupted by the device 324 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 325 * as residual since the ESP counter registers get decremented as 326 * bytes are clocked into the FIFO. 327 */ 328 if (!(csr & D_WRITE) && 329 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 330 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 331 } 332 333 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 334 /* 335 * `Terminal count' is off, so read the residue 336 * out of the ESP counter registers. 337 */ 338 resid += (NCR_READ_REG(nsc, NCR_TCL) | 339 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 340 ((nsc->sc_cfg2 & NCRCFG2_FE) 341 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 342 : 0)); 343 344 if (resid == 0 && sc->sc_dmasize == 65536 && 345 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 346 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 347 resid = 65536; 348 } 349 350 trans = sc->sc_dmasize - resid; 351 if (trans < 0) { /* transferred < 0 ? */ 352 #if 0 353 /* 354 * This situation can happen in perfectly normal operation 355 * if the ESP is reselected while using DMA to select 356 * another target. As such, don't print the warning. 357 */ 358 printf("%s: xfer (%d) > req (%d)\n", 359 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 360 #endif 361 trans = sc->sc_dmasize; 362 } 363 364 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 365 NCR_READ_REG(nsc, NCR_TCL), 366 NCR_READ_REG(nsc, NCR_TCM), 367 (nsc->sc_cfg2 & NCRCFG2_FE) 368 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 369 trans, resid)); 370 371 #ifdef SUN3X_470_EVENTUALLY 372 if (csr & D_WRITE) 373 cache_flush(*sc->sc_dmaaddr, trans); 374 #endif 375 376 if (sc->sc_dvmakaddr) 377 dvma_mapout(sc->sc_dvmakaddr, sc->sc_dmasize); 378 379 *sc->sc_dmalen -= trans; 380 *sc->sc_dmaaddr += trans; 381 382 #if 0 /* this is not normal operation just yet */ 383 if (*sc->sc_dmalen == 0 || 384 nsc->sc_phase != nsc->sc_prevphase) 385 return 0; 386 387 /* and again */ 388 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 389 return 1; 390 #endif 391 return 0; 392 } 393
Indexes created Fri Sep 26 20:09:58 GMT 2025