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dma.c revision 1.14.8.1 
      1 /*	$NetBSD: dma.c,v 1.14.8.1 2005/04/29 11:28:25 kent Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1994 Paul Kranenburg.  All rights reserved.
      5  * Copyright (c) 1994 Peter Galbavy.  All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Peter Galbavy.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #include <sys/cdefs.h>
     34 __KERNEL_RCSID(0, "$NetBSD: dma.c,v 1.14.8.1 2005/04/29 11:28:25 kent Exp $");
     35 
     36 #include <sys/types.h>
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/kernel.h>
     40 #include <sys/errno.h>
     41 #include <sys/device.h>
     42 #include <sys/malloc.h>
     43 
     44 #include <machine/autoconf.h>
     45 #include <machine/dvma.h>
     46 
     47 #include <dev/scsipi/scsi_all.h>
     48 #include <dev/scsipi/scsipi_all.h>
     49 #include <dev/scsipi/scsiconf.h>
     50 
     51 #include <dev/ic/ncr53c9xreg.h>
     52 #include <dev/ic/ncr53c9xvar.h>
     53 
     54 #include <sun3/dev/dmareg.h>
     55 #include <sun3/dev/dmavar.h>
     56 
     57 #define MAX_DMA_SZ	0x01000000	/* 16MB */
     58 
     59 static int	dmamatch (struct device *, struct cfdata *, void *);
     60 static void	dmaattach(struct device *, struct device *, void *);
     61 
     62 CFATTACH_DECL(dma, sizeof(struct dma_softc),
     63     dmamatch, dmaattach, NULL, NULL);
     64 
     65 extern struct cfdriver dma_cd;
     66 
     67 static int
     68 dmamatch(struct device *parent, struct cfdata *cf, void *aux)
     69 {
     70 	struct confargs *ca = aux;
     71 
     72 	/*
     73 	 * Check for the DMA registers.
     74 	 */
     75 	if (bus_peek(ca->ca_bustype, ca->ca_paddr, 4) == -1)
     76 		return (0);
     77 
     78 	/* If default ipl, fill it in. */
     79 	if (ca->ca_intpri == -1)
     80 		ca->ca_intpri = 2;
     81 
     82 	return (1);
     83 }
     84 
     85 static void
     86 dmaattach(struct device *parent, struct device *self, void *aux)
     87 {
     88 	struct confargs *ca = aux;
     89 	struct dma_softc *sc = (void *)self;
     90 	int id;
     91 
     92 #if 0
     93 	/* indirect functions */
     94 	sc->intr = espdmaintr;
     95 	sc->setup = dma_setup;
     96 	sc->reset = dma_reset;
     97 #endif
     98 
     99 	/*
    100 	 * Map in the registers.
    101 	 */
    102 	sc->sc_regs = bus_mapin(ca->ca_bustype, ca->ca_paddr,
    103 					  sizeof(struct dma_regs));
    104 	sc->sc_rev = DMACSR(sc) & D_DEV_ID;
    105 	id = (sc->sc_rev >> 28) & 0xf;
    106 	printf(": rev %d\n", id);
    107 
    108 	/*
    109 	 * Make sure the DMA chip is supported revision.
    110 	 * The Sun3/80 used only the old rev zero chip,
    111 	 * so the initialization has been simplified.
    112 	 */
    113 	switch (sc->sc_rev) {
    114 	case DMAREV_0:
    115 	case DMAREV_1:
    116 		break;
    117 	default:
    118 		panic("unsupported dma rev");
    119 	}
    120 }
    121 
    122 /*
    123  * This is called by espattach to get our softc.
    124  */
    125 struct dma_softc *
    126 espdmafind(int unit)
    127 {
    128 	if (unit < 0 || unit >= dma_cd.cd_ndevs ||
    129 		dma_cd.cd_devs[unit] == NULL)
    130 		panic("no dma");
    131 	return (dma_cd.cd_devs[unit]);
    132 }
    133 
    134 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) {		\
    135 	int count = 100000;						\
    136 	while ((COND) && --count > 0) DELAY(5);				\
    137 	if (count == 0) {						\
    138 		printf("%s: line %d: CSR = 0x%x\n",			\
    139 			__FILE__, __LINE__, DMACSR(SC));		\
    140 		if (DONTPANIC)						\
    141 			printf(MSG);					\
    142 		else							\
    143 			panic(MSG);					\
    144 	}								\
    145 } while (0)
    146 
    147 #define DMA_DRAIN(sc, dontpanic) do {					\
    148 	/*								\
    149 	 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush"	\
    150 	 *     and "drain" bits while it is still thinking about a	\
    151 	 *     request.							\
    152 	 * other revs: D_R_PEND bit reads as 0				\
    153 	 */								\
    154 	DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic);	\
    155 	/*								\
    156 	 * Select drain bit (always rev 0,1)				\
    157 	 * also clears errors and D_TC flag				\
    158 	 */								\
    159 	DMACSR(sc) |= D_DRAIN;						\
    160 	/*								\
    161 	 * Wait for draining to finish					\
    162 	 */								\
    163 	DMAWAIT(sc, DMACSR(sc) & D_PACKCNT, "DRAINING", dontpanic);	\
    164 } while(0)
    165 
    166 #define DMA_FLUSH(sc, dontpanic) do {					\
    167 	/*								\
    168 	 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush"	\
    169 	 *     and "drain" bits while it is still thinking about a	\
    170 	 *     request.							\
    171 	 * other revs: D_R_PEND bit reads as 0				\
    172 	 */								\
    173 	DMAWAIT(sc, DMACSR(sc) & D_R_PEND, "R_PEND", dontpanic);	\
    174 	DMACSR(sc) &= ~(D_WRITE|D_EN_DMA);				\
    175 	DMACSR(sc) |= D_FLUSH;						\
    176 } while(0)
    177 
    178 void
    179 dma_reset(struct dma_softc *sc)
    180 {
    181 
    182 	DMA_FLUSH(sc, 1);
    183 	DMACSR(sc) |= D_RESET;		/* reset DMA */
    184 	DELAY(200);			/* what should this be ? */
    185 	/*DMAWAIT1(sc); why was this here? */
    186 	DMACSR(sc) &= ~D_RESET;		/* de-assert reset line */
    187 	DELAY(5);			/* allow a few ticks to settle */
    188 
    189 	/*
    190 	 * Get transfer burst size from (?) and plug it into the
    191 	 * controller registers. This is needed on the Sun4m...
    192 	 * Do we need it too?  Apparently not, because the 3/80
    193 	 * always has the old, REV zero DMA chip.
    194 	 */
    195 	DMACSR(sc) |= D_INT_EN;		/* enable interrupts */
    196 
    197 	sc->sc_active = 0;
    198 }
    199 
    200 
    201 #define DMAMAX(a)	(MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
    202 
    203 /*
    204  * setup a dma transfer
    205  */
    206 int
    207 dma_setup(struct dma_softc *sc, caddr_t *addr, size_t *len, int datain,
    208     size_t *dmasize)
    209 {
    210 	uint32_t csr;
    211 
    212 	DMA_FLUSH(sc, 0);
    213 
    214 #if 0
    215 	DMACSR(sc) &= ~D_INT_EN;
    216 #endif
    217 	sc->sc_dmaaddr = addr;
    218 	sc->sc_dmalen = len;
    219 
    220 	NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
    221 		*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
    222 
    223 	/*
    224 	 * the rules say we cannot transfer more than the limit
    225 	 * of this DMA chip (64k for old and 16Mb for new),
    226 	 * and we cannot cross a 16Mb boundary.
    227 	 */
    228 	*dmasize = sc->sc_dmasize =
    229 		min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
    230 
    231 	NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
    232 
    233 	/* Program the DMA address */
    234 	if (sc->sc_dmasize) {
    235 		/*
    236 		 * Use dvma mapin routines to map the buffer into DVMA space.
    237 		 */
    238 		sc->sc_dvmaaddr = *sc->sc_dmaaddr;
    239 		sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr,
    240 					       sc->sc_dmasize, 0);
    241 		if (sc->sc_dvmakaddr == NULL)
    242 			panic("dma: cannot allocate DVMA address");
    243 		sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO);
    244 		DMADDR(sc) = sc->sc_dmasaddr;
    245 	} else {
    246 		/* XXX: What is this about? -gwr */
    247 		DMADDR(sc) = (uint32_t) *sc->sc_dmaaddr;
    248 	}
    249 
    250 	/* We never have DMAREV_ESC. */
    251 
    252 	/* Setup DMA control register */
    253 	csr = DMACSR(sc);
    254 	if (datain)
    255 		csr |= D_WRITE;
    256 	else
    257 		csr &= ~D_WRITE;
    258 	csr |= D_INT_EN;
    259 	DMACSR(sc) = csr;
    260 
    261 	return 0;
    262 }
    263 
    264 /*
    265  * Pseudo (chained) interrupt from the esp driver to kick the
    266  * current running DMA transfer. I am relying on espintr() to
    267  * pickup and clean errors for now
    268  *
    269  * return 1 if it was a DMA continue.
    270  */
    271 int
    272 espdmaintr(struct dma_softc *sc)
    273 {
    274 	struct ncr53c9x_softc *nsc = sc->sc_esp;
    275 	char bits[64];
    276 	int trans, resid;
    277 	uint32_t csr;
    278 
    279 	csr = DMACSR(sc);
    280 
    281 	NCR_DMA(("%s: intr: addr 0x%x, csr %s\n",
    282 		 sc->sc_dev.dv_xname, DMADDR(sc),
    283 		 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))));
    284 
    285 	if (csr & D_ERR_PEND) {
    286 		DMACSR(sc) &= ~D_EN_DMA;	/* Stop DMA */
    287 		DMACSR(sc) |= D_FLUSH;
    288 		printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
    289 			bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
    290 		return (-1);
    291 	}
    292 
    293 	/* This is an "assertion" :) */
    294 	if (sc->sc_active == 0)
    295 		panic("dmaintr: DMA wasn't active");
    296 
    297 	DMA_DRAIN(sc, 0);
    298 
    299 	/* DMA has stopped */
    300 	DMACSR(sc) &= ~D_EN_DMA;
    301 	sc->sc_active = 0;
    302 
    303 	if (sc->sc_dmasize == 0) {
    304 		/* A "Transfer Pad" operation completed */
    305 		NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
    306 			NCR_READ_REG(nsc, NCR_TCL) |
    307 				(NCR_READ_REG(nsc, NCR_TCM) << 8),
    308 			NCR_READ_REG(nsc, NCR_TCL),
    309 			NCR_READ_REG(nsc, NCR_TCM)));
    310 		return 0;
    311 	}
    312 
    313 	resid = 0;
    314 	/*
    315 	 * If a transfer onto the SCSI bus gets interrupted by the device
    316 	 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts
    317 	 * as residual since the ESP counter registers get decremented as
    318 	 * bytes are clocked into the FIFO.
    319 	 */
    320 	if (!(csr & D_WRITE) &&
    321 	    (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
    322 		NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
    323 	}
    324 
    325 	if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
    326 		/*
    327 		 * `Terminal count' is off, so read the residue
    328 		 * out of the ESP counter registers.
    329 		 */
    330 		resid += (NCR_READ_REG(nsc, NCR_TCL) |
    331 			  (NCR_READ_REG(nsc, NCR_TCM) << 8) |
    332 			   ((nsc->sc_cfg2 & NCRCFG2_FE)
    333 				? (NCR_READ_REG(nsc, NCR_TCH) << 16)
    334 				: 0));
    335 
    336 		if (resid == 0 && sc->sc_dmasize == 65536 &&
    337 		    (nsc->sc_cfg2 & NCRCFG2_FE) == 0)
    338 			/* A transfer of 64K is encoded as `TCL=TCM=0' */
    339 			resid = 65536;
    340 	}
    341 
    342 	trans = sc->sc_dmasize - resid;
    343 	if (trans < 0) {			/* transferred < 0 ? */
    344 #if 0
    345 		/*
    346 		 * This situation can happen in perfectly normal operation
    347 		 * if the ESP is reselected while using DMA to select
    348 		 * another target.  As such, don't print the warning.
    349 		 */
    350 		printf("%s: xfer (%d) > req (%d)\n",
    351 		    sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
    352 #endif
    353 		trans = sc->sc_dmasize;
    354 	}
    355 
    356 	NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
    357 		NCR_READ_REG(nsc, NCR_TCL),
    358 		NCR_READ_REG(nsc, NCR_TCM),
    359 		(nsc->sc_cfg2 & NCRCFG2_FE)
    360 			? NCR_READ_REG(nsc, NCR_TCH) : 0,
    361 		trans, resid));
    362 
    363 #ifdef	SUN3X_470_EVENTUALLY
    364 	if (csr & D_WRITE)
    365 		cache_flush(*sc->sc_dmaaddr, trans);
    366 #endif
    367 
    368 	if (sc->sc_dvmakaddr)
    369 		dvma_mapout(sc->sc_dvmakaddr, sc->sc_dmasize);
    370 
    371 	*sc->sc_dmalen -= trans;
    372 	*sc->sc_dmaaddr += trans;
    373 
    374 #if 0	/* this is not normal operation just yet */
    375 	if (*sc->sc_dmalen == 0 ||
    376 	    nsc->sc_phase != nsc->sc_prevphase)
    377 		return 0;
    378 
    379 	/* and again */
    380 	dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
    381 	return 1;
    382 #endif
    383 	return 0;
    384 }
    385