dma.c revision 1.3
1 /* $NetBSD: dma.c,v 1.3 1997/03/15 18:11:00 is Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Paul Kranenburg. All rights reserved. 5 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Peter Galbavy. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/ioctl.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/proc.h> 43 #include <sys/user.h> 44 45 #include <machine/autoconf.h> 46 #include <machine/dvma.h> 47 48 #include <scsi/scsi_all.h> 49 #include <scsi/scsiconf.h> 50 51 #include <sun3x/dev/dmareg.h> 52 #include <sun3x/dev/dmavar.h> 53 #include <sun3x/dev/espreg.h> 54 #include <sun3x/dev/espvar.h> 55 56 void dmaattach __P((struct device *, struct device *, void *)); 57 void dma_reset __P((struct dma_softc *)); 58 void dma_enintr __P((struct dma_softc *)); 59 int dma_isintr __P((struct dma_softc *)); 60 int espdmaintr __P((struct dma_softc *)); 61 int dma_setup __P((struct dma_softc *, caddr_t *, size_t *, 62 int, size_t *)); 63 void dma_go __P((struct dma_softc *)); 64 65 #if 0 66 struct cfattach dma_ca = { 67 sizeof(struct dma_softc), dmamatch, dmaattach 68 }; 69 70 struct cfdriver dma_cd = { 71 NULL, "dma", DV_DULL 72 }; 73 #endif /* 0 */ 74 75 /* 76 * Pseudo-attach function. Called from the esp driver during its 77 * attach function. 78 */ 79 void 80 dmaattach(parent, self, aux) 81 struct device *parent, *self; 82 void *aux; 83 { 84 struct dma_softc *sc = (void *)self; 85 86 /* 87 * The esp driver has filled in the virtual address used to 88 * address the dma registers at this point. Normally we would 89 * map them in here and assign them ourselves. 90 * 91 * It has also filled itself in to our sc->sc_esp register. 92 */ 93 94 /* 95 * Get transfer burst size from PROM and plug it into the 96 * controller registers. This is needed on the Sun4m; do 97 * others need it too? 98 * 99 * Sun3x works ok (so far) without it. 100 */ 101 102 printf(": rev "); 103 sc->sc_rev = sc->sc_regs->csr & D_DEV_ID; 104 switch (sc->sc_rev) { 105 case DMAREV_0: 106 printf("0"); 107 break; 108 case DMAREV_ESC: 109 printf("esc"); 110 break; 111 case DMAREV_1: 112 printf("1"); 113 break; 114 case DMAREV_PLUS: 115 printf("1+"); 116 break; 117 case DMAREV_2: 118 printf("2"); 119 break; 120 default: 121 printf("unknown (0x%x)", sc->sc_rev); 122 } 123 printf("\n"); 124 125 /* indirect functions */ 126 sc->intr = espdmaintr; 127 sc->enintr = dma_enintr; 128 sc->isintr = dma_isintr; 129 sc->reset = dma_reset; 130 sc->setup = dma_setup; 131 sc->go = dma_go; 132 } 133 134 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 135 int count = 500000; \ 136 while ((COND) && --count > 0) DELAY(1); \ 137 if (count == 0) { \ 138 printf("%s: line %d: CSR = %lx\n", __FILE__, __LINE__, \ 139 (SC)->sc_regs->csr); \ 140 if (DONTPANIC) \ 141 printf(MSG); \ 142 else \ 143 panic(MSG); \ 144 } \ 145 } while (0) 146 147 #define DMA_DRAIN(sc, dontpanic) do { \ 148 /* \ 149 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 150 * and "drain" bits while it is still thinking about a \ 151 * request. \ 152 * other revs: D_R_PEND bit reads as 0 \ 153 */ \ 154 DMAWAIT(sc, sc->sc_regs->csr & D_R_PEND, "R_PEND", dontpanic); \ 155 /* \ 156 * Select drain bit based on revision \ 157 * also clears errors and D_TC flag \ 158 */ \ 159 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 160 DMACSR(sc) |= D_DRAIN; \ 161 else \ 162 DMACSR(sc) |= D_INVALIDATE; \ 163 /* \ 164 * Wait for draining to finish \ 165 * rev0 & rev1 call this PACKCNT \ 166 */ \ 167 DMAWAIT(sc, sc->sc_regs->csr & D_DRAINING, "DRAINING", dontpanic);\ 168 } while(0) 169 170 void 171 dma_reset(sc) 172 struct dma_softc *sc; 173 { 174 DMA_DRAIN(sc, 1); 175 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 176 DMACSR(sc) |= D_RESET; /* reset DMA */ 177 DELAY(200); /* what should this be ? */ 178 /*DMAWAIT1(sc); why was this here? */ 179 DMACSR(sc) &= ~D_RESET; /* de-assert reset line */ 180 DMACSR(sc) |= D_INT_EN; /* enable interrupts */ 181 if (sc->sc_rev > DMAREV_1) /* XXX - needed in 3x? */ 182 DMACSR(sc) |= D_FASTER; 183 184 sc->sc_active = 0; /* and of course we aren't */ 185 } 186 187 188 void 189 dma_enintr(sc) 190 struct dma_softc *sc; 191 { 192 sc->sc_regs->csr |= D_INT_EN; 193 } 194 195 int 196 dma_isintr(sc) 197 struct dma_softc *sc; 198 { 199 return (sc->sc_regs->csr & (D_INT_PEND|D_ERR_PEND)); 200 } 201 202 #define DMAMAX(a) (0x01000000 - ((a) & 0x00ffffff)) 203 204 205 /* 206 * setup a dma transfer 207 */ 208 int 209 dma_setup(sc, addr, len, datain, dmasize) 210 struct dma_softc *sc; 211 caddr_t *addr; 212 size_t *len; 213 int datain; 214 size_t *dmasize; /* IN-OUT */ 215 { 216 u_long csr; 217 218 DMA_DRAIN(sc, 0); 219 220 #if 0 221 DMACSR(sc) &= ~D_INT_EN; 222 #endif 223 sc->sc_dmaaddr = addr; 224 sc->sc_dmalen = len; 225 226 ESP_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 227 *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 228 229 /* 230 * the rules say we cannot transfer more than the limit 231 * of this DMA chip (64k for old and 16Mb for new), 232 * and we cannot cross a 16Mb boundary. 233 */ 234 *dmasize = sc->sc_dmasize = 235 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 236 237 ESP_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize)); 238 239 /* Program the DMA address */ 240 if (sc->sc_dmasize) { 241 /* 242 * Use dvma mapin routines to map the buffer into DVMA space. 243 */ 244 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 245 sc->sc_dvmakaddr = dvma_mapin(sc->sc_dvmaaddr, 246 sc->sc_dmasize, 0); 247 if (sc->sc_dvmakaddr == NULL) 248 panic("dma: cannot allocate DVMA address"); 249 sc->sc_dmasaddr = dvma_kvtopa(sc->sc_dvmakaddr, BUS_OBIO); 250 DMADDR(sc) = sc->sc_dmasaddr; 251 } else 252 DMADDR(sc) = (u_long) *sc->sc_dmaaddr; 253 254 if (sc->sc_rev == DMAREV_ESC) { 255 /* DMA ESC chip bug work-around */ 256 register long bcnt = sc->sc_dmasize; 257 register long eaddr = bcnt + (long)*sc->sc_dmaaddr; 258 if ((eaddr & PGOFSET) != 0) 259 bcnt = roundup(bcnt, NBPG); 260 DMACNT(sc) = bcnt; 261 } 262 /* Setup DMA control register */ 263 csr = DMACSR(sc); 264 if (datain) 265 csr |= D_WRITE; 266 else 267 csr &= ~D_WRITE; 268 csr |= D_INT_EN; 269 DMACSR(sc) = csr; 270 271 return 0; 272 } 273 274 void 275 dma_go(sc) 276 struct dma_softc *sc; 277 { 278 279 /* Start DMA */ 280 DMACSR(sc) |= D_EN_DMA; 281 sc->sc_active = 1; 282 } 283 284 /* 285 * Pseudo (chained) interrupt from the esp driver to kick the 286 * current running DMA transfer. I am replying on espintr() to 287 * pickup and clean errors for now 288 * 289 * return 1 if it was a DMA continue. 290 */ 291 int 292 espdmaintr(sc) 293 struct dma_softc *sc; 294 { 295 char bits[64]; 296 int trans, resid; 297 u_long csr; 298 csr = DMACSR(sc); 299 300 ESP_DMA(("%s: intr: addr %x, csr %s\n", sc->sc_dev.dv_xname, 301 DMADDR(sc), bitmask_snprintf(csr, DMACSRBITS, bits, 302 sizeof(bits)))); 303 304 if (csr & D_ERR_PEND) { 305 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */ 306 DMACSR(sc) |= D_INVALIDATE; 307 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, 308 bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits))); 309 return -1; 310 } 311 312 /* This is an "assertion" :) */ 313 if (sc->sc_active == 0) 314 panic("dmaintr: DMA wasn't active"); 315 316 DMA_DRAIN(sc, 0); 317 318 /* DMA has stopped */ 319 DMACSR(sc) &= ~D_EN_DMA; 320 sc->sc_active = 0; 321 322 if (sc->sc_dmasize == 0) { 323 /* A "Transfer Pad" operation completed */ 324 ESP_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 325 ESP_READ_REG(sc->sc_esp, ESP_TCL) | 326 (ESP_READ_REG(sc->sc_esp, ESP_TCM) << 8), 327 ESP_READ_REG(sc->sc_esp, ESP_TCL), 328 ESP_READ_REG(sc->sc_esp, ESP_TCM))); 329 return 0; 330 } 331 332 resid = 0; 333 /* 334 * If a transfer onto the SCSI bus gets interrupted by the device 335 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 336 * as residual since the ESP counter registers get decremented as 337 * bytes are clocked into the FIFO. 338 */ 339 if (!(csr & D_WRITE) && 340 (resid = (ESP_READ_REG(sc->sc_esp, ESP_FFLAG) & ESPFIFO_FF)) != 0) { 341 ESP_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 342 ESPCMD(sc->sc_esp, ESPCMD_FLUSH); 343 } 344 345 if ((sc->sc_esp->sc_espstat & ESPSTAT_TC) == 0) { 346 /* 347 * `Terminal count' is off, so read the residue 348 * out of the ESP counter registers. 349 */ 350 resid += ( ESP_READ_REG(sc->sc_esp, ESP_TCL) | 351 (ESP_READ_REG(sc->sc_esp, ESP_TCM) << 8) | 352 ((sc->sc_esp->sc_cfg2 & ESPCFG2_FE) 353 ? (ESP_READ_REG(sc->sc_esp, ESP_TCH) << 16) 354 : 0)); 355 356 if (resid == 0 && sc->sc_dmasize == 65536 && 357 (sc->sc_esp->sc_cfg2 & ESPCFG2_FE) == 0) 358 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 359 resid = 65536; 360 } 361 362 trans = sc->sc_dmasize - resid; 363 if (trans < 0) { /* transferred < 0 ? */ 364 printf("%s: xfer (%d) > req (%d)\n", 365 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 366 trans = sc->sc_dmasize; 367 } 368 369 ESP_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 370 ESP_READ_REG(sc->sc_esp, ESP_TCL), 371 ESP_READ_REG(sc->sc_esp, ESP_TCM), 372 (sc->sc_esp->sc_cfg2 & ESPCFG2_FE) 373 ? ESP_READ_REG(sc->sc_esp, ESP_TCH) : 0, 374 trans, resid)); 375 376 #ifdef SUN3X_470_EVENTUALLY 377 if (csr & D_WRITE) 378 cache_flush(*sc->sc_dmaaddr, trans); 379 #endif 380 381 if (sc->sc_dvmakaddr) 382 dvma_mapout(sc->sc_dvmakaddr, sc->sc_dmasize); 383 384 *sc->sc_dmalen -= trans; 385 *sc->sc_dmaaddr += trans; 386 387 #if 0 /* this is not normal operation just yet */ 388 if (*sc->sc_dmalen == 0 || 389 sc->sc_esp->sc_phase != sc->sc_esp->sc_prevphase) 390 return 0; 391 392 /* and again */ 393 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 394 return 1; 395 #endif 396 return 0; 397 } 398
Indexes created Fri Oct 03 02:09:57 GMT 2025