esp.c revision 1.1
1 /* $NetBSD: esp.c,v 1.1 1997/02/24 01:45:13 jeremy Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1994 Peter Galbavy 34 * Copyright (c) 1995 Paul Kranenburg 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 #include <sys/types.h> 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/errno.h> 77 #include <sys/ioctl.h> 78 #include <sys/device.h> 79 #include <sys/buf.h> 80 #include <sys/proc.h> 81 #include <sys/user.h> 82 #include <sys/queue.h> 83 #include <sys/malloc.h> 84 85 #include <scsi/scsi_all.h> 86 #include <scsi/scsiconf.h> 87 #include <scsi/scsi_message.h> 88 89 #include <machine/autoconf.h> 90 #include <sun3x/dev/dmareg.h> 91 #include <sun3x/dev/dmavar.h> 92 #include <sun3x/dev/espreg.h> 93 #include <sun3x/dev/espvar.h> 94 95 #define ESP_REG_SIZE (12*4) 96 #define ESP_DMA_OFF 0x1000 97 98 int esp_debug = 0; /*ESP_SHOWPHASE|ESP_SHOWMISC|ESP_SHOWTRAC|ESP_SHOWCMDS;*/ 99 100 /*static*/ void espattach __P((struct device *, struct device *, void *)); 101 /*static*/ int espmatch __P((struct device *, struct cfdata *, void *)); 102 /*static*/ u_int esp_adapter_info __P((struct esp_softc *)); 103 /*static*/ void espreadregs __P((struct esp_softc *)); 104 /*static*/ void esp_select __P((struct esp_softc *, struct esp_ecb *)); 105 /*static*/ int esp_reselect __P((struct esp_softc *, int)); 106 /*static*/ void esp_scsi_reset __P((struct esp_softc *)); 107 /*static*/ void esp_reset __P((struct esp_softc *)); 108 /*static*/ void esp_init __P((struct esp_softc *, int)); 109 /*static*/ int esp_scsi_cmd __P((struct scsi_xfer *)); 110 /*static*/ int esp_poll __P((struct esp_softc *, struct scsi_xfer *, int)); 111 /*static*/ void esp_sched __P((struct esp_softc *)); 112 /*static*/ void esp_done __P((struct esp_softc *, struct esp_ecb *)); 113 /*static*/ void esp_msgin __P((struct esp_softc *)); 114 /*static*/ void esp_msgout __P((struct esp_softc *)); 115 /*static*/ int espintr __P((struct esp_softc *)); 116 /*static*/ void esp_timeout __P((void *arg)); 117 /*static*/ void esp_abort __P((struct esp_softc *, struct esp_ecb *)); 118 /*static*/ void esp_dequeue __P((struct esp_softc *, struct esp_ecb *)); 119 void esp_sense __P((struct esp_softc *, struct esp_ecb *)); 120 void esp_free_ecb __P((struct esp_softc *, struct esp_ecb *, int)); 121 struct esp_ecb *esp_get_ecb __P((struct esp_softc *, int)); 122 static inline int esp_stp2cpb __P((struct esp_softc *, int)); 123 static inline int esp_cpb2stp __P((struct esp_softc *, int)); 124 static inline void esp_setsync __P((struct esp_softc *, struct esp_tinfo *)); 125 126 /* 127 * This section is machine-dependent 128 * (autoconf data and match/attach functions) 129 */ 130 131 struct cfattach esp_ca = { 132 sizeof(struct esp_softc), espmatch, espattach 133 }; 134 135 struct cfdriver esp_cd = { 136 NULL, "esp", DV_DULL 137 }; 138 139 struct scsi_adapter esp_switch = { 140 esp_scsi_cmd, 141 minphys, /* no max at this level; handled by DMA code */ 142 NULL, 143 NULL, 144 }; 145 146 struct scsi_device esp_dev = { 147 NULL, /* Use default error handler */ 148 NULL, /* have a queue, served by this */ 149 NULL, /* have no async handler */ 150 NULL, /* Use default 'done' routine */ 151 }; 152 153 int 154 espmatch(parent, cf, aux) 155 struct device *parent; 156 struct cfdata *cf; 157 void *aux; 158 { 159 struct confargs *ca = aux; 160 161 /* 162 * Check for the DMA registers. 163 */ 164 if (bus_peek(ca->ca_bustype, 165 ca->ca_paddr + ESP_DMA_OFF, 4) == -1) 166 return (0); 167 168 /* 169 * Check for the esp registers. 170 */ 171 if (bus_peek(ca->ca_bustype, 172 ca->ca_paddr + (ESP_STAT * 4), 1) == -1) 173 return (0); 174 175 /* If default ipl, fill it in. */ 176 if (ca->ca_intpri == -1) 177 ca->ca_intpri = 2; 178 179 return (1); 180 } 181 182 /* 183 * Attach this instance, and then all the sub-devices 184 */ 185 void 186 espattach(parent, self, aux) 187 struct device *parent, *self; 188 void *aux; 189 { 190 register struct confargs *ca = aux; 191 struct esp_softc *sc = (void *)self; 192 193 /* 194 * Map in the registers. 195 */ 196 sc->sc_reg = (volatile u_char *) 197 bus_mapin(ca->ca_bustype, ca->ca_paddr, NBPG); 198 199 sc->sc_id = 7; 200 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 201 202 /* 203 * It is necessary to try to load the 2nd config register here, 204 * to find out what rev the esp chip is, otherwise esp_reset 205 * will not set up the defaults correctly. 206 */ 207 sc->sc_cfg1 = sc->sc_id | ESPCFG1_PARENB; 208 sc->sc_cfg2 = ESPCFG2_SCSI2 | ESPCFG2_RPE; 209 sc->sc_cfg3 = ESPCFG3_CDB; 210 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 211 212 if ((ESP_READ_REG(sc, ESP_CFG2) & ~ESPCFG2_RSVD) != (ESPCFG2_SCSI2 | ESPCFG2_RPE)) { 213 printf(": ESP100"); 214 sc->sc_rev = ESP100; 215 } else { 216 sc->sc_cfg2 = ESPCFG2_SCSI2; 217 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 218 sc->sc_cfg3 = 0; 219 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 220 sc->sc_cfg3 = (ESPCFG3_CDB | ESPCFG3_FCLK); 221 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 222 if (ESP_READ_REG(sc, ESP_CFG3) != (ESPCFG3_CDB | ESPCFG3_FCLK)) { 223 printf(": ESP100A"); 224 sc->sc_rev = ESP100A; 225 } else { 226 /* ESPCFG2_FE enables > 64K transfers */ 227 sc->sc_cfg2 |= ESPCFG2_FE; 228 sc->sc_cfg3 = 0; 229 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 230 printf(": ESP200"); 231 sc->sc_rev = ESP200; 232 } 233 } 234 printf(" %dMhz, target %d\n", sc->sc_freq, sc->sc_id); 235 236 /* 237 * In the SPARC port, the dma code used by the esp driver looks like 238 * a separate driver, matched and attached by either the esp driver 239 * or the bus attach function. However it's not completely separate 240 * in that the sparc esp driver has to go look in dma_cd.cd_devs to 241 * get the softc for the dma driver, and shares its softc, etc. 242 * 243 * In the current sun3x port, the dma chip is treated as just an 244 * extension of the esp driver because that is easier, and the esp 245 * driver is the only one that uses the dma module. 246 * 247 * The dma module could exist as a separate autoconfig entity, but 248 * that really does not buy us anything, so why bother with that? 249 * We can just simulate an attach call here for compatibility with 250 * the sparc dma.c module. 251 */ 252 sc->sc_dma = malloc(sizeof(struct dma_softc), M_DEVBUF, M_NOWAIT); 253 if (sc->sc_dma == 0) 254 panic("espattach: malloc dma_softc"); 255 bzero(sc->sc_dma, sizeof(struct dma_softc)); 256 257 sc->sc_dma->sc_esp = sc; /* Point back to us */ 258 sc->sc_dma->sc_regs = (struct dma_regs *) 259 (sc->sc_reg + ESP_DMA_OFF); 260 261 /* Simulate the autoconfig messages... */ 262 printf("%s: dma", sc->sc_dev.dv_xname); 263 /* This will print ": rev ..." */ 264 dmaattach(self, (struct device *) sc->sc_dma, NULL); 265 266 /* 267 * This is the value used to start sync negotiations 268 * Note that the ESP register "SYNCTP" is programmed 269 * in "clocks per byte", and has a minimum value of 4. 270 * The SCSI period used in negotiation is one-fourth 271 * of the time (in nanoseconds) needed to transfer one byte. 272 * Since the chip's clock is given in MHz, we have the following 273 * formula: 4 * period = (1000 / freq) * 4 274 */ 275 sc->sc_minsync = 1000 / sc->sc_freq; 276 277 /* 278 * Alas, we must now modify the value a bit, because it's 279 * only valid when can switch on FASTCLK and FASTSCSI bits 280 * in config register 3... 281 */ 282 switch (sc->sc_rev) { 283 case ESP100: 284 sc->sc_maxxfer = 64 * 1024; 285 sc->sc_minsync = 0; /* No synch on old chip? */ 286 break; 287 case ESP100A: 288 sc->sc_maxxfer = 64 * 1024; 289 sc->sc_minsync = esp_cpb2stp(sc, 5); /* Min clocks/byte is 5 */ 290 break; 291 case ESP200: 292 sc->sc_maxxfer = 16 * 1024 * 1024; 293 /* XXX - do actually set FAST* bits */ 294 } 295 296 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 297 298 /* The value *must not* be == 1. Make it 2 */ 299 if (sc->sc_ccf == 1) 300 sc->sc_ccf = 2; 301 302 /* 303 * The recommended timeout is 250ms. This register is loaded 304 * with a value calculated as follows, from the docs: 305 * 306 * (timout period) x (CLK frequency) 307 * reg = ------------------------------------- 308 * 8192 x (Clock Conversion Factor) 309 * 310 * Since CCF has a linear relation to CLK, this generally computes 311 * to the constant of 153. 312 */ 313 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 314 315 /* CCF register only has 3 bits; 0 is actually 8 */ 316 sc->sc_ccf &= 7; 317 318 /* Reset state & bus */ 319 sc->sc_state = 0; 320 esp_init(sc, 1); 321 322 /* and the interuppts */ 323 isr_add_autovect((isr_func_t) espintr, (void *) sc, ca->ca_intpri); 324 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 325 326 /* 327 * fill in the prototype scsi_link. 328 */ 329 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 330 sc->sc_link.adapter_softc = sc; 331 sc->sc_link.adapter_target = sc->sc_id; 332 sc->sc_link.adapter = &esp_switch; 333 sc->sc_link.device = &esp_dev; 334 sc->sc_link.openings = 2; 335 sc->sc_link.max_target = 7; 336 337 /* 338 * Now try to attach all the sub-devices 339 */ 340 config_found(self, &sc->sc_link, scsiprint); 341 } 342 343 /* 344 * End of machine-dependent section 345 */ 346 347 /* 348 * This is the generic esp reset function. It does not reset the SCSI bus, 349 * only this controllers, but kills any on-going commands, and also stops 350 * and resets the DMA. 351 * 352 * After reset, registers are loaded with the defaults from the attach 353 * routine above. 354 */ 355 void 356 esp_reset(sc) 357 struct esp_softc *sc; 358 { 359 360 /* reset DMA first */ 361 DMA_RESET(sc->sc_dma); 362 363 /* reset SCSI chip */ 364 ESPCMD(sc, ESPCMD_RSTCHIP); 365 ESPCMD(sc, ESPCMD_NOP); 366 DELAY(500); 367 368 /* do these backwards, and fall through */ 369 switch (sc->sc_rev) { 370 case ESP200: 371 ESP_WRITE_REG(sc, ESP_CFG3, sc->sc_cfg3); 372 case ESP100A: 373 ESP_WRITE_REG(sc, ESP_CFG2, sc->sc_cfg2); 374 case ESP100: 375 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 376 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 377 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 378 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 379 break; 380 default: 381 printf("%s: unknown revision code, assuming ESP100\n", 382 sc->sc_dev.dv_xname); 383 ESP_WRITE_REG(sc, ESP_CFG1, sc->sc_cfg1); 384 ESP_WRITE_REG(sc, ESP_CCF, sc->sc_ccf); 385 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 386 ESP_WRITE_REG(sc, ESP_TIMEOUT, sc->sc_timeout); 387 } 388 } 389 390 /* 391 * Reset the SCSI bus, but not the chip 392 */ 393 void 394 esp_scsi_reset(sc) 395 struct esp_softc *sc; 396 { 397 /* stop DMA first, as the chip will return to Bus Free phase */ 398 DMACSR(sc->sc_dma) &= ~D_EN_DMA; 399 400 printf("esp: resetting SCSI bus\n"); 401 ESPCMD(sc, ESPCMD_RSTSCSI); 402 } 403 404 /* 405 * Initialize esp state machine 406 */ 407 void 408 esp_init(sc, doreset) 409 struct esp_softc *sc; 410 int doreset; 411 { 412 struct esp_ecb *ecb; 413 int r; 414 415 ESP_TRACE(("[ESP_INIT(%d)] ", doreset)); 416 417 if (sc->sc_state == 0) { 418 /* First time through; initialize. */ 419 TAILQ_INIT(&sc->ready_list); 420 TAILQ_INIT(&sc->nexus_list); 421 TAILQ_INIT(&sc->free_list); 422 sc->sc_nexus = NULL; 423 ecb = sc->sc_ecb; 424 bzero(ecb, sizeof(sc->sc_ecb)); 425 for (r = 0; r < sizeof(sc->sc_ecb) / sizeof(*ecb); r++) { 426 TAILQ_INSERT_TAIL(&sc->free_list, ecb, chain); 427 ecb++; 428 } 429 bzero(sc->sc_tinfo, sizeof(sc->sc_tinfo)); 430 } else { 431 /* Cancel any active commands. */ 432 sc->sc_state = ESP_CLEANING; 433 if ((ecb = sc->sc_nexus) != NULL) { 434 ecb->xs->error = XS_DRIVER_STUFFUP; 435 untimeout(esp_timeout, ecb); 436 esp_done(sc, ecb); 437 } 438 while ((ecb = sc->nexus_list.tqh_first) != NULL) { 439 ecb->xs->error = XS_DRIVER_STUFFUP; 440 untimeout(esp_timeout, ecb); 441 esp_done(sc, ecb); 442 } 443 } 444 445 /* 446 * reset the chip to a known state 447 */ 448 esp_reset(sc); 449 450 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 451 for (r = 0; r < 8; r++) { 452 struct esp_tinfo *ti = &sc->sc_tinfo[r]; 453 /* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 454 int fl = sc->sc_dev.dv_cfdata->cf_flags; 455 456 ti->flags = ((sc->sc_minsync && !(fl & (1<<(r+8)))) 457 ? T_NEGOTIATE : 0) | 458 ((fl & (1<<r)) ? T_RSELECTOFF : 0) | 459 T_NEED_TO_RESET; 460 ti->period = sc->sc_minsync; 461 ti->offset = 0; 462 } 463 464 if (doreset) { 465 sc->sc_state = ESP_SBR; 466 ESPCMD(sc, ESPCMD_RSTSCSI); 467 } else { 468 sc->sc_state = ESP_IDLE; 469 } 470 } 471 472 /* 473 * Read the ESP registers, and save their contents for later use. 474 * ESP_STAT, ESP_STEP & ESP_INTR are mostly zeroed out when reading 475 * ESP_INTR - so make sure it is the last read. 476 * 477 * I think that (from reading the docs) most bits in these registers 478 * only make sense when he DMA CSR has an interrupt showing. Call only 479 * if an interrupt is pending. 480 */ 481 void 482 espreadregs(sc) 483 struct esp_softc *sc; 484 { 485 486 sc->sc_espstat = ESP_READ_REG(sc, ESP_STAT); 487 /* Only the stepo bits are of interest */ 488 sc->sc_espstep = ESP_READ_REG(sc, ESP_STEP) & ESPSTEP_MASK; 489 sc->sc_espintr = ESP_READ_REG(sc, ESP_INTR); 490 491 /* 492 * Determine the SCSI bus phase, return either a real SCSI bus phase 493 * or some pseudo phase we use to detect certain exceptions. 494 */ 495 496 sc->sc_phase = (sc->sc_espintr & ESPINTR_DIS) 497 ? /* Disconnected */ BUSFREE_PHASE 498 : sc->sc_espstat & ESPSTAT_PHASE; 499 500 ESP_MISC(("regs[intr=%02x,stat=%02x,step=%02x] ", 501 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep)); 502 } 503 504 /* 505 * Convert chip register Clock Per Byte value to Synchronous Transfer Period. 506 */ 507 static inline int 508 esp_cpb2stp(sc, cpb) 509 struct esp_softc *sc; 510 int cpb; 511 { 512 return ((250 * cpb) / sc->sc_freq); 513 } 514 515 /* 516 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 517 */ 518 static inline int 519 esp_stp2cpb(sc, period) 520 struct esp_softc *sc; 521 int period; 522 { 523 int v; 524 v = (sc->sc_freq * period) / 250; 525 if (esp_cpb2stp(sc, v) < period) 526 /* Correct round-down error */ 527 v++; 528 return v; 529 } 530 531 static inline void 532 esp_setsync(sc, ti) 533 struct esp_softc *sc; 534 struct esp_tinfo *ti; 535 { 536 537 if (ti->flags & T_SYNCMODE) { 538 ESP_WRITE_REG(sc, ESP_SYNCOFF, ti->offset); 539 ESP_WRITE_REG(sc, ESP_SYNCTP, esp_stp2cpb(sc, ti->period)); 540 } else { 541 ESP_WRITE_REG(sc, ESP_SYNCOFF, 0); 542 ESP_WRITE_REG(sc, ESP_SYNCTP, 0); 543 } 544 } 545 546 /* 547 * Send a command to a target, set the driver state to ESP_SELECTING 548 * and let the caller take care of the rest. 549 * 550 * Keeping this as a function allows me to say that this may be done 551 * by DMA instead of programmed I/O soon. 552 */ 553 void 554 esp_select(sc, ecb) 555 struct esp_softc *sc; 556 struct esp_ecb *ecb; 557 { 558 struct scsi_link *sc_link = ecb->xs->sc_link; 559 int target = sc_link->target; 560 struct esp_tinfo *ti = &sc->sc_tinfo[target]; 561 u_char *cmd; 562 int clen; 563 564 ESP_TRACE(("[esp_select(t%d,l%d,cmd:%x)] ", sc_link->target, sc_link->lun, ecb->cmd.opcode)); 565 566 /* new state ESP_SELECTING */ 567 sc->sc_state = ESP_SELECTING; 568 569 ESPCMD(sc, ESPCMD_FLUSH); 570 571 /* 572 * The docs say the target register is never reset, and I 573 * can't think of a better place to set it 574 */ 575 ESP_WRITE_REG(sc, ESP_SELID, target); 576 esp_setsync(sc, ti); 577 578 /* 579 * Who am I. This is where we tell the target that we are 580 * happy for it to disconnect etc. 581 */ 582 ESP_WRITE_REG(sc, ESP_FIFO, 583 MSG_IDENTIFY(sc_link->lun, (ti->flags & T_RSELECTOFF)?0:1)); 584 585 if (ti->flags & T_NEGOTIATE) { 586 /* Arbitrate, select and stop after IDENTIFY message */ 587 ESPCMD(sc, ESPCMD_SELATNS); 588 return; 589 } 590 591 /* Now the command into the FIFO */ 592 cmd = (u_char *)&ecb->cmd; 593 clen = ecb->clen; 594 while (clen--) 595 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 596 597 /* And get the targets attention */ 598 ESPCMD(sc, ESPCMD_SELATN); 599 } 600 601 void 602 esp_free_ecb(sc, ecb, flags) 603 struct esp_softc *sc; 604 struct esp_ecb *ecb; 605 int flags; 606 { 607 int s; 608 609 s = splbio(); 610 611 ecb->flags = 0; 612 TAILQ_INSERT_HEAD(&sc->free_list, ecb, chain); 613 614 /* 615 * If there were none, wake anybody waiting for one to come free, 616 * starting with queued entries. 617 */ 618 if (ecb->chain.tqe_next == 0) 619 wakeup(&sc->free_list); 620 621 splx(s); 622 } 623 624 struct esp_ecb * 625 esp_get_ecb(sc, flags) 626 struct esp_softc *sc; 627 int flags; 628 { 629 struct esp_ecb *ecb; 630 int s; 631 632 s = splbio(); 633 634 while ((ecb = sc->free_list.tqh_first) == NULL && 635 (flags & SCSI_NOSLEEP) == 0) 636 tsleep(&sc->free_list, PRIBIO, "especb", 0); 637 if (ecb) { 638 TAILQ_REMOVE(&sc->free_list, ecb, chain); 639 ecb->flags |= ECB_ALLOC; 640 } 641 642 splx(s); 643 return ecb; 644 } 645 646 /* 647 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 648 */ 649 650 /* 651 * Start a SCSI-command 652 * This function is called by the higher level SCSI-driver to queue/run 653 * SCSI-commands. 654 */ 655 int 656 esp_scsi_cmd(xs) 657 struct scsi_xfer *xs; 658 { 659 struct scsi_link *sc_link = xs->sc_link; 660 struct esp_softc *sc = sc_link->adapter_softc; 661 struct esp_ecb *ecb; 662 int s, flags; 663 664 ESP_TRACE(("[esp_scsi_cmd] ")); 665 ESP_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 666 sc_link->target)); 667 668 flags = xs->flags; 669 if ((ecb = esp_get_ecb(sc, flags)) == NULL) { 670 xs->error = XS_DRIVER_STUFFUP; 671 return TRY_AGAIN_LATER; 672 } 673 674 /* Initialize ecb */ 675 ecb->xs = xs; 676 ecb->timeout = xs->timeout; 677 678 if (xs->flags & SCSI_RESET) { 679 ecb->flags |= ECB_RESET; 680 ecb->clen = 0; 681 ecb->dleft = 0; 682 } else { 683 bcopy(xs->cmd, &ecb->cmd, xs->cmdlen); 684 ecb->clen = xs->cmdlen; 685 ecb->daddr = xs->data; 686 ecb->dleft = xs->datalen; 687 } 688 ecb->stat = 0; 689 690 s = splbio(); 691 692 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 693 if (sc->sc_state == ESP_IDLE) 694 esp_sched(sc); 695 696 splx(s); 697 698 if ((flags & SCSI_POLL) == 0) 699 return SUCCESSFULLY_QUEUED; 700 701 /* Not allowed to use interrupts, use polling instead */ 702 if (esp_poll(sc, xs, ecb->timeout)) { 703 esp_timeout(ecb); 704 if (esp_poll(sc, xs, ecb->timeout)) 705 esp_timeout(ecb); 706 } 707 return COMPLETE; 708 } 709 710 /* 711 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 712 */ 713 int 714 esp_poll(sc, xs, count) 715 struct esp_softc *sc; 716 struct scsi_xfer *xs; 717 int count; 718 { 719 720 ESP_TRACE(("[esp_poll] ")); 721 while (count) { 722 if (DMA_ISINTR(sc->sc_dma)) { 723 espintr(sc); 724 } 725 #if alternatively 726 if (ESP_READ_REG(sc, ESP_STAT) & ESPSTAT_INT) 727 espintr(sc); 728 #endif 729 if ((xs->flags & ITSDONE) != 0) 730 return 0; 731 if (sc->sc_state == ESP_IDLE) { 732 ESP_TRACE(("[esp_poll: rescheduling] ")); 733 esp_sched(sc); 734 } 735 DELAY(1000); 736 count--; 737 } 738 return 1; 739 } 740 741 742 /* 743 * LOW LEVEL SCSI UTILITIES 744 */ 745 746 /* 747 * Schedule a scsi operation. This has now been pulled out of the interrupt 748 * handler so that we may call it from esp_scsi_cmd and esp_done. This may 749 * save us an unecessary interrupt just to get things going. Should only be 750 * called when state == ESP_IDLE and at bio pl. 751 */ 752 void 753 esp_sched(sc) 754 struct esp_softc *sc; 755 { 756 struct esp_ecb *ecb; 757 struct scsi_link *sc_link; 758 struct esp_tinfo *ti; 759 760 ESP_TRACE(("[esp_sched] ")); 761 if (sc->sc_state != ESP_IDLE) 762 panic("esp_sched: not IDLE (state=%d)", sc->sc_state); 763 764 /* 765 * Find first ecb in ready queue that is for a target/lunit 766 * combinations that is not busy. 767 */ 768 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 769 sc_link = ecb->xs->sc_link; 770 ti = &sc->sc_tinfo[sc_link->target]; 771 if ((ti->lubusy & (1 << sc_link->lun)) == 0) { 772 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 773 sc->sc_nexus = ecb; 774 esp_select(sc, ecb); 775 break; 776 } else 777 ESP_MISC(("%d:%d busy\n", 778 sc_link->target, sc_link->lun)); 779 } 780 } 781 782 void 783 esp_sense(sc, ecb) 784 struct esp_softc *sc; 785 struct esp_ecb *ecb; 786 { 787 struct scsi_xfer *xs = ecb->xs; 788 struct scsi_link *sc_link = xs->sc_link; 789 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 790 struct scsi_sense *ss = (void *)&ecb->cmd; 791 792 ESP_MISC(("requesting sense ")); 793 /* Next, setup a request sense command block */ 794 bzero(ss, sizeof(*ss)); 795 ss->opcode = REQUEST_SENSE; 796 ss->byte2 = sc_link->lun << 5; 797 ss->length = sizeof(struct scsi_sense_data); 798 ecb->clen = sizeof(*ss); 799 ecb->daddr = (char *)&xs->sense; 800 ecb->dleft = sizeof(struct scsi_sense_data); 801 ecb->flags |= ECB_SENSE; 802 ti->senses++; 803 if (ecb->flags & ECB_NEXUS) 804 ti->lubusy &= ~(1 << sc_link->lun); 805 if (ecb == sc->sc_nexus) { 806 esp_select(sc, ecb); 807 } else { 808 esp_dequeue(sc, ecb); 809 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 810 if (sc->sc_state == ESP_IDLE) 811 esp_sched(sc); 812 } 813 } 814 815 /* 816 * POST PROCESSING OF SCSI_CMD (usually current) 817 */ 818 void 819 esp_done(sc, ecb) 820 struct esp_softc *sc; 821 struct esp_ecb *ecb; 822 { 823 struct scsi_xfer *xs = ecb->xs; 824 struct scsi_link *sc_link = xs->sc_link; 825 struct esp_tinfo *ti = &sc->sc_tinfo[sc_link->target]; 826 827 ESP_TRACE(("[esp_done(error:%x)] ", xs->error)); 828 829 /* 830 * Now, if we've come here with no error code, i.e. we've kept the 831 * initial XS_NOERROR, and the status code signals that we should 832 * check sense, we'll need to set up a request sense cmd block and 833 * push the command back into the ready queue *before* any other 834 * commands for this target/lunit, else we lose the sense info. 835 * We don't support chk sense conditions for the request sense cmd. 836 */ 837 if (xs->error == XS_NOERROR) { 838 if ((ecb->flags & ECB_ABORT) != 0) { 839 xs->error = XS_DRIVER_STUFFUP; 840 } else if ((ecb->flags & ECB_SENSE) != 0) { 841 xs->error = XS_SENSE; 842 } else if ((ecb->stat & ST_MASK) == SCSI_CHECK) { 843 /* First, save the return values */ 844 xs->resid = ecb->dleft; 845 xs->status = ecb->stat; 846 esp_sense(sc, ecb); 847 return; 848 } else { 849 xs->resid = ecb->dleft; 850 } 851 } 852 853 xs->flags |= ITSDONE; 854 855 #ifdef ESP_DEBUG 856 if (esp_debug & ESP_SHOWMISC) { 857 if (xs->resid != 0) 858 printf("resid=%d ", xs->resid); 859 if (xs->error == XS_SENSE) 860 printf("sense=0x%02x\n", xs->sense.error_code); 861 else 862 printf("error=%d\n", xs->error); 863 } 864 #endif 865 866 /* 867 * Remove the ECB from whatever queue it's on. 868 */ 869 if (ecb->flags & ECB_NEXUS) 870 ti->lubusy &= ~(1 << sc_link->lun); 871 if (ecb == sc->sc_nexus) { 872 sc->sc_nexus = NULL; 873 sc->sc_state = ESP_IDLE; 874 esp_sched(sc); 875 } else 876 esp_dequeue(sc, ecb); 877 878 esp_free_ecb(sc, ecb, xs->flags); 879 ti->cmds++; 880 scsi_done(xs); 881 } 882 883 void 884 esp_dequeue(sc, ecb) 885 struct esp_softc *sc; 886 struct esp_ecb *ecb; 887 { 888 889 if (ecb->flags & ECB_NEXUS) { 890 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 891 } else { 892 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 893 } 894 } 895 896 /* 897 * INTERRUPT/PROTOCOL ENGINE 898 */ 899 900 /* 901 * Schedule an outgoing message by prioritizing it, and asserting 902 * attention on the bus. We can only do this when we are the initiator 903 * else there will be an illegal command interrupt. 904 */ 905 #define esp_sched_msgout(m) \ 906 do { \ 907 ESP_MISC(("esp_sched_msgout %d ", m)); \ 908 ESPCMD(sc, ESPCMD_SETATN); \ 909 sc->sc_flags |= ESP_ATN; \ 910 sc->sc_msgpriq |= (m); \ 911 } while (0) 912 913 int 914 esp_reselect(sc, message) 915 struct esp_softc *sc; 916 int message; 917 { 918 u_char selid, target, lun; 919 struct esp_ecb *ecb; 920 struct scsi_link *sc_link; 921 struct esp_tinfo *ti; 922 923 /* 924 * The SCSI chip made a snapshot of the data bus while the reselection 925 * was being negotiated. This enables us to determine which target did 926 * the reselect. 927 */ 928 selid = sc->sc_selid & ~(1 << sc->sc_id); 929 if (selid & (selid - 1)) { 930 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 931 sc->sc_dev.dv_xname, selid); 932 goto reset; 933 } 934 935 /* 936 * Search wait queue for disconnected cmd 937 * The list should be short, so I haven't bothered with 938 * any more sophisticated structures than a simple 939 * singly linked list. 940 */ 941 target = ffs(selid) - 1; 942 lun = message & 0x07; 943 for (ecb = sc->nexus_list.tqh_first; ecb != NULL; 944 ecb = ecb->chain.tqe_next) { 945 sc_link = ecb->xs->sc_link; 946 if (sc_link->target == target && sc_link->lun == lun) 947 break; 948 } 949 if (ecb == NULL) { 950 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 951 sc->sc_dev.dv_xname, target, lun); 952 goto abort; 953 } 954 955 /* Make this nexus active again. */ 956 TAILQ_REMOVE(&sc->nexus_list, ecb, chain); 957 sc->sc_state = ESP_CONNECTED; 958 sc->sc_nexus = ecb; 959 ti = &sc->sc_tinfo[target]; 960 ti->lubusy |= (1 << lun); 961 esp_setsync(sc, ti); 962 963 if (ecb->flags & ECB_RESET) 964 esp_sched_msgout(SEND_DEV_RESET); 965 else if (ecb->flags & ECB_ABORT) 966 esp_sched_msgout(SEND_ABORT); 967 968 /* Do an implicit RESTORE POINTERS. */ 969 sc->sc_dp = ecb->daddr; 970 sc->sc_dleft = ecb->dleft; 971 972 return (0); 973 974 reset: 975 esp_sched_msgout(SEND_DEV_RESET); 976 return (1); 977 978 abort: 979 esp_sched_msgout(SEND_ABORT); 980 return (1); 981 } 982 983 #define IS1BYTEMSG(m) (((m) != 1 && (m) < 0x20) || (m) & 0x80) 984 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 985 #define ISEXTMSG(m) ((m) == 1) 986 987 /* 988 * Get an incoming message as initiator. 989 * 990 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 991 * byte in the FIFO 992 */ 993 void 994 esp_msgin(sc) 995 register struct esp_softc *sc; 996 { 997 register int v; 998 999 ESP_TRACE(("[esp_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1000 1001 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) == 0) { 1002 printf("%s: msgin: no msg byte available\n", 1003 sc->sc_dev.dv_xname); 1004 return; 1005 } 1006 1007 /* 1008 * Prepare for a new message. A message should (according 1009 * to the SCSI standard) be transmitted in one single 1010 * MESSAGE_IN_PHASE. If we have been in some other phase, 1011 * then this is a new message. 1012 */ 1013 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1014 sc->sc_flags &= ~ESP_DROP_MSGI; 1015 sc->sc_imlen = 0; 1016 } 1017 1018 v = ESP_READ_REG(sc, ESP_FIFO); 1019 ESP_MISC(("<msgbyte:0x%02x>", v)); 1020 1021 #if 0 1022 if (sc->sc_state == ESP_RESELECTED && sc->sc_imlen == 0) { 1023 /* 1024 * Which target is reselecting us? (The ID bit really) 1025 */ 1026 sc->sc_selid = v; 1027 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1028 return; 1029 } 1030 #endif 1031 1032 sc->sc_imess[sc->sc_imlen] = v; 1033 1034 /* 1035 * If we're going to reject the message, don't bother storing 1036 * the incoming bytes. But still, we need to ACK them. 1037 */ 1038 1039 if ((sc->sc_flags & ESP_DROP_MSGI)) { 1040 ESPCMD(sc, ESPCMD_MSGOK); 1041 printf("<dropping msg byte %x>", 1042 sc->sc_imess[sc->sc_imlen]); 1043 return; 1044 } 1045 1046 if (sc->sc_imlen >= ESP_MAX_MSG_LEN) { 1047 esp_sched_msgout(SEND_REJECT); 1048 sc->sc_flags |= ESP_DROP_MSGI; 1049 } else { 1050 sc->sc_imlen++; 1051 /* 1052 * This testing is suboptimal, but most 1053 * messages will be of the one byte variety, so 1054 * it should not effect performance 1055 * significantly. 1056 */ 1057 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1058 goto gotit; 1059 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1060 goto gotit; 1061 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1062 sc->sc_imlen == sc->sc_imess[1] + 2) 1063 goto gotit; 1064 } 1065 /* Ack what we have so far */ 1066 ESPCMD(sc, ESPCMD_MSGOK); 1067 return; 1068 1069 gotit: 1070 ESP_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1071 /* 1072 * Now we should have a complete message (1 byte, 2 byte 1073 * and moderately long extended messages). We only handle 1074 * extended messages which total length is shorter than 1075 * ESP_MAX_MSG_LEN. Longer messages will be amputated. 1076 */ 1077 switch (sc->sc_state) { 1078 struct esp_ecb *ecb; 1079 struct esp_tinfo *ti; 1080 1081 case ESP_CONNECTED: 1082 ecb = sc->sc_nexus; 1083 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1084 1085 switch (sc->sc_imess[0]) { 1086 case MSG_CMDCOMPLETE: 1087 ESP_MSGS(("cmdcomplete ")); 1088 if (sc->sc_dleft < 0) { 1089 struct scsi_link *sc_link = ecb->xs->sc_link; 1090 printf("%s: %ld extra bytes from %d:%d\n", 1091 sc->sc_dev.dv_xname, -(long)sc->sc_dleft, 1092 sc_link->target, sc_link->lun); 1093 sc->sc_dleft = 0; 1094 } 1095 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1096 sc->sc_state = ESP_CMDCOMPLETE; 1097 break; 1098 1099 case MSG_MESSAGE_REJECT: 1100 if (esp_debug & ESP_SHOWMSGS) 1101 printf("%s: our msg rejected by target\n", 1102 sc->sc_dev.dv_xname); 1103 switch (sc->sc_msgout) { 1104 case SEND_SDTR: 1105 sc->sc_flags &= ~ESP_SYNCHNEGO; 1106 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1107 esp_setsync(sc, ti); 1108 break; 1109 case SEND_INIT_DET_ERR: 1110 goto abort; 1111 } 1112 break; 1113 1114 case MSG_NOOP: 1115 ESP_MSGS(("noop ")); 1116 break; 1117 1118 case MSG_DISCONNECT: 1119 ESP_MSGS(("disconnect ")); 1120 ti->dconns++; 1121 sc->sc_state = ESP_DISCONNECT; 1122 if ((ecb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1123 break; 1124 /*FALLTHROUGH*/ 1125 1126 case MSG_SAVEDATAPOINTER: 1127 ESP_MSGS(("save datapointer ")); 1128 ecb->daddr = sc->sc_dp; 1129 ecb->dleft = sc->sc_dleft; 1130 break; 1131 1132 case MSG_RESTOREPOINTERS: 1133 ESP_MSGS(("restore datapointer ")); 1134 sc->sc_dp = ecb->daddr; 1135 sc->sc_dleft = ecb->dleft; 1136 break; 1137 1138 case MSG_EXTENDED: 1139 ESP_MSGS(("extended(%x) ", sc->sc_imess[2])); 1140 switch (sc->sc_imess[2]) { 1141 case MSG_EXT_SDTR: 1142 ESP_MSGS(("SDTR period %d, offset %d ", 1143 sc->sc_imess[3], sc->sc_imess[4])); 1144 if (sc->sc_imess[1] != 3) 1145 goto reject; 1146 ti->period = sc->sc_imess[3]; 1147 ti->offset = sc->sc_imess[4]; 1148 ti->flags &= ~T_NEGOTIATE; 1149 if (sc->sc_minsync == 0 || 1150 ti->offset == 0 || 1151 ti->period > 124) { 1152 printf("%s:%d: async\n", "esp", 1153 ecb->xs->sc_link->target); 1154 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1155 /* target initiated negotiation */ 1156 ti->offset = 0; 1157 ti->flags &= ~T_SYNCMODE; 1158 esp_sched_msgout(SEND_SDTR); 1159 } else { 1160 /* we are async */ 1161 ti->flags &= ~T_SYNCMODE; 1162 } 1163 } else { 1164 int r = 250/ti->period; 1165 int s = (100*250)/ti->period - 100*r; 1166 int p; 1167 1168 p = esp_stp2cpb(sc, ti->period); 1169 ti->period = esp_cpb2stp(sc, p); 1170 #ifdef ESP_DEBUG 1171 sc_print_addr(ecb->xs->sc_link); 1172 printf("max sync rate %d.%02dMb/s\n", 1173 r, s); 1174 #endif 1175 if ((sc->sc_flags&ESP_SYNCHNEGO) == 0) { 1176 /* target initiated negotiation */ 1177 if (ti->period < sc->sc_minsync) 1178 ti->period = sc->sc_minsync; 1179 if (ti->offset > 15) 1180 ti->offset = 15; 1181 ti->flags &= ~T_SYNCMODE; 1182 esp_sched_msgout(SEND_SDTR); 1183 } else { 1184 /* we are sync */ 1185 ti->flags |= T_SYNCMODE; 1186 } 1187 } 1188 sc->sc_flags &= ~ESP_SYNCHNEGO; 1189 esp_setsync(sc, ti); 1190 break; 1191 1192 default: 1193 printf("%s: unrecognized MESSAGE EXTENDED; sending REJECT\n", 1194 sc->sc_dev.dv_xname); 1195 goto reject; 1196 } 1197 break; 1198 1199 default: 1200 ESP_MSGS(("ident ")); 1201 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1202 sc->sc_dev.dv_xname); 1203 reject: 1204 esp_sched_msgout(SEND_REJECT); 1205 break; 1206 } 1207 break; 1208 1209 case ESP_RESELECTED: 1210 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1211 printf("%s: reselect without IDENTIFY; sending DEVICE RESET\n", 1212 sc->sc_dev.dv_xname); 1213 goto reset; 1214 } 1215 1216 (void) esp_reselect(sc, sc->sc_imess[0]); 1217 break; 1218 1219 default: 1220 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1221 sc->sc_dev.dv_xname); 1222 reset: 1223 esp_sched_msgout(SEND_DEV_RESET); 1224 break; 1225 1226 abort: 1227 esp_sched_msgout(SEND_ABORT); 1228 break; 1229 } 1230 1231 /* Ack last message byte */ 1232 ESPCMD(sc, ESPCMD_MSGOK); 1233 1234 /* Done, reset message pointer. */ 1235 sc->sc_flags &= ~ESP_DROP_MSGI; 1236 sc->sc_imlen = 0; 1237 } 1238 1239 1240 /* 1241 * Send the highest priority, scheduled message 1242 */ 1243 void 1244 esp_msgout(sc) 1245 register struct esp_softc *sc; 1246 { 1247 struct esp_tinfo *ti; 1248 struct esp_ecb *ecb; 1249 size_t size; 1250 1251 ESP_TRACE(("[esp_msgout(priq:%x, prevphase:%x)]", sc->sc_msgpriq, sc->sc_prevphase)); 1252 1253 if (sc->sc_flags & ESP_ATN) { 1254 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 1255 new: 1256 ESPCMD(sc, ESPCMD_FLUSH); 1257 DELAY(1); 1258 sc->sc_msgoutq = 0; 1259 sc->sc_omlen = 0; 1260 } 1261 } else { 1262 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1263 esp_sched_msgout(sc->sc_msgoutq); 1264 goto new; 1265 } else { 1266 printf("esp at line %d: unexpected MESSAGE OUT phase\n", __LINE__); 1267 } 1268 } 1269 1270 if (sc->sc_omlen == 0) { 1271 /* Pick up highest priority message */ 1272 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1273 sc->sc_msgoutq |= sc->sc_msgout; 1274 sc->sc_msgpriq &= ~sc->sc_msgout; 1275 sc->sc_omlen = 1; /* "Default" message len */ 1276 switch (sc->sc_msgout) { 1277 case SEND_SDTR: 1278 ecb = sc->sc_nexus; 1279 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1280 sc->sc_omess[0] = MSG_EXTENDED; 1281 sc->sc_omess[1] = 3; 1282 sc->sc_omess[2] = MSG_EXT_SDTR; 1283 sc->sc_omess[3] = ti->period; 1284 sc->sc_omess[4] = ti->offset; 1285 sc->sc_omlen = 5; 1286 if ((sc->sc_flags & ESP_SYNCHNEGO) == 0) { 1287 ti->flags |= T_SYNCMODE; 1288 esp_setsync(sc, ti); 1289 } 1290 break; 1291 case SEND_IDENTIFY: 1292 if (sc->sc_state != ESP_CONNECTED) { 1293 printf("esp at line %d: no nexus\n", __LINE__); 1294 } 1295 ecb = sc->sc_nexus; 1296 sc->sc_omess[0] = MSG_IDENTIFY(ecb->xs->sc_link->lun,0); 1297 break; 1298 case SEND_DEV_RESET: 1299 sc->sc_flags |= ESP_ABORTING; 1300 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1301 ecb = sc->sc_nexus; 1302 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1303 ti->flags &= ~T_SYNCMODE; 1304 ti->flags |= T_NEGOTIATE; 1305 break; 1306 case SEND_PARITY_ERROR: 1307 sc->sc_omess[0] = MSG_PARITY_ERROR; 1308 break; 1309 case SEND_ABORT: 1310 sc->sc_flags |= ESP_ABORTING; 1311 sc->sc_omess[0] = MSG_ABORT; 1312 break; 1313 case SEND_INIT_DET_ERR: 1314 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1315 break; 1316 case SEND_REJECT: 1317 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1318 break; 1319 default: 1320 ESPCMD(sc, ESPCMD_RSTATN); 1321 sc->sc_flags &= ~ESP_ATN; 1322 sc->sc_omess[0] = MSG_NOOP; 1323 break; 1324 } 1325 sc->sc_omp = sc->sc_omess; 1326 } 1327 1328 #if 1 1329 /* (re)send the message */ 1330 size = min(sc->sc_omlen, sc->sc_maxxfer); 1331 DMA_SETUP(sc->sc_dma, &sc->sc_omp, &sc->sc_omlen, 0, &size); 1332 /* Program the SCSI counter */ 1333 ESP_WRITE_REG(sc, ESP_TCL, size); 1334 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1335 if (sc->sc_cfg2 & ESPCFG2_FE) { 1336 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1337 } 1338 /* load the count in */ 1339 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1340 ESPCMD(sc, ESPCMD_TRANS|ESPCMD_DMA); 1341 DMA_GO(sc->sc_dma); 1342 #else 1343 { int i; 1344 for (i = 0; i < sc->sc_omlen; i++) 1345 ESP_WRITE_REG(sc, FIFO, sc->sc_omess[i]); 1346 ESPCMD(sc, ESPCMD_TRANS); 1347 sc->sc_omlen = 0; 1348 } 1349 #endif 1350 } 1351 1352 /* 1353 * This is the most critical part of the driver, and has to know 1354 * how to deal with *all* error conditions and phases from the SCSI 1355 * bus. If there are no errors and the DMA was active, then call the 1356 * DMA pseudo-interrupt handler. If this returns 1, then that was it 1357 * and we can return from here without further processing. 1358 * 1359 * Most of this needs verifying. 1360 */ 1361 int 1362 espintr(sc) 1363 register struct esp_softc *sc; 1364 { 1365 register struct esp_ecb *ecb; 1366 register struct scsi_link *sc_link; 1367 struct esp_tinfo *ti; 1368 int loop; 1369 size_t size; 1370 1371 ESP_TRACE(("[espintr]")); 1372 1373 /* 1374 * I have made some (maybe seriously flawed) assumptions here, 1375 * but basic testing (uncomment the printf() below), show that 1376 * certainly something happens when this loop is here. 1377 * 1378 * The idea is that many of the SCSI operations take very little 1379 * time, and going away and getting interrupted is too high an 1380 * overhead to pay. For example, selecting, sending a message 1381 * and command and then doing some work can be done in one "pass". 1382 * 1383 * The DELAY is not variable because I do not understand that the 1384 * DELAY loop should be fixed-time regardless of CPU speed, but 1385 * I am *assuming* that the faster SCSI processors get things done 1386 * quicker (sending a command byte etc), and so there is no 1387 * need to be too slow. 1388 * 1389 * This is a heuristic. It is 2 when at 20Mhz, 2 at 25Mhz and 1 1390 * at 40Mhz. This needs testing. 1391 */ 1392 for (loop = 0; 1;loop++, DELAY(50/sc->sc_freq)) { 1393 /* a feeling of deja-vu */ 1394 if (!DMA_ISINTR(sc->sc_dma)) 1395 return (loop != 0); 1396 #if 0 1397 if (loop) 1398 printf("*"); 1399 #endif 1400 1401 /* and what do the registers say... */ 1402 espreadregs(sc); 1403 1404 sc->sc_intrcnt.ev_count++; 1405 1406 /* 1407 * At the moment, only a SCSI Bus Reset or Illegal 1408 * Command are classed as errors. A disconnect is a 1409 * valid condition, and we let the code check is the 1410 * "ESP_BUSFREE_OK" flag was set before declaring it 1411 * and error. 1412 * 1413 * Also, the status register tells us about "Gross 1414 * Errors" and "Parity errors". Only the Gross Error 1415 * is really bad, and the parity errors are dealt 1416 * with later 1417 * 1418 * TODO 1419 * If there are too many parity error, go to slow 1420 * cable mode ? 1421 */ 1422 1423 /* SCSI Reset */ 1424 if (sc->sc_espintr & ESPINTR_SBR) { 1425 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1426 ESPCMD(sc, ESPCMD_FLUSH); 1427 DELAY(1); 1428 } 1429 if (sc->sc_state != ESP_SBR) { 1430 printf("%s: SCSI bus reset\n", 1431 sc->sc_dev.dv_xname); 1432 esp_init(sc, 0); /* Restart everything */ 1433 return 1; 1434 } 1435 #if 0 1436 /*XXX*/ printf("<expected bus reset: " 1437 "[intr %x, stat %x, step %d]>\n", 1438 sc->sc_espintr, sc->sc_espstat, 1439 sc->sc_espstep); 1440 #endif 1441 if (sc->sc_nexus) 1442 panic("%s: nexus in reset state", 1443 sc->sc_dev.dv_xname); 1444 goto sched; 1445 } 1446 1447 ecb = sc->sc_nexus; 1448 1449 #define ESPINTR_ERR (ESPINTR_SBR|ESPINTR_ILL) 1450 if (sc->sc_espintr & ESPINTR_ERR || 1451 sc->sc_espstat & ESPSTAT_GE) { 1452 1453 if (sc->sc_espstat & ESPSTAT_GE) { 1454 /* no target ? */ 1455 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1456 ESPCMD(sc, ESPCMD_FLUSH); 1457 DELAY(1); 1458 } 1459 if (sc->sc_state == ESP_CONNECTED || 1460 sc->sc_state == ESP_SELECTING) { 1461 ecb->xs->error = XS_DRIVER_STUFFUP; 1462 esp_done(sc, ecb); 1463 } 1464 return 1; 1465 } 1466 1467 if (sc->sc_espintr & ESPINTR_ILL) { 1468 /* illegal command, out of sync ? */ 1469 printf("%s: illegal command: 0x%x (state %d, phase %x, prevphase %x)\n", 1470 sc->sc_dev.dv_xname, sc->sc_lastcmd, 1471 sc->sc_state, sc->sc_phase, 1472 sc->sc_prevphase); 1473 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1474 ESPCMD(sc, ESPCMD_FLUSH); 1475 DELAY(1); 1476 } 1477 esp_init(sc, 0); /* Restart everything */ 1478 return 1; 1479 } 1480 } 1481 1482 /* 1483 * Call if DMA is active. 1484 * 1485 * If DMA_INTR returns true, then maybe go 'round the loop 1486 * again in case there is no more DMA queued, but a phase 1487 * change is expected. 1488 */ 1489 if (DMA_ISACTIVE(sc->sc_dma)) { 1490 int r = DMA_INTR(sc->sc_dma); 1491 if (r == -1) { 1492 printf("%s: DMA error; resetting\n", 1493 sc->sc_dev.dv_xname); 1494 esp_init(sc, 1); 1495 } 1496 /* If DMA active here, then go back to work... */ 1497 if (DMA_ISACTIVE(sc->sc_dma)) 1498 return 1; 1499 1500 if (sc->sc_dleft == 0 && 1501 (sc->sc_espstat & ESPSTAT_TC) == 0) 1502 printf("%s: !TC [intr %x, stat %x, step %d]" 1503 " prevphase %x, resid %x\n", 1504 sc->sc_dev.dv_xname, 1505 sc->sc_espintr, 1506 sc->sc_espstat, 1507 sc->sc_espstep, 1508 sc->sc_prevphase, 1509 ecb?ecb->dleft:-1); 1510 } 1511 1512 #if 0 /* Unreliable on some ESP revisions? */ 1513 if ((sc->sc_espstat & ESPSTAT_INT) == 0) { 1514 printf("%s: spurious interrupt\n", sc->sc_dev.dv_xname); 1515 return 1; 1516 } 1517 #endif 1518 1519 /* 1520 * check for less serious errors 1521 */ 1522 if (sc->sc_espstat & ESPSTAT_PE) { 1523 printf("%s: SCSI bus parity error\n", 1524 sc->sc_dev.dv_xname); 1525 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 1526 esp_sched_msgout(SEND_PARITY_ERROR); 1527 else 1528 esp_sched_msgout(SEND_INIT_DET_ERR); 1529 } 1530 1531 if (sc->sc_espintr & ESPINTR_DIS) { 1532 ESP_MISC(("<DISC [intr %x, stat %x, step %d]>", 1533 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 1534 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1535 ESPCMD(sc, ESPCMD_FLUSH); 1536 DELAY(1); 1537 } 1538 /* 1539 * This command must (apparently) be issued within 1540 * 250mS of a disconnect. So here you are... 1541 */ 1542 ESPCMD(sc, ESPCMD_ENSEL); 1543 switch (sc->sc_state) { 1544 case ESP_RESELECTED: 1545 goto sched; 1546 1547 case ESP_SELECTING: 1548 ecb->xs->error = XS_SELTIMEOUT; 1549 goto finish; 1550 1551 case ESP_CONNECTED: 1552 if ((sc->sc_flags & ESP_SYNCHNEGO)) { 1553 #ifdef ESP_DEBUG 1554 if (ecb) 1555 sc_print_addr(ecb->xs->sc_link); 1556 printf("sync nego not completed!\n"); 1557 #endif 1558 ti = &sc->sc_tinfo[ecb->xs->sc_link->target]; 1559 sc->sc_flags &= ~ESP_SYNCHNEGO; 1560 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1561 } 1562 1563 /* it may be OK to disconnect */ 1564 if ((sc->sc_flags & ESP_ABORTING) == 0) { 1565 /* 1566 * Section 5.1.1 of the SCSI 2 spec 1567 * suggests issuing a REQUEST SENSE 1568 * following an unexpected disconnect. 1569 * Some devices go into a contingent 1570 * allegiance condition when 1571 * disconnecting, and this is necessary 1572 * to clean up their state. 1573 */ 1574 printf("%s: unexpected disconnect; ", 1575 sc->sc_dev.dv_xname); 1576 if (ecb->flags & ECB_SENSE) { 1577 printf("resetting\n"); 1578 goto reset; 1579 } 1580 printf("sending REQUEST SENSE\n"); 1581 esp_sense(sc, ecb); 1582 goto out; 1583 } 1584 1585 ecb->xs->error = XS_DRIVER_STUFFUP; 1586 goto finish; 1587 1588 case ESP_DISCONNECT: 1589 TAILQ_INSERT_HEAD(&sc->nexus_list, ecb, chain); 1590 sc->sc_nexus = NULL; 1591 goto sched; 1592 1593 case ESP_CMDCOMPLETE: 1594 goto finish; 1595 } 1596 } 1597 1598 switch (sc->sc_state) { 1599 1600 case ESP_SBR: 1601 printf("%s: waiting for SCSI Bus Reset to happen\n", 1602 sc->sc_dev.dv_xname); 1603 return 1; 1604 1605 case ESP_RESELECTED: 1606 /* 1607 * we must be continuing a message ? 1608 */ 1609 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1610 printf("%s: target didn't identify\n", 1611 sc->sc_dev.dv_xname); 1612 esp_init(sc, 1); 1613 return 1; 1614 } 1615 printf("<<RESELECT CONT'd>>"); 1616 #if XXXX 1617 esp_msgin(sc); 1618 if (sc->sc_state != ESP_CONNECTED) { 1619 /* IDENTIFY fail?! */ 1620 printf("%s: identify failed\n", 1621 sc->sc_dev.dv_xname); 1622 esp_init(sc, 1); 1623 return 1; 1624 } 1625 #endif 1626 break; 1627 1628 case ESP_IDLE: 1629 if (sc->sc_flags & ESP_ICCS) printf("[[esp: BUMMER]]"); 1630 case ESP_SELECTING: 1631 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1632 sc->sc_flags = 0; 1633 1634 if (sc->sc_espintr & ESPINTR_RESEL) { 1635 /* 1636 * If we're trying to select a 1637 * target ourselves, push our command 1638 * back into the ready list. 1639 */ 1640 if (sc->sc_state == ESP_SELECTING) { 1641 ESP_MISC(("backoff selector ")); 1642 sc_link = sc->sc_nexus->xs->sc_link; 1643 ti = &sc->sc_tinfo[sc_link->target]; 1644 TAILQ_INSERT_HEAD(&sc->ready_list, 1645 sc->sc_nexus, chain); 1646 ecb = sc->sc_nexus = NULL; 1647 } 1648 sc->sc_state = ESP_RESELECTED; 1649 if (sc->sc_phase != MESSAGE_IN_PHASE) { 1650 /* 1651 * Things are seriously fucked up. 1652 * Pull the brakes, i.e. reset 1653 */ 1654 printf("%s: target didn't identify\n", 1655 sc->sc_dev.dv_xname); 1656 esp_init(sc, 1); 1657 return 1; 1658 } 1659 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1660 printf("%s: RESELECT: %d bytes in FIFO!\n", 1661 sc->sc_dev.dv_xname, 1662 ESP_READ_REG(sc, ESP_FFLAG) & 1663 ESPFIFO_FF); 1664 esp_init(sc, 1); 1665 return 1; 1666 } 1667 sc->sc_selid = ESP_READ_REG(sc, ESP_FIFO); 1668 ESP_MISC(("selid=0x%2x ", sc->sc_selid)); 1669 esp_msgin(sc); /* Handle identify message */ 1670 if (sc->sc_state != ESP_CONNECTED) { 1671 /* IDENTIFY fail?! */ 1672 printf("%s: identify failed\n", 1673 sc->sc_dev.dv_xname); 1674 esp_init(sc, 1); 1675 return 1; 1676 } 1677 continue; /* ie. next phase expected soon */ 1678 } 1679 1680 #define ESPINTR_DONE (ESPINTR_FC|ESPINTR_BS) 1681 if ((sc->sc_espintr & ESPINTR_DONE) == ESPINTR_DONE) { 1682 ecb = sc->sc_nexus; 1683 if (!ecb) 1684 panic("esp: not nexus at sc->sc_nexus"); 1685 1686 sc_link = ecb->xs->sc_link; 1687 ti = &sc->sc_tinfo[sc_link->target]; 1688 1689 switch (sc->sc_espstep) { 1690 case 0: 1691 printf("%s: select timeout/no disconnect\n", 1692 sc->sc_dev.dv_xname); 1693 ecb->xs->error = XS_SELTIMEOUT; 1694 goto finish; 1695 case 1: 1696 if ((ti->flags & T_NEGOTIATE) == 0) { 1697 printf("%s: step 1 & !NEG\n", 1698 sc->sc_dev.dv_xname); 1699 goto reset; 1700 } 1701 if (sc->sc_phase != MESSAGE_OUT_PHASE) { 1702 printf("%s: !MSGOUT\n", 1703 sc->sc_dev.dv_xname); 1704 goto reset; 1705 } 1706 /* Start negotiating */ 1707 ti->period = sc->sc_minsync; 1708 ti->offset = 15; 1709 sc->sc_flags |= ESP_SYNCHNEGO; 1710 esp_sched_msgout(SEND_SDTR); 1711 break; 1712 case 3: 1713 /* 1714 * Grr, this is supposed to mean 1715 * "target left command phase 1716 * prematurely". It seems to happen 1717 * regularly when sync mode is on. 1718 * Look at FIFO to see if command 1719 * went out. 1720 * (Timing problems?) 1721 */ 1722 if ((ESP_READ_REG(sc, ESP_FFLAG)&ESPFIFO_FF) == 0) { 1723 /* Hope for the best.. */ 1724 break; 1725 } 1726 printf("(%s:%d:%d): selection failed;" 1727 " %d left in FIFO " 1728 "[intr %x, stat %x, step %d]\n", 1729 sc->sc_dev.dv_xname, 1730 sc_link->target, 1731 sc_link->lun, 1732 ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF, 1733 sc->sc_espintr, sc->sc_espstat, 1734 sc->sc_espstep); 1735 ESPCMD(sc, ESPCMD_FLUSH); 1736 esp_sched_msgout(SEND_ABORT); 1737 return 1; 1738 case 2: 1739 /* Select stuck at Command Phase */ 1740 ESPCMD(sc, ESPCMD_FLUSH); 1741 case 4: 1742 /* So far, everything went fine */ 1743 break; 1744 } 1745 #if 0 1746 if (ecb->xs->flags & SCSI_RESET) 1747 esp_sched_msgout(SEND_DEV_RESET); 1748 else if (ti->flags & T_NEGOTIATE) 1749 esp_sched_msgout( 1750 SEND_IDENTIFY | SEND_SDTR); 1751 else 1752 esp_sched_msgout(SEND_IDENTIFY); 1753 #endif 1754 1755 ecb->flags |= ECB_NEXUS; 1756 ti->lubusy |= (1 << sc_link->lun); 1757 1758 sc->sc_prevphase = INVALID_PHASE; /* ?? */ 1759 /* Do an implicit RESTORE POINTERS. */ 1760 sc->sc_dp = ecb->daddr; 1761 sc->sc_dleft = ecb->dleft; 1762 1763 /* On our first connection, schedule a timeout. */ 1764 if ((ecb->xs->flags & SCSI_POLL) == 0) 1765 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 1766 1767 sc->sc_state = ESP_CONNECTED; 1768 break; 1769 } else { 1770 printf("%s: unexpected status after select" 1771 ": [intr %x, stat %x, step %x]\n", 1772 sc->sc_dev.dv_xname, 1773 sc->sc_espintr, sc->sc_espstat, 1774 sc->sc_espstep); 1775 ESPCMD(sc, ESPCMD_FLUSH); 1776 DELAY(1); 1777 goto reset; 1778 } 1779 if (sc->sc_state == ESP_IDLE) { 1780 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 1781 return 0; 1782 } 1783 break; 1784 1785 case ESP_CONNECTED: 1786 if (sc->sc_flags & ESP_ICCS) { 1787 u_char msg; 1788 1789 sc->sc_flags &= ~ESP_ICCS; 1790 1791 if (!(sc->sc_espintr & ESPINTR_DONE)) { 1792 printf("%s: ICCS: " 1793 ": [intr %x, stat %x, step %x]\n", 1794 sc->sc_dev.dv_xname, 1795 sc->sc_espintr, sc->sc_espstat, 1796 sc->sc_espstep); 1797 } 1798 if ((ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) != 2) { 1799 int i = (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) - 2; 1800 while (i--) 1801 (void) ESP_READ_REG(sc, ESP_FIFO); 1802 } 1803 ecb->stat = ESP_READ_REG(sc, ESP_FIFO); 1804 msg = ESP_READ_REG(sc, ESP_FIFO); 1805 ESP_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 1806 if (msg == MSG_CMDCOMPLETE) { 1807 ecb->xs->resid = ecb->dleft = sc->sc_dleft; 1808 sc->sc_state = ESP_CMDCOMPLETE; 1809 } else 1810 printf("%s: STATUS_PHASE: msg %d\n", 1811 sc->sc_dev.dv_xname, msg); 1812 ESPCMD(sc, ESPCMD_MSGOK); 1813 continue; /* ie. wait for disconnect */ 1814 } 1815 break; 1816 default: 1817 panic("%s: invalid state: %d", 1818 sc->sc_dev.dv_xname, 1819 sc->sc_state); 1820 } 1821 1822 /* 1823 * Driver is now in state ESP_CONNECTED, i.e. we 1824 * have a current command working the SCSI bus. 1825 */ 1826 if (sc->sc_state != ESP_CONNECTED || ecb == NULL) { 1827 panic("esp no nexus"); 1828 } 1829 1830 switch (sc->sc_phase) { 1831 case MESSAGE_OUT_PHASE: 1832 ESP_PHASE(("MESSAGE_OUT_PHASE ")); 1833 esp_msgout(sc); 1834 sc->sc_prevphase = MESSAGE_OUT_PHASE; 1835 break; 1836 case MESSAGE_IN_PHASE: 1837 ESP_PHASE(("MESSAGE_IN_PHASE ")); 1838 if (sc->sc_espintr & ESPINTR_BS) { 1839 ESPCMD(sc, ESPCMD_FLUSH); 1840 sc->sc_flags |= ESP_WAITI; 1841 ESPCMD(sc, ESPCMD_TRANS); 1842 } else if (sc->sc_espintr & ESPINTR_FC) { 1843 if ((sc->sc_flags & ESP_WAITI) == 0) { 1844 printf("%s: MSGIN: unexpected FC bit: " 1845 "[intr %x, stat %x, step %x]\n", 1846 sc->sc_dev.dv_xname, 1847 sc->sc_espintr, sc->sc_espstat, 1848 sc->sc_espstep); 1849 } 1850 sc->sc_flags &= ~ESP_WAITI; 1851 esp_msgin(sc); 1852 } else { 1853 printf("%s: MSGIN: weird bits: " 1854 "[intr %x, stat %x, step %x]\n", 1855 sc->sc_dev.dv_xname, 1856 sc->sc_espintr, sc->sc_espstat, 1857 sc->sc_espstep); 1858 } 1859 sc->sc_prevphase = MESSAGE_IN_PHASE; 1860 break; 1861 case COMMAND_PHASE: { 1862 /* well, this means send the command again */ 1863 u_char *cmd = (u_char *)&ecb->cmd; 1864 int i; 1865 1866 ESP_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 1867 ecb->cmd.opcode, ecb->clen)); 1868 if (ESP_READ_REG(sc, ESP_FFLAG) & ESPFIFO_FF) { 1869 ESPCMD(sc, ESPCMD_FLUSH); 1870 DELAY(1); 1871 } 1872 /* Now the command into the FIFO */ 1873 for (i = 0; i < ecb->clen; i++) 1874 ESP_WRITE_REG(sc, ESP_FIFO, *cmd++); 1875 ESPCMD(sc, ESPCMD_TRANS); 1876 sc->sc_prevphase = COMMAND_PHASE; 1877 } 1878 break; 1879 case DATA_OUT_PHASE: 1880 ESP_PHASE(("DATA_OUT_PHASE [%ld] ",(long)sc->sc_dleft)); 1881 ESPCMD(sc, ESPCMD_FLUSH); 1882 size = min(sc->sc_dleft, sc->sc_maxxfer); 1883 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 1884 0, &size); 1885 sc->sc_prevphase = DATA_OUT_PHASE; 1886 goto setup_xfer; 1887 case DATA_IN_PHASE: 1888 ESP_PHASE(("DATA_IN_PHASE ")); 1889 if (sc->sc_rev == ESP100) 1890 ESPCMD(sc, ESPCMD_FLUSH); 1891 size = min(sc->sc_dleft, sc->sc_maxxfer); 1892 DMA_SETUP(sc->sc_dma, &sc->sc_dp, &sc->sc_dleft, 1893 1, &size); 1894 sc->sc_prevphase = DATA_IN_PHASE; 1895 setup_xfer: 1896 /* Program the SCSI counter */ 1897 ESP_WRITE_REG(sc, ESP_TCL, size); 1898 ESP_WRITE_REG(sc, ESP_TCM, size >> 8); 1899 if (sc->sc_cfg2 & ESPCFG2_FE) { 1900 ESP_WRITE_REG(sc, ESP_TCH, size >> 16); 1901 } 1902 /* load the count in */ 1903 ESPCMD(sc, ESPCMD_NOP|ESPCMD_DMA); 1904 1905 /* 1906 * Note that if `size' is 0, we've already transceived 1907 * all the bytes we want but we're still in DATA PHASE. 1908 * Apparently, the device needs padding. Also, a 1909 * transfer size of 0 means "maximum" to the chip 1910 * DMA logic. 1911 */ 1912 ESPCMD(sc, 1913 (size==0?ESPCMD_TRPAD:ESPCMD_TRANS)|ESPCMD_DMA); 1914 DMA_GO(sc->sc_dma); 1915 return 1; 1916 case STATUS_PHASE: 1917 ESP_PHASE(("STATUS_PHASE ")); 1918 sc->sc_flags |= ESP_ICCS; 1919 ESPCMD(sc, ESPCMD_ICCS); 1920 sc->sc_prevphase = STATUS_PHASE; 1921 break; 1922 case INVALID_PHASE: 1923 break; 1924 default: 1925 printf("%s: unexpected bus phase; resetting\n", 1926 sc->sc_dev.dv_xname); 1927 goto reset; 1928 } 1929 } 1930 panic("esp: should not get here.."); 1931 1932 reset: 1933 esp_init(sc, 1); 1934 return 1; 1935 1936 finish: 1937 untimeout(esp_timeout, ecb); 1938 esp_done(sc, ecb); 1939 goto out; 1940 1941 sched: 1942 sc->sc_state = ESP_IDLE; 1943 esp_sched(sc); 1944 goto out; 1945 1946 out: 1947 return 1; 1948 } 1949 1950 void 1951 esp_abort(sc, ecb) 1952 struct esp_softc *sc; 1953 struct esp_ecb *ecb; 1954 { 1955 1956 /* 2 secs for the abort */ 1957 ecb->timeout = ESP_ABORT_TIMEOUT; 1958 ecb->flags |= ECB_ABORT; 1959 1960 if (ecb == sc->sc_nexus) { 1961 /* 1962 * If we're still selecting, the message will be scheduled 1963 * after selection is complete. 1964 */ 1965 if (sc->sc_state == ESP_CONNECTED) 1966 esp_sched_msgout(SEND_ABORT); 1967 1968 /* 1969 * Reschedule timeout. First, cancel a queued timeout (if any) 1970 * in case someone decides to call esp_abort() from elsewhere. 1971 */ 1972 untimeout(esp_timeout, ecb); 1973 timeout(esp_timeout, ecb, (ecb->timeout * hz) / 1000); 1974 } else { 1975 esp_dequeue(sc, ecb); 1976 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1977 if (sc->sc_state == ESP_IDLE) 1978 esp_sched(sc); 1979 } 1980 } 1981 1982 void 1983 esp_timeout(arg) 1984 void *arg; 1985 { 1986 struct esp_ecb *ecb = arg; 1987 struct scsi_xfer *xs = ecb->xs; 1988 struct scsi_link *sc_link = xs->sc_link; 1989 struct esp_softc *sc = sc_link->adapter_softc; 1990 int s; 1991 1992 sc_print_addr(sc_link); 1993 printf("%s: timed out [ecb %p (flags 0x%x, dleft %x, stat %x)], " 1994 "<state %d, nexus %p, phase(c %x, p %x), resid %lx, msg(q %x,o %x) %s>", 1995 sc->sc_dev.dv_xname, 1996 ecb, ecb->flags, ecb->dleft, ecb->stat, 1997 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 1998 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 1999 DMA_ISACTIVE(sc->sc_dma) ? "DMA active" : ""); 2000 #if ESP_DEBUG > 0 2001 printf("TRACE: %s.", ecb->trace); 2002 #endif 2003 2004 s = splbio(); 2005 2006 if (ecb->flags & ECB_ABORT) { 2007 /* abort timed out */ 2008 printf(" AGAIN\n"); 2009 esp_init(sc, 1); 2010 } else { 2011 /* abort the operation that has timed out */ 2012 printf("\n"); 2013 xs->error = XS_TIMEOUT; 2014 esp_abort(sc, ecb); 2015 } 2016 2017 splx(s); 2018 } 2019
Indexes created Tue Sep 30 11:09:46 GMT 2025