esp.c revision 1.10
1 /* $NetBSD: esp.c,v 1.10 1999/04/08 04:46:41 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/buf.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/autoconf.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 #include <sun3/dev/dmareg.h> 63 #include <sun3/dev/dmavar.h> 64 65 #define ESP_REG_SIZE (12*4) 66 67 struct esp_softc { 68 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 69 volatile u_char *sc_reg; /* the registers */ 70 struct dma_softc *sc_dma; /* pointer to my dma */ 71 }; 72 73 static int espmatch __P((struct device *, struct cfdata *, void *)); 74 static void espattach __P((struct device *, struct device *, void *)); 75 76 struct cfattach esp_ca = { 77 sizeof(struct esp_softc), espmatch, espattach 78 }; 79 80 static struct scsipi_device esp_dev = { 81 NULL, /* Use default error handler */ 82 NULL, /* have a queue, served by this */ 83 NULL, /* have no async handler */ 84 NULL, /* Use default 'done' routine */ 85 }; 86 87 /* 88 * Functions and the switch for the MI code. 89 */ 90 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 91 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 92 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 93 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 94 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 95 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 96 size_t *, int, size_t *)); 97 static void esp_dma_go __P((struct ncr53c9x_softc *)); 98 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 99 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 100 101 static struct ncr53c9x_glue esp_glue = { 102 esp_read_reg, 103 esp_write_reg, 104 esp_dma_isintr, 105 esp_dma_reset, 106 esp_dma_intr, 107 esp_dma_setup, 108 esp_dma_go, 109 esp_dma_stop, 110 esp_dma_isactive, 111 NULL, /* gl_clear_latched_intr */ 112 }; 113 114 static int 115 espmatch(parent, cf, aux) 116 struct device *parent; 117 struct cfdata *cf; 118 void *aux; 119 { 120 struct confargs *ca = aux; 121 122 /* 123 * Check for the esp registers. 124 */ 125 if (bus_peek(ca->ca_bustype, 126 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 127 return (0); 128 129 /* If default ipl, fill it in. */ 130 if (ca->ca_intpri == -1) 131 ca->ca_intpri = 2; 132 133 return (1); 134 } 135 136 static void 137 espattach(parent, self, aux) 138 struct device *parent, *self; 139 void *aux; 140 { 141 struct confargs *ca = aux; 142 struct esp_softc *esc = (void *)self; 143 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 144 145 /* 146 * Set up glue for MI code early; we use some of it here. 147 */ 148 sc->sc_glue = &esp_glue; 149 150 /* 151 * Map in the ESP registers. 152 */ 153 esc->sc_reg = 154 bus_mapin(ca->ca_bustype, ca->ca_paddr, ESP_REG_SIZE); 155 156 /* Other settings */ 157 sc->sc_id = 7; 158 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 159 160 /* 161 * Hook up the DMA driver. 162 */ 163 esc->sc_dma = espdmafind(sc->sc_dev.dv_unit); 164 esc->sc_dma->sc_esp = sc; /* Point back to us */ 165 166 /* 167 * XXX More of this should be in ncr53c9x_attach(), but 168 * XXX should we really poke around the chip that much in 169 * XXX the MI code? Think about this more... 170 */ 171 172 /* 173 * It is necessary to try to load the 2nd config register here, 174 * to find out what rev the esp chip is, else the ncr53c9x_reset 175 * will not set up the defaults correctly. 176 */ 177 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 178 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 179 sc->sc_cfg3 = NCRCFG3_CDB; 180 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 181 182 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 183 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 184 sc->sc_rev = NCR_VARIANT_ESP100; 185 } else { 186 sc->sc_cfg2 = NCRCFG2_SCSI2; 187 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 188 sc->sc_cfg3 = 0; 189 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 190 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 191 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 192 if (NCR_READ_REG(sc, NCR_CFG3) != 193 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 194 sc->sc_rev = NCR_VARIANT_ESP100A; 195 } else { 196 /* NCRCFG2_FE enables > 64K transfers */ 197 sc->sc_cfg2 |= NCRCFG2_FE; 198 sc->sc_cfg3 = 0; 199 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 200 sc->sc_rev = NCR_VARIANT_ESP200; 201 } 202 } 203 204 /* 205 * XXX minsync and maxxfer _should_ be set up in MI code, 206 * XXX but it appears to have some dependency on what sort 207 * XXX of DMA we're hooked up to, etc. 208 */ 209 210 /* 211 * This is the value used to start sync negotiations 212 * Note that the NCR register "SYNCTP" is programmed 213 * in "clocks per byte", and has a minimum value of 4. 214 * The SCSI period used in negotiation is one-fourth 215 * of the time (in nanoseconds) needed to transfer one byte. 216 * Since the chip's clock is given in MHz, we have the following 217 * formula: 4 * period = (1000 / freq) * 4 218 */ 219 sc->sc_minsync = 1000 / sc->sc_freq; 220 221 /* 222 * Alas, we must now modify the value a bit, because it's 223 * only valid when can switch on FASTCLK and FASTSCSI bits 224 * in config register 3... 225 */ 226 switch (sc->sc_rev) { 227 case NCR_VARIANT_ESP100: 228 sc->sc_maxxfer = 64 * 1024; 229 sc->sc_minsync = 0; /* No synch on old chip? */ 230 break; 231 232 case NCR_VARIANT_ESP100A: 233 sc->sc_maxxfer = 64 * 1024; 234 /* Min clocks/byte is 5 */ 235 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 236 break; 237 238 case NCR_VARIANT_ESP200: 239 sc->sc_maxxfer = 16 * 1024 * 1024; 240 /* XXX - do actually set FAST* bits */ 241 break; 242 } 243 244 /* and the interuppts */ 245 isr_add_autovect((void*)ncr53c9x_intr, sc, ca->ca_intpri); 246 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 247 248 /* Do the common parts of attachment. */ 249 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 250 sc->sc_adapter.scsipi_minphys = minphys; 251 ncr53c9x_attach(sc, &esp_dev); 252 253 #if 0 254 /* XXX - This doesn't work yet. Not sure why... */ 255 /* Turn on target selection using the `dma' method */ 256 ncr53c9x_dmaselect = 1; /* XXX - OK? */ 257 #endif 258 } 259 260 261 /* 262 * Glue functions. 263 */ 264 265 u_char 266 esp_read_reg(sc, reg) 267 struct ncr53c9x_softc *sc; 268 int reg; 269 { 270 struct esp_softc *esc = (struct esp_softc *)sc; 271 272 return (esc->sc_reg[reg * 4]); 273 } 274 275 void 276 esp_write_reg(sc, reg, val) 277 struct ncr53c9x_softc *sc; 278 int reg; 279 u_char val; 280 { 281 struct esp_softc *esc = (struct esp_softc *)sc; 282 283 esc->sc_reg[reg * 4] = val; 284 } 285 286 int 287 esp_dma_isintr(sc) 288 struct ncr53c9x_softc *sc; 289 { 290 struct esp_softc *esc = (struct esp_softc *)sc; 291 u_int32_t csr; 292 293 csr = DMACSR(esc->sc_dma); 294 return (csr & (D_INT_PEND|D_ERR_PEND)); 295 } 296 297 void 298 esp_dma_reset(sc) 299 struct ncr53c9x_softc *sc; 300 { 301 struct esp_softc *esc = (struct esp_softc *)sc; 302 303 dma_reset(esc->sc_dma); 304 } 305 306 int 307 esp_dma_intr(sc) 308 struct ncr53c9x_softc *sc; 309 { 310 struct esp_softc *esc = (struct esp_softc *)sc; 311 312 return (espdmaintr(esc->sc_dma)); 313 } 314 315 int 316 esp_dma_setup(sc, addr, len, datain, dmasize) 317 struct ncr53c9x_softc *sc; 318 caddr_t *addr; 319 size_t *len; 320 int datain; 321 size_t *dmasize; 322 { 323 struct esp_softc *esc = (struct esp_softc *)sc; 324 325 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 326 } 327 328 void 329 esp_dma_go(sc) 330 struct ncr53c9x_softc *sc; 331 { 332 struct esp_softc *esc = (struct esp_softc *)sc; 333 334 /* Start DMA */ 335 DMACSR(esc->sc_dma) |= D_EN_DMA; 336 esc->sc_dma->sc_active = 1; 337 } 338 339 void 340 esp_dma_stop(sc) 341 struct ncr53c9x_softc *sc; 342 { 343 struct esp_softc *esc = (struct esp_softc *)sc; 344 345 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 346 } 347 348 int 349 esp_dma_isactive(sc) 350 struct ncr53c9x_softc *sc; 351 { 352 struct esp_softc *esc = (struct esp_softc *)sc; 353 354 return (esc->sc_dma->sc_active); 355 } 356
Indexes created Tue Sep 30 06:09:59 GMT 2025