esp.c revision 1.18
1 /* $NetBSD: esp.c,v 1.18 2003/07/15 03:36:14 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.18 2003/07/15 03:36:14 lukem Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/autoconf.h> 61 62 #include <dev/ic/ncr53c9xreg.h> 63 #include <dev/ic/ncr53c9xvar.h> 64 65 #include <sun3/dev/dmareg.h> 66 #include <sun3/dev/dmavar.h> 67 68 #define ESP_REG_SIZE (12*4) 69 70 struct esp_softc { 71 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 72 volatile u_char *sc_reg; /* the registers */ 73 struct dma_softc *sc_dma; /* pointer to my dma */ 74 }; 75 76 static int espmatch __P((struct device *, struct cfdata *, void *)); 77 static void espattach __P((struct device *, struct device *, void *)); 78 79 CFATTACH_DECL(esp, sizeof(struct esp_softc), 80 espmatch, espattach, NULL, NULL); 81 82 /* 83 * Functions and the switch for the MI code. 84 */ 85 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 86 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 87 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 88 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 89 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 90 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 91 size_t *, int, size_t *)); 92 static void esp_dma_go __P((struct ncr53c9x_softc *)); 93 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 94 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 95 96 static struct ncr53c9x_glue esp_glue = { 97 esp_read_reg, 98 esp_write_reg, 99 esp_dma_isintr, 100 esp_dma_reset, 101 esp_dma_intr, 102 esp_dma_setup, 103 esp_dma_go, 104 esp_dma_stop, 105 esp_dma_isactive, 106 NULL, /* gl_clear_latched_intr */ 107 }; 108 109 static int 110 espmatch(parent, cf, aux) 111 struct device *parent; 112 struct cfdata *cf; 113 void *aux; 114 { 115 struct confargs *ca = aux; 116 117 /* 118 * Check for the esp registers. 119 */ 120 if (bus_peek(ca->ca_bustype, 121 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 122 return (0); 123 124 /* If default ipl, fill it in. */ 125 if (ca->ca_intpri == -1) 126 ca->ca_intpri = 2; 127 128 return (1); 129 } 130 131 static void 132 espattach(parent, self, aux) 133 struct device *parent, *self; 134 void *aux; 135 { 136 struct confargs *ca = aux; 137 struct esp_softc *esc = (void *)self; 138 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 139 140 /* 141 * Set up glue for MI code early; we use some of it here. 142 */ 143 sc->sc_glue = &esp_glue; 144 145 /* 146 * Map in the ESP registers. 147 */ 148 esc->sc_reg = 149 bus_mapin(ca->ca_bustype, ca->ca_paddr, ESP_REG_SIZE); 150 151 /* Other settings */ 152 sc->sc_id = 7; 153 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 154 155 /* 156 * Hook up the DMA driver. 157 */ 158 esc->sc_dma = espdmafind(sc->sc_dev.dv_unit); 159 esc->sc_dma->sc_esp = sc; /* Point back to us */ 160 161 /* 162 * XXX More of this should be in ncr53c9x_attach(), but 163 * XXX should we really poke around the chip that much in 164 * XXX the MI code? Think about this more... 165 */ 166 167 /* 168 * It is necessary to try to load the 2nd config register here, 169 * to find out what rev the esp chip is, else the ncr53c9x_reset 170 * will not set up the defaults correctly. 171 */ 172 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 173 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 174 sc->sc_cfg3 = NCRCFG3_CDB; 175 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 176 177 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 178 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 179 sc->sc_rev = NCR_VARIANT_ESP100; 180 } else { 181 sc->sc_cfg2 = NCRCFG2_SCSI2; 182 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 183 sc->sc_cfg3 = 0; 184 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 185 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 186 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 187 if (NCR_READ_REG(sc, NCR_CFG3) != 188 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 189 sc->sc_rev = NCR_VARIANT_ESP100A; 190 } else { 191 /* NCRCFG2_FE enables > 64K transfers */ 192 sc->sc_cfg2 |= NCRCFG2_FE; 193 sc->sc_cfg3 = 0; 194 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 195 sc->sc_rev = NCR_VARIANT_ESP200; 196 } 197 } 198 199 /* 200 * XXX minsync and maxxfer _should_ be set up in MI code, 201 * XXX but it appears to have some dependency on what sort 202 * XXX of DMA we're hooked up to, etc. 203 */ 204 205 /* 206 * This is the value used to start sync negotiations 207 * Note that the NCR register "SYNCTP" is programmed 208 * in "clocks per byte", and has a minimum value of 4. 209 * The SCSI period used in negotiation is one-fourth 210 * of the time (in nanoseconds) needed to transfer one byte. 211 * Since the chip's clock is given in MHz, we have the following 212 * formula: 4 * period = (1000 / freq) * 4 213 */ 214 sc->sc_minsync = 1000 / sc->sc_freq; 215 216 /* 217 * Alas, we must now modify the value a bit, because it's 218 * only valid when can switch on FASTCLK and FASTSCSI bits 219 * in config register 3... 220 */ 221 switch (sc->sc_rev) { 222 case NCR_VARIANT_ESP100: 223 sc->sc_maxxfer = 64 * 1024; 224 sc->sc_minsync = 0; /* No synch on old chip? */ 225 break; 226 227 case NCR_VARIANT_ESP100A: 228 sc->sc_maxxfer = 64 * 1024; 229 /* Min clocks/byte is 5 */ 230 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 231 break; 232 233 case NCR_VARIANT_ESP200: 234 sc->sc_maxxfer = 16 * 1024 * 1024; 235 /* XXX - do actually set FAST* bits */ 236 break; 237 } 238 239 /* and the interuppts */ 240 isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri); 241 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 242 sc->sc_dev.dv_xname, "intr"); 243 244 /* Do the common parts of attachment. */ 245 sc->sc_adapter.adapt_minphys = minphys; 246 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 247 ncr53c9x_attach(sc); 248 249 #if 0 250 /* XXX - This doesn't work yet. Not sure why... */ 251 /* Turn on target selection using the `dma' method */ 252 sc->sc_features |= NCR_F_DMASELECT; /* XXX - OK? */ 253 #endif 254 } 255 256 257 /* 258 * Glue functions. 259 */ 260 261 u_char 262 esp_read_reg(sc, reg) 263 struct ncr53c9x_softc *sc; 264 int reg; 265 { 266 struct esp_softc *esc = (struct esp_softc *)sc; 267 268 return (esc->sc_reg[reg * 4]); 269 } 270 271 void 272 esp_write_reg(sc, reg, val) 273 struct ncr53c9x_softc *sc; 274 int reg; 275 u_char val; 276 { 277 struct esp_softc *esc = (struct esp_softc *)sc; 278 279 esc->sc_reg[reg * 4] = val; 280 } 281 282 int 283 esp_dma_isintr(sc) 284 struct ncr53c9x_softc *sc; 285 { 286 struct esp_softc *esc = (struct esp_softc *)sc; 287 u_int32_t csr; 288 289 csr = DMACSR(esc->sc_dma); 290 return (csr & (D_INT_PEND|D_ERR_PEND)); 291 } 292 293 void 294 esp_dma_reset(sc) 295 struct ncr53c9x_softc *sc; 296 { 297 struct esp_softc *esc = (struct esp_softc *)sc; 298 299 dma_reset(esc->sc_dma); 300 } 301 302 int 303 esp_dma_intr(sc) 304 struct ncr53c9x_softc *sc; 305 { 306 struct esp_softc *esc = (struct esp_softc *)sc; 307 308 return (espdmaintr(esc->sc_dma)); 309 } 310 311 int 312 esp_dma_setup(sc, addr, len, datain, dmasize) 313 struct ncr53c9x_softc *sc; 314 caddr_t *addr; 315 size_t *len; 316 int datain; 317 size_t *dmasize; 318 { 319 struct esp_softc *esc = (struct esp_softc *)sc; 320 321 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 322 } 323 324 void 325 esp_dma_go(sc) 326 struct ncr53c9x_softc *sc; 327 { 328 struct esp_softc *esc = (struct esp_softc *)sc; 329 330 /* Start DMA */ 331 DMACSR(esc->sc_dma) |= D_EN_DMA; 332 esc->sc_dma->sc_active = 1; 333 } 334 335 void 336 esp_dma_stop(sc) 337 struct ncr53c9x_softc *sc; 338 { 339 struct esp_softc *esc = (struct esp_softc *)sc; 340 341 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 342 } 343 344 int 345 esp_dma_isactive(sc) 346 struct ncr53c9x_softc *sc; 347 { 348 struct esp_softc *esc = (struct esp_softc *)sc; 349 350 return (esc->sc_dma->sc_active); 351 } 352
Indexes created Tue Sep 30 06:09:59 GMT 2025