esp.c revision 1.20
1 /* $NetBSD: esp.c,v 1.20 2005/01/30 03:52:41 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.20 2005/01/30 03:52:41 tsutsui Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/autoconf.h> 61 62 #include <dev/ic/ncr53c9xreg.h> 63 #include <dev/ic/ncr53c9xvar.h> 64 65 #include <sun3/dev/dmareg.h> 66 #include <sun3/dev/dmavar.h> 67 68 #define ESP_REG_SIZE (12*4) 69 70 struct esp_softc { 71 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 72 volatile u_char *sc_reg; /* the registers */ 73 struct dma_softc *sc_dma; /* pointer to my dma */ 74 }; 75 76 static int espmatch(struct device *, struct cfdata *, void *); 77 static void espattach(struct device *, struct device *, void *); 78 79 CFATTACH_DECL(esp, sizeof(struct esp_softc), 80 espmatch, espattach, NULL, NULL); 81 82 /* 83 * Functions and the switch for the MI code. 84 */ 85 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 86 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 87 static int esp_dma_isintr(struct ncr53c9x_softc *); 88 static void esp_dma_reset(struct ncr53c9x_softc *); 89 static int esp_dma_intr(struct ncr53c9x_softc *); 90 static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, 91 size_t *); 92 static void esp_dma_go(struct ncr53c9x_softc *); 93 static void esp_dma_stop(struct ncr53c9x_softc *); 94 static int esp_dma_isactive(struct ncr53c9x_softc *); 95 96 static struct ncr53c9x_glue esp_glue = { 97 esp_read_reg, 98 esp_write_reg, 99 esp_dma_isintr, 100 esp_dma_reset, 101 esp_dma_intr, 102 esp_dma_setup, 103 esp_dma_go, 104 esp_dma_stop, 105 esp_dma_isactive, 106 NULL, /* gl_clear_latched_intr */ 107 }; 108 109 static int 110 espmatch(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 struct confargs *ca = aux; 113 114 /* 115 * Check for the esp registers. 116 */ 117 if (bus_peek(ca->ca_bustype, 118 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 119 return (0); 120 121 /* If default ipl, fill it in. */ 122 if (ca->ca_intpri == -1) 123 ca->ca_intpri = 2; 124 125 return (1); 126 } 127 128 static void 129 espattach(struct device *parent, struct device *self, void *aux) 130 { 131 struct confargs *ca = aux; 132 struct esp_softc *esc = (void *)self; 133 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 134 135 /* 136 * Set up glue for MI code early; we use some of it here. 137 */ 138 sc->sc_glue = &esp_glue; 139 140 /* 141 * Map in the ESP registers. 142 */ 143 esc->sc_reg = 144 bus_mapin(ca->ca_bustype, ca->ca_paddr, ESP_REG_SIZE); 145 146 /* Other settings */ 147 sc->sc_id = 7; 148 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 149 150 /* 151 * Hook up the DMA driver. 152 */ 153 esc->sc_dma = espdmafind(sc->sc_dev.dv_unit); 154 esc->sc_dma->sc_esp = sc; /* Point back to us */ 155 156 /* 157 * XXX More of this should be in ncr53c9x_attach(), but 158 * XXX should we really poke around the chip that much in 159 * XXX the MI code? Think about this more... 160 */ 161 162 /* 163 * It is necessary to try to load the 2nd config register here, 164 * to find out what rev the esp chip is, else the ncr53c9x_reset 165 * will not set up the defaults correctly. 166 */ 167 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 168 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 169 sc->sc_cfg3 = NCRCFG3_CDB; 170 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 171 172 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 173 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 174 sc->sc_rev = NCR_VARIANT_ESP100; 175 } else { 176 sc->sc_cfg2 = NCRCFG2_SCSI2; 177 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 178 sc->sc_cfg3 = 0; 179 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 180 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 181 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 182 if (NCR_READ_REG(sc, NCR_CFG3) != 183 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 184 sc->sc_rev = NCR_VARIANT_ESP100A; 185 } else { 186 /* NCRCFG2_FE enables > 64K transfers */ 187 sc->sc_cfg2 |= NCRCFG2_FE; 188 sc->sc_cfg3 = 0; 189 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 190 sc->sc_rev = NCR_VARIANT_ESP200; 191 } 192 } 193 194 /* 195 * XXX minsync and maxxfer _should_ be set up in MI code, 196 * XXX but it appears to have some dependency on what sort 197 * XXX of DMA we're hooked up to, etc. 198 */ 199 200 /* 201 * This is the value used to start sync negotiations 202 * Note that the NCR register "SYNCTP" is programmed 203 * in "clocks per byte", and has a minimum value of 4. 204 * The SCSI period used in negotiation is one-fourth 205 * of the time (in nanoseconds) needed to transfer one byte. 206 * Since the chip's clock is given in MHz, we have the following 207 * formula: 4 * period = (1000 / freq) * 4 208 */ 209 sc->sc_minsync = 1000 / sc->sc_freq; 210 211 /* 212 * Alas, we must now modify the value a bit, because it's 213 * only valid when can switch on FASTCLK and FASTSCSI bits 214 * in config register 3... 215 */ 216 switch (sc->sc_rev) { 217 case NCR_VARIANT_ESP100: 218 sc->sc_maxxfer = 64 * 1024; 219 sc->sc_minsync = 0; /* No synch on old chip? */ 220 break; 221 222 case NCR_VARIANT_ESP100A: 223 sc->sc_maxxfer = 64 * 1024; 224 /* Min clocks/byte is 5 */ 225 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 226 break; 227 228 case NCR_VARIANT_ESP200: 229 sc->sc_maxxfer = 16 * 1024 * 1024; 230 /* XXX - do actually set FAST* bits */ 231 break; 232 } 233 234 /* and the interuppts */ 235 isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri); 236 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 237 sc->sc_dev.dv_xname, "intr"); 238 239 /* Do the common parts of attachment. */ 240 sc->sc_adapter.adapt_minphys = minphys; 241 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 242 ncr53c9x_attach(sc); 243 244 /* Turn on target selection using the `dma' method */ 245 sc->sc_features |= NCR_F_DMASELECT; 246 } 247 248 249 /* 250 * Glue functions. 251 */ 252 253 u_char 254 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 255 { 256 struct esp_softc *esc = (struct esp_softc *)sc; 257 258 return (esc->sc_reg[reg * 4]); 259 } 260 261 void 262 esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 263 { 264 struct esp_softc *esc = (struct esp_softc *)sc; 265 266 esc->sc_reg[reg * 4] = val; 267 } 268 269 int 270 esp_dma_isintr(struct ncr53c9x_softc *sc) 271 { 272 struct esp_softc *esc = (struct esp_softc *)sc; 273 uint32_t csr; 274 275 csr = DMACSR(esc->sc_dma); 276 return (csr & (D_INT_PEND|D_ERR_PEND)); 277 } 278 279 void 280 esp_dma_reset(struct ncr53c9x_softc *sc) 281 { 282 struct esp_softc *esc = (struct esp_softc *)sc; 283 284 dma_reset(esc->sc_dma); 285 } 286 287 int 288 esp_dma_intr(struct ncr53c9x_softc *sc) 289 { 290 struct esp_softc *esc = (struct esp_softc *)sc; 291 292 return (espdmaintr(esc->sc_dma)); 293 } 294 295 int 296 esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, int datain, 297 size_t *dmasize) 298 { 299 struct esp_softc *esc = (struct esp_softc *)sc; 300 301 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 302 } 303 304 void 305 esp_dma_go(struct ncr53c9x_softc *sc) 306 { 307 struct esp_softc *esc = (struct esp_softc *)sc; 308 309 /* Start DMA */ 310 DMACSR(esc->sc_dma) |= D_EN_DMA; 311 esc->sc_dma->sc_active = 1; 312 } 313 314 void 315 esp_dma_stop(struct ncr53c9x_softc *sc) 316 { 317 struct esp_softc *esc = (struct esp_softc *)sc; 318 319 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 320 } 321 322 int 323 esp_dma_isactive(struct ncr53c9x_softc *sc) 324 { 325 struct esp_softc *esc = (struct esp_softc *)sc; 326 327 return (esc->sc_dma->sc_active); 328 } 329
Indexes created Tue Sep 30 06:09:59 GMT 2025