esp.c revision 1.24
1 /* $NetBSD: esp.c,v 1.24 2007/01/23 15:58:22 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.24 2007/01/23 15:58:22 tsutsui Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/autoconf.h> 61 #include <machine/bus.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <sun3/dev/dmareg.h> 67 #include <sun3/dev/dmavar.h> 68 69 #define ESP_REG_SIZE (12*4) 70 71 struct esp_softc { 72 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 73 bus_space_tag_t sc_bst; /* bus space tag */ 74 bus_space_handle_t sc_bsh; /* bus space handle */ 75 struct dma_softc *sc_dma; /* pointer to my dma */ 76 }; 77 78 static int espmatch(struct device *, struct cfdata *, void *); 79 static void espattach(struct device *, struct device *, void *); 80 81 CFATTACH_DECL(esp, sizeof(struct esp_softc), 82 espmatch, espattach, NULL, NULL); 83 84 /* 85 * Functions and the switch for the MI code. 86 */ 87 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 88 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 89 static int esp_dma_isintr(struct ncr53c9x_softc *); 90 static void esp_dma_reset(struct ncr53c9x_softc *); 91 static int esp_dma_intr(struct ncr53c9x_softc *); 92 static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, 93 size_t *); 94 static void esp_dma_go(struct ncr53c9x_softc *); 95 static void esp_dma_stop(struct ncr53c9x_softc *); 96 static int esp_dma_isactive(struct ncr53c9x_softc *); 97 98 static struct ncr53c9x_glue esp_glue = { 99 esp_read_reg, 100 esp_write_reg, 101 esp_dma_isintr, 102 esp_dma_reset, 103 esp_dma_intr, 104 esp_dma_setup, 105 esp_dma_go, 106 esp_dma_stop, 107 esp_dma_isactive, 108 NULL, /* gl_clear_latched_intr */ 109 }; 110 111 static int 112 espmatch(struct device *parent, struct cfdata *cf, void *aux) 113 { 114 struct confargs *ca = aux; 115 116 /* 117 * Check for the esp registers. 118 */ 119 if (bus_peek(ca->ca_bustype, 120 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 121 return (0); 122 123 /* If default ipl, fill it in. */ 124 if (ca->ca_intpri == -1) 125 ca->ca_intpri = 2; 126 127 return (1); 128 } 129 130 static void 131 espattach(struct device *parent, struct device *self, void *aux) 132 { 133 struct confargs *ca = aux; 134 struct esp_softc *esc = (void *)self; 135 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 136 137 /* 138 * Set up glue for MI code early; we use some of it here. 139 */ 140 sc->sc_glue = &esp_glue; 141 142 /* 143 * Map the ESP registers. 144 */ 145 esc->sc_bst = ca->ca_bustag; 146 if (bus_space_map(esc->sc_bst, ca->ca_paddr, ESP_REG_SIZE, 0, 147 &esc->sc_bsh) != 0) { 148 printf(": can't map register\n"); 149 return; 150 } 151 152 /* Other settings */ 153 sc->sc_id = 7; 154 sc->sc_freq = 20; /* The 3/80 esp runs at 20 MHz */ 155 156 /* 157 * Hook up the DMA driver. 158 */ 159 esc->sc_dma = espdmafind(device_unit(&sc->sc_dev)); 160 esc->sc_dma->sc_esp = sc; /* Point back to us */ 161 162 /* 163 * XXX More of this should be in ncr53c9x_attach(), but 164 * XXX should we really poke around the chip that much in 165 * XXX the MI code? Think about this more... 166 */ 167 168 /* 169 * It is necessary to try to load the 2nd config register here, 170 * to find out what rev the esp chip is, else the ncr53c9x_reset 171 * will not set up the defaults correctly. 172 */ 173 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 174 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 175 sc->sc_cfg3 = NCRCFG3_CDB; 176 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 177 178 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 179 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 180 sc->sc_rev = NCR_VARIANT_ESP100; 181 } else { 182 sc->sc_cfg2 = NCRCFG2_SCSI2; 183 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 184 sc->sc_cfg3 = 0; 185 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 186 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 187 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 188 if (NCR_READ_REG(sc, NCR_CFG3) != 189 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 190 sc->sc_rev = NCR_VARIANT_ESP100A; 191 } else { 192 /* NCRCFG2_FE enables > 64K transfers */ 193 sc->sc_cfg2 |= NCRCFG2_FE; 194 sc->sc_cfg3 = 0; 195 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 196 sc->sc_rev = NCR_VARIANT_ESP200; 197 } 198 } 199 200 /* 201 * XXX minsync and maxxfer _should_ be set up in MI code, 202 * XXX but it appears to have some dependency on what sort 203 * XXX of DMA we're hooked up to, etc. 204 */ 205 206 /* 207 * This is the value used to start sync negotiations 208 * Note that the NCR register "SYNCTP" is programmed 209 * in "clocks per byte", and has a minimum value of 4. 210 * The SCSI period used in negotiation is one-fourth 211 * of the time (in nanoseconds) needed to transfer one byte. 212 * Since the chip's clock is given in MHz, we have the following 213 * formula: 4 * period = (1000 / freq) * 4 214 */ 215 sc->sc_minsync = 1000 / sc->sc_freq; 216 217 /* 218 * Alas, we must now modify the value a bit, because it's 219 * only valid when can switch on FASTCLK and FASTSCSI bits 220 * in config register 3... 221 */ 222 switch (sc->sc_rev) { 223 case NCR_VARIANT_ESP100: 224 sc->sc_maxxfer = 64 * 1024; 225 sc->sc_minsync = 0; /* No synch on old chip? */ 226 break; 227 228 case NCR_VARIANT_ESP100A: 229 sc->sc_maxxfer = 64 * 1024; 230 /* Min clocks/byte is 5 */ 231 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 232 break; 233 234 case NCR_VARIANT_ESP200: 235 sc->sc_maxxfer = 16 * 1024 * 1024; 236 /* XXX - do actually set FAST* bits */ 237 break; 238 } 239 240 /* and the interuppts */ 241 isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri); 242 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 243 sc->sc_dev.dv_xname, "intr"); 244 245 /* Do the common parts of attachment. */ 246 sc->sc_adapter.adapt_minphys = minphys; 247 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 248 ncr53c9x_attach(sc); 249 250 /* Turn on target selection using the `dma' method */ 251 sc->sc_features |= NCR_F_DMASELECT; 252 } 253 254 255 /* 256 * Glue functions. 257 */ 258 259 u_char 260 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 261 { 262 struct esp_softc *esc = (struct esp_softc *)sc; 263 264 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4); 265 } 266 267 void 268 esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 269 { 270 struct esp_softc *esc = (struct esp_softc *)sc; 271 272 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4, val); 273 } 274 275 int 276 esp_dma_isintr(struct ncr53c9x_softc *sc) 277 { 278 struct esp_softc *esc = (struct esp_softc *)sc; 279 uint32_t csr; 280 281 csr = DMACSR(esc->sc_dma); 282 return (csr & (D_INT_PEND|D_ERR_PEND)); 283 } 284 285 void 286 esp_dma_reset(struct ncr53c9x_softc *sc) 287 { 288 struct esp_softc *esc = (struct esp_softc *)sc; 289 290 dma_reset(esc->sc_dma); 291 } 292 293 int 294 esp_dma_intr(struct ncr53c9x_softc *sc) 295 { 296 struct esp_softc *esc = (struct esp_softc *)sc; 297 298 return (espdmaintr(esc->sc_dma)); 299 } 300 301 int 302 esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, int datain, 303 size_t *dmasize) 304 { 305 struct esp_softc *esc = (struct esp_softc *)sc; 306 307 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 308 } 309 310 void 311 esp_dma_go(struct ncr53c9x_softc *sc) 312 { 313 struct esp_softc *esc = (struct esp_softc *)sc; 314 315 /* Start DMA */ 316 DMACSR(esc->sc_dma) |= D_EN_DMA; 317 esc->sc_dma->sc_active = 1; 318 } 319 320 void 321 esp_dma_stop(struct ncr53c9x_softc *sc) 322 { 323 struct esp_softc *esc = (struct esp_softc *)sc; 324 325 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 326 } 327 328 int 329 esp_dma_isactive(struct ncr53c9x_softc *sc) 330 { 331 struct esp_softc *esc = (struct esp_softc *)sc; 332 333 return (esc->sc_dma->sc_active); 334 } 335
Indexes created Tue Sep 30 06:09:59 GMT 2025