esp.c revision 1.3
1 /* $NetBSD: esp.c,v 1.3 1997/03/20 16:01:40 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 #include <sys/malloc.h> 56 57 #include <scsi/scsi_all.h> 58 #include <scsi/scsiconf.h> 59 #include <scsi/scsi_message.h> 60 61 #include <machine/autoconf.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <sun3x/dev/dmareg.h> 67 #include <sun3x/dev/dmavar.h> 68 69 #define ESP_REG_SIZE (12*4) 70 #define ESP_DMA_OFF 0x1000 71 72 struct esp_softc { 73 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 74 volatile u_char *sc_reg; /* the registers */ 75 struct dma_softc *sc_dma; /* pointer to my dma */ 76 }; 77 78 static int espmatch __P((struct device *, struct cfdata *, void *)); 79 static void espattach __P((struct device *, struct device *, void *)); 80 81 struct cfattach esp_ca = { 82 sizeof(struct esp_softc), espmatch, espattach 83 }; 84 85 struct cfdriver esp_cd = { 86 NULL, "esp", DV_DULL 87 }; 88 89 struct scsi_adapter esp_switch = { 90 ncr53c9x_scsi_cmd, 91 minphys, /* no max at this level; handled by DMA code */ 92 NULL, 93 NULL, 94 }; 95 96 struct scsi_device esp_dev = { 97 NULL, /* Use default error handler */ 98 NULL, /* have a queue, served by this */ 99 NULL, /* have no async handler */ 100 NULL, /* Use default 'done' routine */ 101 }; 102 103 /* 104 * Functions and the switch for the MI code. 105 */ 106 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 107 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 108 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 109 void esp_dma_reset __P((struct ncr53c9x_softc *)); 110 int esp_dma_intr __P((struct ncr53c9x_softc *)); 111 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 112 size_t *, int, size_t *)); 113 void esp_dma_go __P((struct ncr53c9x_softc *)); 114 void esp_dma_stop __P((struct ncr53c9x_softc *)); 115 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 116 117 static struct ncr53c9x_glue esp_glue = { 118 esp_read_reg, 119 esp_write_reg, 120 esp_dma_isintr, 121 esp_dma_reset, 122 esp_dma_intr, 123 esp_dma_setup, 124 esp_dma_go, 125 esp_dma_stop, 126 esp_dma_isactive, 127 NULL, /* gl_clear_latched_intr */ 128 }; 129 130 static int 131 espmatch(parent, cf, aux) 132 struct device *parent; 133 struct cfdata *cf; 134 void *aux; 135 { 136 struct confargs *ca = aux; 137 138 /* 139 * Check for the DMA registers. 140 */ 141 if (bus_peek(ca->ca_bustype, 142 ca->ca_paddr + ESP_DMA_OFF, 4) == -1) 143 return (0); 144 145 /* 146 * Check for the esp registers. 147 */ 148 if (bus_peek(ca->ca_bustype, 149 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 150 return (0); 151 152 /* If default ipl, fill it in. */ 153 if (ca->ca_intpri == -1) 154 ca->ca_intpri = 2; 155 156 return (1); 157 } 158 159 /* 160 * Attach this instance, and then all the sub-devices 161 * 162 * In the SPARC port, the dma code used by the esp driver looks like 163 * a separate driver, matched and attached by either the esp driver 164 * or the bus attach function. However it's not completely separate 165 * in that the sparc esp driver has to go look in dma_cd.cd_devs to 166 * get the softc for the dma driver, and shares its softc, etc. 167 * 168 * The dma module could exist as a separate autoconfig entity, but 169 * that really does not buy us anything, so why bother with that? 170 * In the current sun3x port, the dma chip is treated as just an 171 * extension of the esp driver because that is easier, and the esp 172 * driver is the only one that uses the dma module. 173 */ 174 static void 175 espattach(parent, self, aux) 176 struct device *parent, *self; 177 void *aux; 178 { 179 register struct confargs *ca = aux; 180 struct esp_softc *esc = (void *)self; 181 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 182 183 /* 184 * Set up glue for MI code early; we use some of it here. 185 */ 186 sc->sc_glue = &esp_glue; 187 188 /* 189 * Map in the ESP registers. 190 */ 191 esc->sc_reg = (volatile u_char *) 192 bus_mapin(ca->ca_bustype, ca->ca_paddr, NBPG); 193 194 /* Other settings */ 195 sc->sc_id = 7; 196 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 197 198 /* 199 * Hook up the DMA driver. 200 * XXX - Would rather do this later, after the common 201 * attach function is done printing its line so the DMA 202 * module can print its revision, but the common attach 203 * code needs this done first... 204 * XXX - Move printf back to MD code? 205 */ 206 esc->sc_dma = malloc(sizeof(struct dma_softc), M_DEVBUF, M_NOWAIT); 207 if (esc->sc_dma == 0) 208 panic("espattach: malloc dma_softc"); 209 bzero(esc->sc_dma, sizeof(struct dma_softc)); 210 esc->sc_dma->sc_esp = sc; /* Point back to us */ 211 esc->sc_dma->sc_regs = (struct dma_regs *) 212 (esc->sc_reg + ESP_DMA_OFF); 213 214 /* 215 * Simulate an attach call here for compatibility with 216 * the sparc dma.c module. It does not print anything. 217 */ 218 dmaattach(self, (struct device *) esc->sc_dma, NULL); 219 220 /* 221 * XXX More of this should be in ncr53c9x_attach(), but 222 * XXX should we really poke around the chip that much in 223 * XXX the MI code? Think about this more... 224 */ 225 226 /* 227 * It is necessary to try to load the 2nd config register here, 228 * to find out what rev the esp chip is, else the ncr53c9x_reset 229 * will not set up the defaults correctly. 230 */ 231 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 232 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 233 sc->sc_cfg3 = NCRCFG3_CDB; 234 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 235 236 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 237 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 238 sc->sc_rev = NCR_VARIANT_ESP100; 239 } else { 240 sc->sc_cfg2 = NCRCFG2_SCSI2; 241 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 242 sc->sc_cfg3 = 0; 243 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 244 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 245 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 246 if (NCR_READ_REG(sc, NCR_CFG3) != 247 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 248 sc->sc_rev = NCR_VARIANT_ESP100A; 249 } else { 250 /* NCRCFG2_FE enables > 64K transfers */ 251 sc->sc_cfg2 |= NCRCFG2_FE; 252 sc->sc_cfg3 = 0; 253 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 254 sc->sc_rev = NCR_VARIANT_ESP200; 255 } 256 } 257 258 /* 259 * XXX minsync and maxxfer _should_ be set up in MI code, 260 * XXX but it appears to have some dependency on what sort 261 * XXX of DMA we're hooked up to, etc. 262 */ 263 264 /* 265 * This is the value used to start sync negotiations 266 * Note that the NCR register "SYNCTP" is programmed 267 * in "clocks per byte", and has a minimum value of 4. 268 * The SCSI period used in negotiation is one-fourth 269 * of the time (in nanoseconds) needed to transfer one byte. 270 * Since the chip's clock is given in MHz, we have the following 271 * formula: 4 * period = (1000 / freq) * 4 272 */ 273 sc->sc_minsync = 1000 / sc->sc_freq; 274 275 /* 276 * Alas, we must now modify the value a bit, because it's 277 * only valid when can switch on FASTCLK and FASTSCSI bits 278 * in config register 3... 279 */ 280 switch (sc->sc_rev) { 281 case NCR_VARIANT_ESP100: 282 sc->sc_maxxfer = 64 * 1024; 283 sc->sc_minsync = 0; /* No synch on old chip? */ 284 break; 285 286 case NCR_VARIANT_ESP100A: 287 sc->sc_maxxfer = 64 * 1024; 288 /* Min clocks/byte is 5 */ 289 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 290 break; 291 292 case NCR_VARIANT_ESP200: 293 sc->sc_maxxfer = 16 * 1024 * 1024; 294 /* XXX - do actually set FAST* bits */ 295 break; 296 } 297 298 /* and the interuppts */ 299 isr_add_autovect((void*)ncr53c9x_intr, sc, ca->ca_intpri); 300 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 301 302 /* Do the common parts of attachment. */ 303 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 304 } 305 306 307 /* 308 * Glue functions. 309 */ 310 311 u_char 312 esp_read_reg(sc, reg) 313 struct ncr53c9x_softc *sc; 314 int reg; 315 { 316 struct esp_softc *esc = (struct esp_softc *)sc; 317 318 return (esc->sc_reg[reg * 4]); 319 } 320 321 void 322 esp_write_reg(sc, reg, val) 323 struct ncr53c9x_softc *sc; 324 int reg; 325 u_char val; 326 { 327 struct esp_softc *esc = (struct esp_softc *)sc; 328 u_char v = val; 329 330 esc->sc_reg[reg * 4] = v; 331 } 332 333 int 334 esp_dma_isintr(sc) 335 struct ncr53c9x_softc *sc; 336 { 337 struct esp_softc *esc = (struct esp_softc *)sc; 338 339 return (dma_isintr(esc->sc_dma)); 340 } 341 342 void 343 esp_dma_reset(sc) 344 struct ncr53c9x_softc *sc; 345 { 346 struct esp_softc *esc = (struct esp_softc *)sc; 347 348 dma_reset(esc->sc_dma); 349 } 350 351 int 352 esp_dma_intr(sc) 353 struct ncr53c9x_softc *sc; 354 { 355 struct esp_softc *esc = (struct esp_softc *)sc; 356 357 return (espdmaintr(esc->sc_dma)); 358 } 359 360 int 361 esp_dma_setup(sc, addr, len, datain, dmasize) 362 struct ncr53c9x_softc *sc; 363 caddr_t *addr; 364 size_t *len; 365 int datain; 366 size_t *dmasize; 367 { 368 struct esp_softc *esc = (struct esp_softc *)sc; 369 370 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 371 } 372 373 void 374 esp_dma_go(sc) 375 struct ncr53c9x_softc *sc; 376 { 377 struct esp_softc *esc = (struct esp_softc *)sc; 378 379 /* Start DMA */ 380 DMACSR(esc->sc_dma) |= D_EN_DMA; 381 esc->sc_dma->sc_active = 1; 382 } 383 384 void 385 esp_dma_stop(sc) 386 struct ncr53c9x_softc *sc; 387 { 388 struct esp_softc *esc = (struct esp_softc *)sc; 389 390 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 391 } 392 393 int 394 esp_dma_isactive(sc) 395 struct ncr53c9x_softc *sc; 396 { 397 struct esp_softc *esc = (struct esp_softc *)sc; 398 399 return (esc->sc_dma->sc_active); 400 } 401
Indexes created Tue Sep 30 11:09:46 GMT 2025