esp.c revision 1.4
1 /* $NetBSD: esp.c,v 1.4 1997/06/27 02:07:32 jeremy Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 #include <sys/malloc.h> 56 57 #include <scsi/scsi_all.h> 58 #include <scsi/scsiconf.h> 59 #include <scsi/scsi_message.h> 60 61 #include <machine/autoconf.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <sun3x/dev/dmareg.h> 67 #include <sun3x/dev/dmavar.h> 68 69 #define ESP_REG_SIZE (12*4) 70 #define ESP_DMA_OFF 0x1000 71 72 struct esp_softc { 73 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 74 volatile u_char *sc_reg; /* the registers */ 75 struct dma_softc *sc_dma; /* pointer to my dma */ 76 }; 77 78 static int espmatch __P((struct device *, struct cfdata *, void *)); 79 static void espattach __P((struct device *, struct device *, void *)); 80 81 struct cfattach esp_ca = { 82 sizeof(struct esp_softc), espmatch, espattach 83 }; 84 85 struct cfdriver esp_cd = { 86 NULL, "esp", DV_DULL 87 }; 88 89 struct scsi_adapter esp_switch = { 90 ncr53c9x_scsi_cmd, 91 minphys, /* no max at this level; handled by DMA code */ 92 NULL, 93 NULL, 94 }; 95 96 struct scsi_device esp_dev = { 97 NULL, /* Use default error handler */ 98 NULL, /* have a queue, served by this */ 99 NULL, /* have no async handler */ 100 NULL, /* Use default 'done' routine */ 101 }; 102 103 /* 104 * Functions and the switch for the MI code. 105 */ 106 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 107 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 108 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 109 void esp_dma_reset __P((struct ncr53c9x_softc *)); 110 int esp_dma_intr __P((struct ncr53c9x_softc *)); 111 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 112 size_t *, int, size_t *)); 113 void esp_dma_go __P((struct ncr53c9x_softc *)); 114 void esp_dma_stop __P((struct ncr53c9x_softc *)); 115 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 116 117 static struct ncr53c9x_glue esp_glue = { 118 esp_read_reg, 119 esp_write_reg, 120 esp_dma_isintr, 121 esp_dma_reset, 122 esp_dma_intr, 123 esp_dma_setup, 124 esp_dma_go, 125 esp_dma_stop, 126 esp_dma_isactive, 127 NULL, /* gl_clear_latched_intr */ 128 }; 129 130 extern int ncr53c9x_dmaselect; /* Used in dev/ic/ncr53c9x.c */ 131 132 static int 133 espmatch(parent, cf, aux) 134 struct device *parent; 135 struct cfdata *cf; 136 void *aux; 137 { 138 struct confargs *ca = aux; 139 140 /* 141 * Check for the DMA registers. 142 */ 143 if (bus_peek(ca->ca_bustype, 144 ca->ca_paddr + ESP_DMA_OFF, 4) == -1) 145 return (0); 146 147 /* 148 * Check for the esp registers. 149 */ 150 if (bus_peek(ca->ca_bustype, 151 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 152 return (0); 153 154 /* If default ipl, fill it in. */ 155 if (ca->ca_intpri == -1) 156 ca->ca_intpri = 2; 157 158 return (1); 159 } 160 161 /* 162 * Attach this instance, and then all the sub-devices 163 * 164 * In the SPARC port, the dma code used by the esp driver looks like 165 * a separate driver, matched and attached by either the esp driver 166 * or the bus attach function. However it's not completely separate 167 * in that the sparc esp driver has to go look in dma_cd.cd_devs to 168 * get the softc for the dma driver, and shares its softc, etc. 169 * 170 * The dma module could exist as a separate autoconfig entity, but 171 * that really does not buy us anything, so why bother with that? 172 * In the current sun3x port, the dma chip is treated as just an 173 * extension of the esp driver because that is easier, and the esp 174 * driver is the only one that uses the dma module. 175 */ 176 static void 177 espattach(parent, self, aux) 178 struct device *parent, *self; 179 void *aux; 180 { 181 register struct confargs *ca = aux; 182 struct esp_softc *esc = (void *)self; 183 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 184 185 /* 186 * Set up glue for MI code early; we use some of it here. 187 */ 188 sc->sc_glue = &esp_glue; 189 190 /* 191 * Map in the ESP registers. 192 */ 193 esc->sc_reg = (volatile u_char *) 194 bus_mapin(ca->ca_bustype, ca->ca_paddr, NBPG); 195 196 /* Other settings */ 197 sc->sc_id = 7; 198 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 199 200 /* 201 * Hook up the DMA driver. 202 * XXX - Would rather do this later, after the common 203 * attach function is done printing its line so the DMA 204 * module can print its revision, but the common attach 205 * code needs this done first... 206 * XXX - Move printf back to MD code? 207 */ 208 esc->sc_dma = malloc(sizeof(struct dma_softc), M_DEVBUF, M_NOWAIT); 209 if (esc->sc_dma == 0) 210 panic("espattach: malloc dma_softc"); 211 bzero(esc->sc_dma, sizeof(struct dma_softc)); 212 esc->sc_dma->sc_esp = sc; /* Point back to us */ 213 esc->sc_dma->sc_regs = (struct dma_regs *) 214 (esc->sc_reg + ESP_DMA_OFF); 215 216 /* 217 * Simulate an attach call here for compatibility with 218 * the sparc dma.c module. It does not print anything. 219 */ 220 dmaattach(self, (struct device *) esc->sc_dma, NULL); 221 222 /* 223 * XXX More of this should be in ncr53c9x_attach(), but 224 * XXX should we really poke around the chip that much in 225 * XXX the MI code? Think about this more... 226 */ 227 228 /* 229 * It is necessary to try to load the 2nd config register here, 230 * to find out what rev the esp chip is, else the ncr53c9x_reset 231 * will not set up the defaults correctly. 232 */ 233 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 234 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 235 sc->sc_cfg3 = NCRCFG3_CDB; 236 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 237 238 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 239 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 240 sc->sc_rev = NCR_VARIANT_ESP100; 241 } else { 242 sc->sc_cfg2 = NCRCFG2_SCSI2; 243 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 244 sc->sc_cfg3 = 0; 245 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 246 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 247 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 248 if (NCR_READ_REG(sc, NCR_CFG3) != 249 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 250 sc->sc_rev = NCR_VARIANT_ESP100A; 251 } else { 252 /* NCRCFG2_FE enables > 64K transfers */ 253 sc->sc_cfg2 |= NCRCFG2_FE; 254 sc->sc_cfg3 = 0; 255 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 256 sc->sc_rev = NCR_VARIANT_ESP200; 257 } 258 } 259 260 /* 261 * XXX minsync and maxxfer _should_ be set up in MI code, 262 * XXX but it appears to have some dependency on what sort 263 * XXX of DMA we're hooked up to, etc. 264 */ 265 266 /* 267 * This is the value used to start sync negotiations 268 * Note that the NCR register "SYNCTP" is programmed 269 * in "clocks per byte", and has a minimum value of 4. 270 * The SCSI period used in negotiation is one-fourth 271 * of the time (in nanoseconds) needed to transfer one byte. 272 * Since the chip's clock is given in MHz, we have the following 273 * formula: 4 * period = (1000 / freq) * 4 274 */ 275 sc->sc_minsync = 1000 / sc->sc_freq; 276 277 /* 278 * Alas, we must now modify the value a bit, because it's 279 * only valid when can switch on FASTCLK and FASTSCSI bits 280 * in config register 3... 281 */ 282 switch (sc->sc_rev) { 283 case NCR_VARIANT_ESP100: 284 sc->sc_maxxfer = 64 * 1024; 285 sc->sc_minsync = 0; /* No synch on old chip? */ 286 /* Avoid hardware bug by using DMA when selecting targets */ 287 /* ncr53c9x_dmaselect = 1; */ 288 break; 289 290 case NCR_VARIANT_ESP100A: 291 sc->sc_maxxfer = 64 * 1024; 292 /* Min clocks/byte is 5 */ 293 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 294 break; 295 296 case NCR_VARIANT_ESP200: 297 sc->sc_maxxfer = 16 * 1024 * 1024; 298 /* XXX - do actually set FAST* bits */ 299 break; 300 } 301 302 /* and the interuppts */ 303 isr_add_autovect((void*)ncr53c9x_intr, sc, ca->ca_intpri); 304 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 305 306 /* Do the common parts of attachment. */ 307 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 308 } 309 310 311 /* 312 * Glue functions. 313 */ 314 315 u_char 316 esp_read_reg(sc, reg) 317 struct ncr53c9x_softc *sc; 318 int reg; 319 { 320 struct esp_softc *esc = (struct esp_softc *)sc; 321 322 return (esc->sc_reg[reg * 4]); 323 } 324 325 void 326 esp_write_reg(sc, reg, val) 327 struct ncr53c9x_softc *sc; 328 int reg; 329 u_char val; 330 { 331 struct esp_softc *esc = (struct esp_softc *)sc; 332 u_char v = val; 333 334 esc->sc_reg[reg * 4] = v; 335 } 336 337 int 338 esp_dma_isintr(sc) 339 struct ncr53c9x_softc *sc; 340 { 341 struct esp_softc *esc = (struct esp_softc *)sc; 342 343 return (dma_isintr(esc->sc_dma)); 344 } 345 346 void 347 esp_dma_reset(sc) 348 struct ncr53c9x_softc *sc; 349 { 350 struct esp_softc *esc = (struct esp_softc *)sc; 351 352 dma_reset(esc->sc_dma); 353 } 354 355 int 356 esp_dma_intr(sc) 357 struct ncr53c9x_softc *sc; 358 { 359 struct esp_softc *esc = (struct esp_softc *)sc; 360 361 return (espdmaintr(esc->sc_dma)); 362 } 363 364 int 365 esp_dma_setup(sc, addr, len, datain, dmasize) 366 struct ncr53c9x_softc *sc; 367 caddr_t *addr; 368 size_t *len; 369 int datain; 370 size_t *dmasize; 371 { 372 struct esp_softc *esc = (struct esp_softc *)sc; 373 374 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 375 } 376 377 void 378 esp_dma_go(sc) 379 struct ncr53c9x_softc *sc; 380 { 381 struct esp_softc *esc = (struct esp_softc *)sc; 382 383 /* Start DMA */ 384 DMACSR(esc->sc_dma) |= D_EN_DMA; 385 esc->sc_dma->sc_active = 1; 386 } 387 388 void 389 esp_dma_stop(sc) 390 struct ncr53c9x_softc *sc; 391 { 392 struct esp_softc *esc = (struct esp_softc *)sc; 393 394 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 395 } 396 397 int 398 esp_dma_isactive(sc) 399 struct ncr53c9x_softc *sc; 400 { 401 struct esp_softc *esc = (struct esp_softc *)sc; 402 403 return (esc->sc_dma->sc_active); 404 } 405
Indexes created Tue Sep 30 11:09:46 GMT 2025