esp.c revision 1.7
1 /* $NetBSD: esp.c,v 1.7 1998/02/05 04:56:37 gwr Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 #include <sys/malloc.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <dev/scsipi/scsi_message.h> 61 62 #include <machine/autoconf.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <sun3/dev/dmareg.h> 68 #include <sun3/dev/dmavar.h> 69 70 #define ESP_REG_SIZE (12*4) 71 #define ESP_DMA_OFF 0x1000 72 73 struct esp_softc { 74 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 75 volatile u_char *sc_reg; /* the registers */ 76 struct dma_softc *sc_dma; /* pointer to my dma */ 77 }; 78 79 static int espmatch __P((struct device *, struct cfdata *, void *)); 80 static void espattach __P((struct device *, struct device *, void *)); 81 82 struct cfattach esp_ca = { 83 sizeof(struct esp_softc), espmatch, espattach 84 }; 85 86 struct scsipi_adapter esp_switch = { 87 ncr53c9x_scsi_cmd, 88 minphys, /* no max at this level; handled by DMA code */ 89 NULL, 90 NULL, 91 }; 92 93 struct scsipi_device esp_dev = { 94 NULL, /* Use default error handler */ 95 NULL, /* have a queue, served by this */ 96 NULL, /* have no async handler */ 97 NULL, /* Use default 'done' routine */ 98 }; 99 100 /* 101 * Functions and the switch for the MI code. 102 */ 103 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 104 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 105 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 106 void esp_dma_reset __P((struct ncr53c9x_softc *)); 107 int esp_dma_intr __P((struct ncr53c9x_softc *)); 108 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 109 size_t *, int, size_t *)); 110 void esp_dma_go __P((struct ncr53c9x_softc *)); 111 void esp_dma_stop __P((struct ncr53c9x_softc *)); 112 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 113 114 static struct ncr53c9x_glue esp_glue = { 115 esp_read_reg, 116 esp_write_reg, 117 esp_dma_isintr, 118 esp_dma_reset, 119 esp_dma_intr, 120 esp_dma_setup, 121 esp_dma_go, 122 esp_dma_stop, 123 esp_dma_isactive, 124 NULL, /* gl_clear_latched_intr */ 125 }; 126 127 extern int ncr53c9x_dmaselect; /* Used in dev/ic/ncr53c9x.c */ 128 129 static int 130 espmatch(parent, cf, aux) 131 struct device *parent; 132 struct cfdata *cf; 133 void *aux; 134 { 135 struct confargs *ca = aux; 136 137 /* 138 * Check for the DMA registers. 139 */ 140 if (bus_peek(ca->ca_bustype, 141 ca->ca_paddr + ESP_DMA_OFF, 4) == -1) 142 return (0); 143 144 /* 145 * Check for the esp registers. 146 */ 147 if (bus_peek(ca->ca_bustype, 148 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 149 return (0); 150 151 /* If default ipl, fill it in. */ 152 if (ca->ca_intpri == -1) 153 ca->ca_intpri = 2; 154 155 return (1); 156 } 157 158 /* 159 * Attach this instance, and then all the sub-devices 160 * 161 * In the SPARC port, the dma code used by the esp driver looks like 162 * a separate driver, matched and attached by either the esp driver 163 * or the bus attach function. However it's not completely separate 164 * in that the sparc esp driver has to go look in dma_cd.cd_devs to 165 * get the softc for the dma driver, and shares its softc, etc. 166 * 167 * The dma module could exist as a separate autoconfig entity, but 168 * that really does not buy us anything, so why bother with that? 169 * In the current sun3x port, the dma chip is treated as just an 170 * extension of the esp driver because that is easier, and the esp 171 * driver is the only one that uses the dma module. 172 */ 173 static void 174 espattach(parent, self, aux) 175 struct device *parent, *self; 176 void *aux; 177 { 178 register struct confargs *ca = aux; 179 struct esp_softc *esc = (void *)self; 180 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 181 182 /* 183 * Set up glue for MI code early; we use some of it here. 184 */ 185 sc->sc_glue = &esp_glue; 186 187 /* 188 * Map in the ESP registers. 189 */ 190 esc->sc_reg = (volatile u_char *) 191 bus_mapin(ca->ca_bustype, ca->ca_paddr, NBPG); 192 193 /* Other settings */ 194 sc->sc_id = 7; 195 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 196 197 /* 198 * Hook up the DMA driver. 199 * XXX - Would rather do this later, after the common 200 * attach function is done printing its line so the DMA 201 * module can print its revision, but the common attach 202 * code needs this done first... 203 * XXX - Move printf back to MD code? 204 */ 205 esc->sc_dma = malloc(sizeof(struct dma_softc), M_DEVBUF, M_NOWAIT); 206 if (esc->sc_dma == 0) 207 panic("espattach: malloc dma_softc"); 208 bzero(esc->sc_dma, sizeof(struct dma_softc)); 209 esc->sc_dma->sc_esp = sc; /* Point back to us */ 210 esc->sc_dma->sc_regs = (struct dma_regs *) 211 (esc->sc_reg + ESP_DMA_OFF); 212 213 /* 214 * Simulate an attach call here for compatibility with 215 * the sparc dma.c module. It does not print anything. 216 */ 217 dmaattach(self, (struct device *) esc->sc_dma, NULL); 218 219 /* 220 * XXX More of this should be in ncr53c9x_attach(), but 221 * XXX should we really poke around the chip that much in 222 * XXX the MI code? Think about this more... 223 */ 224 225 /* 226 * It is necessary to try to load the 2nd config register here, 227 * to find out what rev the esp chip is, else the ncr53c9x_reset 228 * will not set up the defaults correctly. 229 */ 230 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 231 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 232 sc->sc_cfg3 = NCRCFG3_CDB; 233 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 234 235 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 236 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 237 sc->sc_rev = NCR_VARIANT_ESP100; 238 } else { 239 sc->sc_cfg2 = NCRCFG2_SCSI2; 240 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 241 sc->sc_cfg3 = 0; 242 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 243 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 244 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 245 if (NCR_READ_REG(sc, NCR_CFG3) != 246 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 247 sc->sc_rev = NCR_VARIANT_ESP100A; 248 } else { 249 /* NCRCFG2_FE enables > 64K transfers */ 250 sc->sc_cfg2 |= NCRCFG2_FE; 251 sc->sc_cfg3 = 0; 252 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 253 sc->sc_rev = NCR_VARIANT_ESP200; 254 } 255 } 256 257 /* 258 * XXX minsync and maxxfer _should_ be set up in MI code, 259 * XXX but it appears to have some dependency on what sort 260 * XXX of DMA we're hooked up to, etc. 261 */ 262 263 /* 264 * This is the value used to start sync negotiations 265 * Note that the NCR register "SYNCTP" is programmed 266 * in "clocks per byte", and has a minimum value of 4. 267 * The SCSI period used in negotiation is one-fourth 268 * of the time (in nanoseconds) needed to transfer one byte. 269 * Since the chip's clock is given in MHz, we have the following 270 * formula: 4 * period = (1000 / freq) * 4 271 */ 272 sc->sc_minsync = 1000 / sc->sc_freq; 273 274 /* 275 * Alas, we must now modify the value a bit, because it's 276 * only valid when can switch on FASTCLK and FASTSCSI bits 277 * in config register 3... 278 */ 279 switch (sc->sc_rev) { 280 case NCR_VARIANT_ESP100: 281 sc->sc_maxxfer = 64 * 1024; 282 sc->sc_minsync = 0; /* No synch on old chip? */ 283 /* Avoid hardware bug by using DMA when selecting targets */ 284 /* ncr53c9x_dmaselect = 1; */ 285 break; 286 287 case NCR_VARIANT_ESP100A: 288 sc->sc_maxxfer = 64 * 1024; 289 /* Min clocks/byte is 5 */ 290 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 291 break; 292 293 case NCR_VARIANT_ESP200: 294 sc->sc_maxxfer = 16 * 1024 * 1024; 295 /* XXX - do actually set FAST* bits */ 296 break; 297 } 298 299 /* and the interuppts */ 300 isr_add_autovect((void*)ncr53c9x_intr, sc, ca->ca_intpri); 301 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 302 303 /* Do the common parts of attachment. */ 304 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 305 } 306 307 308 /* 309 * Glue functions. 310 */ 311 312 u_char 313 esp_read_reg(sc, reg) 314 struct ncr53c9x_softc *sc; 315 int reg; 316 { 317 struct esp_softc *esc = (struct esp_softc *)sc; 318 319 return (esc->sc_reg[reg * 4]); 320 } 321 322 void 323 esp_write_reg(sc, reg, val) 324 struct ncr53c9x_softc *sc; 325 int reg; 326 u_char val; 327 { 328 struct esp_softc *esc = (struct esp_softc *)sc; 329 u_char v = val; 330 331 esc->sc_reg[reg * 4] = v; 332 } 333 334 int 335 esp_dma_isintr(sc) 336 struct ncr53c9x_softc *sc; 337 { 338 struct esp_softc *esc = (struct esp_softc *)sc; 339 340 return (dma_isintr(esc->sc_dma)); 341 } 342 343 void 344 esp_dma_reset(sc) 345 struct ncr53c9x_softc *sc; 346 { 347 struct esp_softc *esc = (struct esp_softc *)sc; 348 349 dma_reset(esc->sc_dma); 350 } 351 352 int 353 esp_dma_intr(sc) 354 struct ncr53c9x_softc *sc; 355 { 356 struct esp_softc *esc = (struct esp_softc *)sc; 357 358 return (espdmaintr(esc->sc_dma)); 359 } 360 361 int 362 esp_dma_setup(sc, addr, len, datain, dmasize) 363 struct ncr53c9x_softc *sc; 364 caddr_t *addr; 365 size_t *len; 366 int datain; 367 size_t *dmasize; 368 { 369 struct esp_softc *esc = (struct esp_softc *)sc; 370 371 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 372 } 373 374 void 375 esp_dma_go(sc) 376 struct ncr53c9x_softc *sc; 377 { 378 struct esp_softc *esc = (struct esp_softc *)sc; 379 380 /* Start DMA */ 381 DMACSR(esc->sc_dma) |= D_EN_DMA; 382 esc->sc_dma->sc_active = 1; 383 } 384 385 void 386 esp_dma_stop(sc) 387 struct ncr53c9x_softc *sc; 388 { 389 struct esp_softc *esc = (struct esp_softc *)sc; 390 391 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 392 } 393 394 int 395 esp_dma_isactive(sc) 396 struct ncr53c9x_softc *sc; 397 { 398 struct esp_softc *esc = (struct esp_softc *)sc; 399 400 return (esc->sc_dma->sc_active); 401 } 402
Indexes created Tue Sep 30 11:09:46 GMT 2025