esp.c revision 1.9
1 /* $NetBSD: esp.c,v 1.9 1998/11/19 21:49:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and Gordon W. Ross 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * "Front end" glue for the ncr53c9x chip, formerly known as the 41 * Emulex SCSI Processor (ESP) which is what we actually have. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 #include <sys/malloc.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsiconf.h> 60 #include <dev/scsipi/scsi_message.h> 61 62 #include <machine/autoconf.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <sun3/dev/dmareg.h> 68 #include <sun3/dev/dmavar.h> 69 70 #define ESP_REG_SIZE (12*4) 71 #define ESP_DMA_OFF 0x1000 72 73 struct esp_softc { 74 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 75 volatile u_char *sc_reg; /* the registers */ 76 struct dma_softc *sc_dma; /* pointer to my dma */ 77 }; 78 79 static int espmatch __P((struct device *, struct cfdata *, void *)); 80 static void espattach __P((struct device *, struct device *, void *)); 81 82 struct cfattach esp_ca = { 83 sizeof(struct esp_softc), espmatch, espattach 84 }; 85 86 struct scsipi_device esp_dev = { 87 NULL, /* Use default error handler */ 88 NULL, /* have a queue, served by this */ 89 NULL, /* have no async handler */ 90 NULL, /* Use default 'done' routine */ 91 }; 92 93 /* 94 * Functions and the switch for the MI code. 95 */ 96 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 97 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 98 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 99 void esp_dma_reset __P((struct ncr53c9x_softc *)); 100 int esp_dma_intr __P((struct ncr53c9x_softc *)); 101 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 102 size_t *, int, size_t *)); 103 void esp_dma_go __P((struct ncr53c9x_softc *)); 104 void esp_dma_stop __P((struct ncr53c9x_softc *)); 105 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 106 107 static struct ncr53c9x_glue esp_glue = { 108 esp_read_reg, 109 esp_write_reg, 110 esp_dma_isintr, 111 esp_dma_reset, 112 esp_dma_intr, 113 esp_dma_setup, 114 esp_dma_go, 115 esp_dma_stop, 116 esp_dma_isactive, 117 NULL, /* gl_clear_latched_intr */ 118 }; 119 120 extern int ncr53c9x_dmaselect; /* Used in dev/ic/ncr53c9x.c */ 121 122 static int 123 espmatch(parent, cf, aux) 124 struct device *parent; 125 struct cfdata *cf; 126 void *aux; 127 { 128 struct confargs *ca = aux; 129 130 /* 131 * Check for the DMA registers. 132 */ 133 if (bus_peek(ca->ca_bustype, 134 ca->ca_paddr + ESP_DMA_OFF, 4) == -1) 135 return (0); 136 137 /* 138 * Check for the esp registers. 139 */ 140 if (bus_peek(ca->ca_bustype, 141 ca->ca_paddr + (NCR_STAT * 4), 1) == -1) 142 return (0); 143 144 /* If default ipl, fill it in. */ 145 if (ca->ca_intpri == -1) 146 ca->ca_intpri = 2; 147 148 return (1); 149 } 150 151 /* 152 * Attach this instance, and then all the sub-devices 153 * 154 * In the SPARC port, the dma code used by the esp driver looks like 155 * a separate driver, matched and attached by either the esp driver 156 * or the bus attach function. However it's not completely separate 157 * in that the sparc esp driver has to go look in dma_cd.cd_devs to 158 * get the softc for the dma driver, and shares its softc, etc. 159 * 160 * The dma module could exist as a separate autoconfig entity, but 161 * that really does not buy us anything, so why bother with that? 162 * In the current sun3x port, the dma chip is treated as just an 163 * extension of the esp driver because that is easier, and the esp 164 * driver is the only one that uses the dma module. 165 */ 166 static void 167 espattach(parent, self, aux) 168 struct device *parent, *self; 169 void *aux; 170 { 171 register struct confargs *ca = aux; 172 struct esp_softc *esc = (void *)self; 173 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 174 175 /* 176 * Set up glue for MI code early; we use some of it here. 177 */ 178 sc->sc_glue = &esp_glue; 179 180 /* 181 * Map in the ESP registers. 182 */ 183 esc->sc_reg = (volatile u_char *) 184 bus_mapin(ca->ca_bustype, ca->ca_paddr, NBPG); 185 186 /* Other settings */ 187 sc->sc_id = 7; 188 sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */ 189 190 /* 191 * Hook up the DMA driver. 192 * XXX - Would rather do this later, after the common 193 * attach function is done printing its line so the DMA 194 * module can print its revision, but the common attach 195 * code needs this done first... 196 * XXX - Move printf back to MD code? 197 */ 198 esc->sc_dma = malloc(sizeof(struct dma_softc), M_DEVBUF, M_NOWAIT); 199 if (esc->sc_dma == 0) 200 panic("espattach: malloc dma_softc"); 201 bzero(esc->sc_dma, sizeof(struct dma_softc)); 202 esc->sc_dma->sc_esp = sc; /* Point back to us */ 203 esc->sc_dma->sc_regs = (struct dma_regs *) 204 (esc->sc_reg + ESP_DMA_OFF); 205 206 /* 207 * Simulate an attach call here for compatibility with 208 * the sparc dma.c module. It does not print anything. 209 */ 210 dmaattach(self, (struct device *) esc->sc_dma, NULL); 211 212 /* 213 * XXX More of this should be in ncr53c9x_attach(), but 214 * XXX should we really poke around the chip that much in 215 * XXX the MI code? Think about this more... 216 */ 217 218 /* 219 * It is necessary to try to load the 2nd config register here, 220 * to find out what rev the esp chip is, else the ncr53c9x_reset 221 * will not set up the defaults correctly. 222 */ 223 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 224 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 225 sc->sc_cfg3 = NCRCFG3_CDB; 226 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 227 228 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 229 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 230 sc->sc_rev = NCR_VARIANT_ESP100; 231 } else { 232 sc->sc_cfg2 = NCRCFG2_SCSI2; 233 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 234 sc->sc_cfg3 = 0; 235 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 236 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 237 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 238 if (NCR_READ_REG(sc, NCR_CFG3) != 239 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 240 sc->sc_rev = NCR_VARIANT_ESP100A; 241 } else { 242 /* NCRCFG2_FE enables > 64K transfers */ 243 sc->sc_cfg2 |= NCRCFG2_FE; 244 sc->sc_cfg3 = 0; 245 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 246 sc->sc_rev = NCR_VARIANT_ESP200; 247 } 248 } 249 250 /* 251 * XXX minsync and maxxfer _should_ be set up in MI code, 252 * XXX but it appears to have some dependency on what sort 253 * XXX of DMA we're hooked up to, etc. 254 */ 255 256 /* 257 * This is the value used to start sync negotiations 258 * Note that the NCR register "SYNCTP" is programmed 259 * in "clocks per byte", and has a minimum value of 4. 260 * The SCSI period used in negotiation is one-fourth 261 * of the time (in nanoseconds) needed to transfer one byte. 262 * Since the chip's clock is given in MHz, we have the following 263 * formula: 4 * period = (1000 / freq) * 4 264 */ 265 sc->sc_minsync = 1000 / sc->sc_freq; 266 267 /* 268 * Alas, we must now modify the value a bit, because it's 269 * only valid when can switch on FASTCLK and FASTSCSI bits 270 * in config register 3... 271 */ 272 switch (sc->sc_rev) { 273 case NCR_VARIANT_ESP100: 274 sc->sc_maxxfer = 64 * 1024; 275 sc->sc_minsync = 0; /* No synch on old chip? */ 276 /* Avoid hardware bug by using DMA when selecting targets */ 277 /* ncr53c9x_dmaselect = 1; */ 278 break; 279 280 case NCR_VARIANT_ESP100A: 281 sc->sc_maxxfer = 64 * 1024; 282 /* Min clocks/byte is 5 */ 283 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 284 break; 285 286 case NCR_VARIANT_ESP200: 287 sc->sc_maxxfer = 16 * 1024 * 1024; 288 /* XXX - do actually set FAST* bits */ 289 break; 290 } 291 292 /* and the interuppts */ 293 isr_add_autovect((void*)ncr53c9x_intr, sc, ca->ca_intpri); 294 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 295 296 /* Do the common parts of attachment. */ 297 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 298 sc->sc_adapter.scsipi_minphys = minphys; 299 ncr53c9x_attach(sc, &esp_dev); 300 } 301 302 303 /* 304 * Glue functions. 305 */ 306 307 u_char 308 esp_read_reg(sc, reg) 309 struct ncr53c9x_softc *sc; 310 int reg; 311 { 312 struct esp_softc *esc = (struct esp_softc *)sc; 313 314 return (esc->sc_reg[reg * 4]); 315 } 316 317 void 318 esp_write_reg(sc, reg, val) 319 struct ncr53c9x_softc *sc; 320 int reg; 321 u_char val; 322 { 323 struct esp_softc *esc = (struct esp_softc *)sc; 324 u_char v = val; 325 326 esc->sc_reg[reg * 4] = v; 327 } 328 329 int 330 esp_dma_isintr(sc) 331 struct ncr53c9x_softc *sc; 332 { 333 struct esp_softc *esc = (struct esp_softc *)sc; 334 335 return (dma_isintr(esc->sc_dma)); 336 } 337 338 void 339 esp_dma_reset(sc) 340 struct ncr53c9x_softc *sc; 341 { 342 struct esp_softc *esc = (struct esp_softc *)sc; 343 344 dma_reset(esc->sc_dma); 345 } 346 347 int 348 esp_dma_intr(sc) 349 struct ncr53c9x_softc *sc; 350 { 351 struct esp_softc *esc = (struct esp_softc *)sc; 352 353 return (espdmaintr(esc->sc_dma)); 354 } 355 356 int 357 esp_dma_setup(sc, addr, len, datain, dmasize) 358 struct ncr53c9x_softc *sc; 359 caddr_t *addr; 360 size_t *len; 361 int datain; 362 size_t *dmasize; 363 { 364 struct esp_softc *esc = (struct esp_softc *)sc; 365 366 return (dma_setup(esc->sc_dma, addr, len, datain, dmasize)); 367 } 368 369 void 370 esp_dma_go(sc) 371 struct ncr53c9x_softc *sc; 372 { 373 struct esp_softc *esc = (struct esp_softc *)sc; 374 375 /* Start DMA */ 376 DMACSR(esc->sc_dma) |= D_EN_DMA; 377 esc->sc_dma->sc_active = 1; 378 } 379 380 void 381 esp_dma_stop(sc) 382 struct ncr53c9x_softc *sc; 383 { 384 struct esp_softc *esc = (struct esp_softc *)sc; 385 386 DMACSR(esc->sc_dma) &= ~D_EN_DMA; 387 } 388 389 int 390 esp_dma_isactive(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 struct esp_softc *esc = (struct esp_softc *)sc; 394 395 return (esc->sc_dma->sc_active); 396 } 397
Indexes created Tue Sep 30 11:09:46 GMT 2025