if_iereg.h revision 1.1
11.1Sgwr/*	$NetBSD: if_iereg.h,v 1.1 1994/12/12 18:59:09 gwr Exp $ */
21.1Sgwr
31.1Sgwr/*
41.1Sgwr * if_sunie.h
51.1Sgwr *
61.1Sgwr * sun's ie interface
71.1Sgwr */
81.1Sgwr
91.1Sgwr/*
101.1Sgwr * programming notes:
111.1Sgwr *
121.1Sgwr * the ie chip operates in a 24 bit address space.
131.1Sgwr *
141.1Sgwr * most ie interfaces appear to be divided into two parts:
151.1Sgwr *	 - generic 586 stuff
161.1Sgwr *	 - board specific
171.1Sgwr *
181.1Sgwr * generic:
191.1Sgwr *	the generic stuff of the ie chip is all done with data structures
201.1Sgwr * 	that live in the chip's memory address space.   the chip expects
211.1Sgwr * 	its main data structure (the sys conf ptr -- SCP) to be at a fixed
221.1Sgwr * 	address in its 24 bit space: 0xfffff4
231.1Sgwr *
241.1Sgwr *      the SCP points to another structure called the ISCP.
251.1Sgwr *      the ISCP points to another structure called the SCB.
261.1Sgwr * 	the SCB has a status field, a linked list of "commands", and
271.1Sgwr * 	a linked list of "receive buffers".   these are data structures that
281.1Sgwr * 	live in memory, not registers.
291.1Sgwr *
301.1Sgwr * board:
311.1Sgwr * 	to get the chip to do anything, you first put a command in the
321.1Sgwr * 	command data structure list.   then you have to signal "attention"
331.1Sgwr * 	to the chip to get it to look at the command.   how you
341.1Sgwr * 	signal attention depends on what board you have... on PC's
351.1Sgwr * 	there is an i/o port number to do this, on sun's there is a
361.1Sgwr * 	register bit you toggle.
371.1Sgwr *
381.1Sgwr * 	to get data from the chip you program it to interrupt...
391.1Sgwr *
401.1Sgwr *
411.1Sgwr * sun issues:
421.1Sgwr *
431.1Sgwr *      there are 3 kinds of sun "ie" interfaces:
441.1Sgwr *        1 - a VME/multibus card
451.1Sgwr *        2 - an on-board interface (sun3's, sun-4/100's, and sun-4/200's)
461.1Sgwr *        3 - another VME board called the 3E
471.1Sgwr *
481.1Sgwr * 	the VME boards lives in vme16 space.   only 16 and 8 bit accesses
491.1Sgwr * 	are allowed, so functions that copy data must be aware of this.
501.1Sgwr *
511.1Sgwr * 	the chip is an intel chip.  this means that the byte order
521.1Sgwr * 	on all the "short"s in the chip's data structures is wrong.
531.1Sgwr * 	so, constants described in the intel docs are swapped for the sun.
541.1Sgwr * 	that means that any buffer pointers you give the chip must be
551.1Sgwr * 	swapped to intel format.   yuck.
561.1Sgwr *
571.1Sgwr *   VME/multibus interface:
581.1Sgwr * 	for the multibus interface the board ignores the top 4 bits
591.1Sgwr * 	of the chip address.   the multibus interface seems to have its
601.1Sgwr * 	own MMU like page map (without protections or valid bits, etc).
611.1Sgwr * 	there are 256 pages of physical memory on the board (each page
621.1Sgwr * 	is 1024 bytes).   there are 1024 slots in the page map.  so,
631.1Sgwr * 	a 1024 byte page takes up 10 bits of address for the offset,
641.1Sgwr * 	and if there are 1024 slots in the page that is another 10 bits
651.1Sgwr * 	of the address.   that makes a 20 bit address, and as stated
661.1Sgwr * 	earlier the board ignores the top 4 bits, so that accounts
671.1Sgwr * 	for all 24 bits of address.
681.1Sgwr *
691.1Sgwr * 	note that the last entry of the page map maps the top of the
701.1Sgwr * 	24 bit address space and that the SCP is supposed to be at
711.1Sgwr * 	0xfffff4 (taking into account allignment).   so,
721.1Sgwr *	for multibus, that entry in the page map has to be used for the SCP.
731.1Sgwr *
741.1Sgwr * 	the page map effects BOTH how the ie chip sees the
751.1Sgwr * 	memory, and how the host sees it.
761.1Sgwr *
771.1Sgwr * 	the page map is part of the "register" area of the board
781.1Sgwr *
791.1Sgwr *   on-board interface:
801.1Sgwr *
811.1Sgwr *	<fill in useful info later>
821.1Sgwr *
831.1Sgwr *
841.1Sgwr *   VME3E interface:
851.1Sgwr *
861.1Sgwr *	<fill in useful info later>
871.1Sgwr *
881.1Sgwr */
891.1Sgwr
901.1Sgwr/*
911.1Sgwr * PART 1: VME/multibus defs
921.1Sgwr */
931.1Sgwr#define IEVME_PAGESIZE 1024	/* bytes */
941.1Sgwr#define IEVME_PAGSHIFT 10	/* bits */
951.1Sgwr#define IEVME_NPAGES   256	/* number of pages on chip */
961.1Sgwr#define IEVME_MAPSZ    1024	/* number of entries in the map */
971.1Sgwr
981.1Sgwr/*
991.1Sgwr * PTE for the page map
1001.1Sgwr */
1011.1Sgwr#define IEVME_SBORDR 0x8000	/* sun byte order */
1021.1Sgwr#define IEVME_IBORDR 0x0000	/* intel byte ordr */
1031.1Sgwr
1041.1Sgwr#define IEVME_P2MEM  0x2000	/* memory is on P2 */
1051.1Sgwr#define IEVME_OBMEM  0x0000	/* memory is on board */
1061.1Sgwr
1071.1Sgwr#define IEVME_PGMASK 0x0fff	/* gives the physical page frame number */
1081.1Sgwr
1091.1Sgwrstruct ievme {
1101.1Sgwr	u_short pgmap[IEVME_MAPSZ];
1111.1Sgwr	u_short xxx[32];	/* prom */
1121.1Sgwr	u_short status;		/* see below for bits */
1131.1Sgwr	u_short xxx2;		/* filler */
1141.1Sgwr	u_short pectrl;		/* parity control (see below) */
1151.1Sgwr	u_short peaddr;		/* low 16 bits of address */
1161.1Sgwr};
1171.1Sgwr
1181.1Sgwr/*
1191.1Sgwr * status bits
1201.1Sgwr */
1211.1Sgwr#define IEVME_RESET 0x8000	/* reset board */
1221.1Sgwr#define IEVME_ONAIR 0x4000	/* go out of loopback 'on-air' */
1231.1Sgwr#define IEVME_ATTEN 0x2000	/* attention */
1241.1Sgwr#define IEVME_IENAB 0x1000	/* interrupt enable */
1251.1Sgwr#define IEVME_PEINT 0x0800	/* parity error interrupt enable */
1261.1Sgwr#define IEVME_PERR  0x0200	/* parity error flag */
1271.1Sgwr#define IEVME_INT   0x0100	/* interrupt flag */
1281.1Sgwr#define IEVME_P2EN  0x0020	/* enable p2 bus */
1291.1Sgwr#define IEVME_256K  0x0010	/* 256kb rams */
1301.1Sgwr#define IEVME_HADDR 0x000f	/* mask for bits 17-20 of address */
1311.1Sgwr
1321.1Sgwr/*
1331.1Sgwr * parity control
1341.1Sgwr */
1351.1Sgwr#define IEVME_PARACK 0x0100	/* parity error ack */
1361.1Sgwr#define IEVME_PARSRC 0x0080	/* parity error source */
1371.1Sgwr#define IEVME_PAREND 0x0040	/* which end of the data got the error */
1381.1Sgwr#define IEVME_PARADR 0x000f	/* mask to get bits 17-20 of parity address */
1391.1Sgwr
1401.1Sgwr
1411.1Sgwr/*
1421.1Sgwr * PART 2: the on-board interface
1431.1Sgwr */
1441.1Sgwrstruct ieob {
1451.1Sgwr	u_char  obctrl;
1461.1Sgwr};
1471.1Sgwr#define IEOB_NORSET 0x80	/* don't reset the board */
1481.1Sgwr#define IEOB_ONAIR  0x40	/* put us on the air */
1491.1Sgwr#define IEOB_ATTEN  0x20	/* attention! */
1501.1Sgwr#define IEOB_IENAB  0x10	/* interrupt enable */
1511.1Sgwr#define IEOB_XXXXX  0x08	/* free bit */
1521.1Sgwr#define IEOB_XCVRL2 0x04	/* level 2 transceiver? */
1531.1Sgwr#define IEOB_BUSERR 0x02	/* bus error */
1541.1Sgwr#define IEOB_INT    0x01	/* interrupt */
1551.1Sgwr
1561.1Sgwr/*
1571.1Sgwr * PART 3: the 3E board
1581.1Sgwr */
1591.1Sgwr
1601.1Sgwr/*
1611.1Sgwr * not supported (yet?)
1621.1Sgwr */
1631.1Sgwr
164