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      1  1.17    andvar /*	$NetBSD: if_ievar.h,v 1.17 2021/10/24 20:00:11 andvar Exp $	*/
      2   1.1       gwr 
      3   1.1       gwr /*
      4   1.1       gwr  * Machine-dependent glue for the Intel Ethernet (ie) driver.
      5   1.1       gwr  */
      6   1.1       gwr 
      7   1.8       gwr #define	MXFRAMES	128	/* max number of frames to allow for receive */
      8   1.8       gwr #define	MXRXBUF 	192	/* max number of buffers to allocate */
      9   1.1       gwr #define	IE_RBUF_SIZE	256	/* size of each buffer, MUST BE POWER OF TWO */
     10   1.1       gwr #define	NTXBUF		2	/* number of transmit buffer/command pairs */
     11   1.6       gwr #define	IE_TBUF_SIZE	(3*512)	/* length of transmit buffer */
     12   1.1       gwr 
     13   1.1       gwr enum ie_hardware {
     14   1.1       gwr 	IE_VME,			/* multibus to VME ie card */
     15   1.1       gwr 	IE_OBIO,		/* on board */
     16   1.1       gwr 	IE_VME3E,		/* sun 3e VME card */
     17   1.1       gwr 	IE_UNKNOWN
     18   1.1       gwr };
     19   1.1       gwr 
     20   1.1       gwr /*
     21   1.1       gwr  * Ethernet status, per interface.
     22   1.1       gwr  *
     23   1.1       gwr  * hardware addresses/sizes to know (all KVA):
     24   1.1       gwr  *   sc_iobase = base of chip's 24 bit address space
     25   1.1       gwr  *   sc_maddr  = base address of chip RAM as stored in ie_base of iscp
     26   1.1       gwr  *   sc_msize  = size of chip's RAM
     27   1.1       gwr  *   sc_reg    = address of card dependent registers
     28   1.1       gwr  *
     29   1.1       gwr  * the chip uses two types of pointers: 16 bit and 24 bit
     30   1.1       gwr  *   16 bit pointers are offsets from sc_maddr/ie_base
     31   1.1       gwr  *      KVA(16 bit offset) = offset + sc_maddr
     32   1.1       gwr  *   24 bit pointers are offset from sc_iobase in KVA
     33   1.1       gwr  *      KVA(24 bit address) = address + sc_iobase
     34   1.1       gwr  *
     35   1.1       gwr  * on the vme/multibus we have the page map to control where ram appears
     36   1.1       gwr  * in the address space.   we choose to have RAM start at 0 in the
     37   1.1       gwr  * 24 bit address space.   this means that sc_iobase == sc_maddr!
     38  1.17    andvar  * to get the physical address of the board's RAM you must take the
     39   1.1       gwr  * top 12 bits of the physical address of the register address
     40   1.1       gwr  * and or in the 4 bits from the status word as bits 17-20 (remember that
     41   1.1       gwr  * the board ignores the chip's top 4 address lines).
     42   1.1       gwr  * For example:
     43   1.1       gwr  *   if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000.
     44  1.11     soren  *   to get the 4 bits from the status word just do status & IEVME_HADDR.
     45   1.1       gwr  *   suppose the value is "4".   Then just shift it left 16 bits to get
     46   1.1       gwr  *   it into bits 17-20 (e.g. 0x40000).    Then or it to get the
     47   1.1       gwr  *   address of RAM (in our example: 0xffe40000).   see the attach routine!
     48   1.1       gwr  *
     49   1.4       gwr  * In the onboard ie interface, the 24 bit address space is hardwired
     50   1.1       gwr  * to be 0xff000000 -> 0xffffffff of KVA.   this means that sc_iobase
     51   1.1       gwr  * will be 0xff000000.   sc_maddr will be where ever we allocate RAM
     52   1.1       gwr  * in KVA.    note that since the SCP is at a fixed address it means
     53   1.4       gwr  * that we have to use some memory at a fixed KVA for the SCP.
     54   1.4       gwr  * The Sun PROM leaves a page for us at the end of KVA space.
     55   1.1       gwr  */
     56   1.1       gwr struct ie_softc {
     57  1.15   tsutsui 	device_t sc_dev;	/* device structure */
     58   1.1       gwr 
     59   1.9        is 	struct ethercom sc_ethercom;/* system ethercom structure */
     60   1.9        is #define	sc_if	sc_ethercom.ec_if 		/* network-visible interface */
     61   1.9        is 
     62   1.9        is 	/* XXX: This is used only during attach. */
     63  1.12       chs 	uint8_t sc_addr[ETHER_ADDR_LEN];
     64  1.12       chs 	uint8_t sc_pad1[2];
     65   1.1       gwr 
     66   1.8       gwr 	int     sc_debug;	/* See IEDEBUG */
     67   1.7       gwr 
     68   1.7       gwr 	/* card dependent functions: */
     69  1.12       chs 	void    (*reset_586)(struct ie_softc *);
     70  1.12       chs 	void    (*chan_attn)(struct ie_softc *);
     71  1.12       chs 	void    (*run_586)  (struct ie_softc *);
     72  1.12       chs 	void	*(*sc_memcpy)(void *, const void *, size_t);
     73  1.12       chs 	void	*(*sc_memset)(void *, int, size_t);
     74   1.1       gwr 
     75  1.14  christos 	void *sc_iobase;	/* KVA of base of 24bit addr space */
     76  1.14  christos 	void *sc_maddr;	/* KVA of base of chip's RAM */
     77   1.8       gwr 	u_int   sc_msize;	/* how much RAM we have/use */
     78  1.14  christos 	void *sc_reg;		/* KVA of card's register */
     79   1.8       gwr 
     80   1.8       gwr 	enum ie_hardware hard_type;	/* card type */
     81   1.8       gwr 
     82   1.1       gwr 	int     want_mcsetup;	/* flag for multicast setup */
     83  1.16   msaitoh 	u_short     promisc;	/* are we in promisc mode? */
     84   1.1       gwr 
     85   1.8       gwr 	int ntxbuf;       /* number of tx frames/buffers */
     86   1.8       gwr 	int nframes;      /* number of recv frames in use */
     87   1.8       gwr 	int nrxbuf;       /* number of recv buffs in use */
     88   1.8       gwr 
     89   1.1       gwr 	/*
     90   1.1       gwr 	 * pointers to the 3 major control structures
     91   1.1       gwr 	 */
     92   1.1       gwr 	volatile struct ie_sys_conf_ptr *scp;
     93   1.1       gwr 	volatile struct ie_int_sys_conf_ptr *iscp;
     94   1.1       gwr 	volatile struct ie_sys_ctl_block *scb;
     95   1.1       gwr 
     96   1.1       gwr 	/*
     97   1.1       gwr 	 * pointer and size of a block of KVA where the buffers
     98   1.1       gwr 	 * are to be allocated from
     99   1.1       gwr 	 */
    100  1.15   tsutsui 	uint8_t *buf_area;
    101   1.1       gwr 	int     buf_area_sz;
    102   1.1       gwr 
    103   1.1       gwr 	/*
    104   1.8       gwr 	 * Transmit commands, descriptors, and buffers
    105   1.4       gwr 	 */
    106   1.1       gwr 	volatile struct ie_xmit_cmd *xmit_cmds[NTXBUF];
    107   1.1       gwr 	volatile struct ie_xmit_buf *xmit_buffs[NTXBUF];
    108   1.8       gwr 	char *xmit_cbuffs[NTXBUF];
    109   1.4       gwr 	int xmit_busy;
    110   1.4       gwr 	int xmit_free;
    111   1.4       gwr 	int xchead, xctail;
    112   1.1       gwr 
    113   1.8       gwr 	/*
    114   1.8       gwr 	 * Receive frames, descriptors, and buffers
    115   1.8       gwr 	 */
    116   1.8       gwr 	volatile struct ie_recv_frame_desc *rframes[MXFRAMES];
    117   1.8       gwr 	volatile struct ie_recv_buf_desc *rbuffs[MXRXBUF];
    118   1.8       gwr 	char *cbuffs[MXRXBUF];
    119   1.8       gwr 	int     rfhead, rftail, rbhead, rbtail;
    120   1.8       gwr 
    121   1.8       gwr 	/* Multi-cast stuff */
    122   1.8       gwr 	int     mcast_count;
    123   1.1       gwr 	struct ie_en_addr mcast_addrs[MAXMCAST + 1];
    124   1.1       gwr };
    125   1.1       gwr 
    126   1.1       gwr 
    127  1.12       chs extern void    ie_attach(struct ie_softc *);
    128  1.12       chs extern int  ie_intr(void *);
    129