if_ievar.h revision 1.1 1 1.1 gwr /* $NetBSD: if_ievar.h,v 1.1 1994/12/12 18:59:11 gwr Exp $ */
2 1.1 gwr
3 1.1 gwr /*
4 1.1 gwr * Machine-dependent glue for the Intel Ethernet (ie) driver.
5 1.1 gwr */
6 1.1 gwr
7 1.1 gwr #define B_PER_F 3 /* number of buffers to allocate per frame */
8 1.1 gwr #define MXFRAMES 300 /* max number of frames to allow for receive */
9 1.1 gwr #define MXRXBUF (MXFRAMES*B_PER_F) /* max number of buffers to allocate */
10 1.1 gwr #define IE_RBUF_SIZE 256 /* size of each buffer, MUST BE POWER OF TWO */
11 1.1 gwr #define NTXBUF 2 /* number of transmit buffer/command pairs */
12 1.1 gwr #define IE_TBUF_SIZE 1512 /* length of transmit buffer */
13 1.1 gwr
14 1.1 gwr enum ie_hardware {
15 1.1 gwr IE_VME, /* multibus to VME ie card */
16 1.1 gwr IE_OBIO, /* on board */
17 1.1 gwr IE_VME3E, /* sun 3e VME card */
18 1.1 gwr IE_UNKNOWN
19 1.1 gwr };
20 1.1 gwr
21 1.1 gwr const char *ie_hardware_names[] = {
22 1.1 gwr "multibus/vme",
23 1.1 gwr "onboard",
24 1.1 gwr "3e/vme",
25 1.1 gwr "unknown"
26 1.1 gwr };
27 1.1 gwr
28 1.1 gwr /*
29 1.1 gwr * Ethernet status, per interface.
30 1.1 gwr *
31 1.1 gwr * hardware addresses/sizes to know (all KVA):
32 1.1 gwr * sc_iobase = base of chip's 24 bit address space
33 1.1 gwr * sc_maddr = base address of chip RAM as stored in ie_base of iscp
34 1.1 gwr * sc_msize = size of chip's RAM
35 1.1 gwr * sc_reg = address of card dependent registers
36 1.1 gwr *
37 1.1 gwr * the chip uses two types of pointers: 16 bit and 24 bit
38 1.1 gwr * 16 bit pointers are offsets from sc_maddr/ie_base
39 1.1 gwr * KVA(16 bit offset) = offset + sc_maddr
40 1.1 gwr * 24 bit pointers are offset from sc_iobase in KVA
41 1.1 gwr * KVA(24 bit address) = address + sc_iobase
42 1.1 gwr *
43 1.1 gwr * on the vme/multibus we have the page map to control where ram appears
44 1.1 gwr * in the address space. we choose to have RAM start at 0 in the
45 1.1 gwr * 24 bit address space. this means that sc_iobase == sc_maddr!
46 1.1 gwr * to get the phyiscal address of the board's RAM you must take the
47 1.1 gwr * top 12 bits of the physical address of the register address
48 1.1 gwr * and or in the 4 bits from the status word as bits 17-20 (remember that
49 1.1 gwr * the board ignores the chip's top 4 address lines).
50 1.1 gwr * For example:
51 1.1 gwr * if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000.
52 1.1 gwr * to get the 4 bits from the the status word just do status & IEVME_HADDR.
53 1.1 gwr * suppose the value is "4". Then just shift it left 16 bits to get
54 1.1 gwr * it into bits 17-20 (e.g. 0x40000). Then or it to get the
55 1.1 gwr * address of RAM (in our example: 0xffe40000). see the attach routine!
56 1.1 gwr *
57 1.1 gwr * XXX CONFIRM THE BELOW COMMENT
58 1.1 gwr * on the onboard ie interface the 24 bit address space is hardwired
59 1.1 gwr * to be 0xff000000 -> 0xffffffff of KVA. this means that sc_iobase
60 1.1 gwr * will be 0xff000000. sc_maddr will be where ever we allocate RAM
61 1.1 gwr * in KVA. note that since the SCP is at a fixed address it means
62 1.1 gwr * that we have to allocate a fixed KVA for the SCP.
63 1.1 gwr */
64 1.1 gwr struct ie_softc {
65 1.1 gwr struct device sc_dev; /* device structure */
66 1.1 gwr
67 1.1 gwr struct arpcom sc_arpcom;/* system arpcom structure */
68 1.1 gwr #define sc_if sc_arpcom.ac_if /* network-visible interface */
69 1.1 gwr #define sc_addr sc_arpcom.ac_enaddr /* hardware Ethernet address */
70 1.1 gwr
71 1.1 gwr caddr_t sc_iobase; /* KVA of base of 24bit addr space */
72 1.1 gwr caddr_t sc_maddr; /* KVA of base of chip's RAM */
73 1.1 gwr u_int sc_msize; /* how much RAM we have/use */
74 1.1 gwr caddr_t sc_reg; /* KVA of card's register */
75 1.1 gwr
76 1.1 gwr void (*reset_586)(); /* card dependent reset function */
77 1.1 gwr void (*chan_attn)(); /* card dependent attn function */
78 1.1 gwr void (*run_586)(); /* card dependent "go on-line" function */
79 1.1 gwr
80 1.1 gwr enum ie_hardware hard_type; /* card type */
81 1.1 gwr void (*memcopy) __P((const void *, void *, u_int));
82 1.1 gwr void (*memzero) __P((void *, u_int));
83 1.1 gwr
84 1.1 gwr int want_mcsetup; /* flag for multicast setup */
85 1.1 gwr int promisc; /* are we in promisc mode? */
86 1.1 gwr
87 1.1 gwr /*
88 1.1 gwr * pointers to the 3 major control structures
89 1.1 gwr */
90 1.1 gwr volatile struct ie_sys_conf_ptr *scp;
91 1.1 gwr volatile struct ie_int_sys_conf_ptr *iscp;
92 1.1 gwr volatile struct ie_sys_ctl_block *scb;
93 1.1 gwr
94 1.1 gwr /*
95 1.1 gwr * pointer and size of a block of KVA where the buffers
96 1.1 gwr * are to be allocated from
97 1.1 gwr */
98 1.1 gwr caddr_t buf_area;
99 1.1 gwr int buf_area_sz;
100 1.1 gwr
101 1.1 gwr /*
102 1.1 gwr * the actual buffers (recv and xmit)
103 1.1 gwr */
104 1.1 gwr volatile struct ie_recv_frame_desc *rframes[MXFRAMES];
105 1.1 gwr volatile struct ie_recv_buf_desc *rbuffs[MXRXBUF];
106 1.1 gwr volatile char *cbuffs[MXRXBUF];
107 1.1 gwr int rfhead, rftail, rbhead, rbtail;
108 1.1 gwr
109 1.1 gwr volatile struct ie_xmit_cmd *xmit_cmds[NTXBUF];
110 1.1 gwr volatile struct ie_xmit_buf *xmit_buffs[NTXBUF];
111 1.1 gwr int xmit_count;
112 1.1 gwr u_char *xmit_cbuffs[NTXBUF];
113 1.1 gwr
114 1.1 gwr struct ie_en_addr mcast_addrs[MAXMCAST + 1];
115 1.1 gwr int mcast_count;
116 1.1 gwr
117 1.1 gwr int nframes, nrxbuf;
118 1.1 gwr #ifdef IEDEBUG
119 1.1 gwr int sc_debug;
120 1.1 gwr #endif
121 1.1 gwr };
122 1.1 gwr
123 1.1 gwr
124 1.1 gwr extern int ie_md_match(struct device *, void *, void *args);
125 1.1 gwr extern void ie_md_attach(struct device *, struct device *, void *);
126 1.1 gwr extern int ie_intr(void *);
127