1 1.23 tsutsui /* $NetBSD: memerr.c,v 1.23 2024/12/20 23:52:00 tsutsui Exp $ */ 2 1.1 gwr 3 1.1 gwr /* 4 1.1 gwr * Copyright (c) 1992, 1993 5 1.1 gwr * The Regents of the University of California. All rights reserved. 6 1.1 gwr * 7 1.1 gwr * This software was developed by the Computer Systems Engineering group 8 1.1 gwr * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 1.1 gwr * contributed to Berkeley. 10 1.1 gwr * 11 1.1 gwr * All advertising materials mentioning features or use of this software 12 1.1 gwr * must display the following acknowledgement: 13 1.1 gwr * This product includes software developed by the University of 14 1.1 gwr * California, Lawrence Berkeley Laboratory. 15 1.1 gwr * 16 1.1 gwr * Redistribution and use in source and binary forms, with or without 17 1.1 gwr * modification, are permitted provided that the following conditions 18 1.1 gwr * are met: 19 1.1 gwr * 1. Redistributions of source code must retain the above copyright 20 1.1 gwr * notice, this list of conditions and the following disclaimer. 21 1.1 gwr * 2. Redistributions in binary form must reproduce the above copyright 22 1.1 gwr * notice, this list of conditions and the following disclaimer in the 23 1.1 gwr * documentation and/or other materials provided with the distribution. 24 1.16 agc * 3. Neither the name of the University nor the names of its contributors 25 1.1 gwr * may be used to endorse or promote products derived from this software 26 1.1 gwr * without specific prior written permission. 27 1.1 gwr * 28 1.1 gwr * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 1.1 gwr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 1.1 gwr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 1.1 gwr * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 1.1 gwr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 1.1 gwr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 1.1 gwr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 1.1 gwr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 1.1 gwr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 1.1 gwr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 1.1 gwr * SUCH DAMAGE. 39 1.1 gwr * 40 1.1 gwr * @(#)memreg.c 8.1 (Berkeley) 6/11/93 41 1.1 gwr */ 42 1.15 lukem 43 1.15 lukem #include <sys/cdefs.h> 44 1.23 tsutsui __KERNEL_RCSID(0, "$NetBSD: memerr.c,v 1.23 2024/12/20 23:52:00 tsutsui Exp $"); 45 1.1 gwr 46 1.1 gwr #include <sys/param.h> 47 1.1 gwr #include <sys/systm.h> 48 1.1 gwr #include <sys/device.h> 49 1.1 gwr 50 1.1 gwr #include <machine/autoconf.h> 51 1.1 gwr #include <machine/cpu.h> 52 1.7 gwr #include <machine/idprom.h> 53 1.1 gwr #include <machine/pte.h> 54 1.1 gwr 55 1.10 gwr #include <sun3/sun3/machdep.h> 56 1.1 gwr #include <sun3/dev/memerr.h> 57 1.1 gwr /* #include <sun3/dev/eccreg.h> - not yet */ 58 1.1 gwr 59 1.1 gwr #define ME_PRI 7 /* Interrupt level (NMI) */ 60 1.1 gwr 61 1.1 gwr enum memerr_type { ME_PAR = 0, ME_ECC = 1 }; 62 1.1 gwr 63 1.1 gwr struct memerr_softc { 64 1.21 tsutsui device_t sc_dev; 65 1.1 gwr struct memerr *sc_reg; 66 1.1 gwr enum memerr_type sc_type; 67 1.18 tsutsui const char *sc_typename; /* "Parity" or "ECC" */ 68 1.18 tsutsui const char *sc_csrbits; /* how to print csr bits */ 69 1.1 gwr /* XXX: counters? */ 70 1.1 gwr }; 71 1.1 gwr 72 1.21 tsutsui static int memerr_match(device_t, cfdata_t, void *); 73 1.21 tsutsui static void memerr_attach(device_t, device_t, void *); 74 1.17 chs static int memerr_interrupt(void *); 75 1.17 chs static void memerr_correctable(struct memerr_softc *); 76 1.1 gwr 77 1.21 tsutsui CFATTACH_DECL_NEW(memerr, sizeof(struct memerr_softc), 78 1.14 thorpej memerr_match, memerr_attach, NULL, NULL); 79 1.1 gwr 80 1.21 tsutsui static int memerr_attached; 81 1.11 chs 82 1.23 tsutsui static int 83 1.21 tsutsui memerr_match(device_t parent, cfdata_t cf, void *args) 84 1.1 gwr { 85 1.1 gwr struct confargs *ca = args; 86 1.1 gwr 87 1.11 chs /* This driver only supports one instance. */ 88 1.11 chs if (memerr_attached) 89 1.21 tsutsui return 0; 90 1.1 gwr 91 1.8 gwr /* Make sure there is something there... */ 92 1.5 gwr if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1) 93 1.21 tsutsui return 0; 94 1.1 gwr 95 1.5 gwr /* Default interrupt priority. */ 96 1.5 gwr if (ca->ca_intpri == -1) 97 1.5 gwr ca->ca_intpri = ME_PRI; 98 1.5 gwr 99 1.21 tsutsui return 1; 100 1.1 gwr } 101 1.1 gwr 102 1.23 tsutsui static void 103 1.21 tsutsui memerr_attach(device_t parent, device_t self, void *args) 104 1.1 gwr { 105 1.21 tsutsui struct memerr_softc *sc = device_private(self); 106 1.1 gwr struct confargs *ca = args; 107 1.1 gwr struct memerr *mer; 108 1.1 gwr 109 1.21 tsutsui sc->sc_dev = self; 110 1.21 tsutsui 111 1.1 gwr /* 112 1.1 gwr * Which type of memory subsystem do we have? 113 1.1 gwr */ 114 1.1 gwr switch (cpu_machine_id) { 115 1.19 thorpej case ID_SUN3_160: /* XXX: correct? */ 116 1.19 thorpej case ID_SUN3_260: 117 1.19 thorpej case ID_SUN3X_470: 118 1.1 gwr sc->sc_type = ME_ECC; 119 1.1 gwr sc->sc_typename = "ECC"; 120 1.1 gwr sc->sc_csrbits = ME_ECC_STR; 121 1.1 gwr break; 122 1.1 gwr 123 1.1 gwr default: 124 1.1 gwr sc->sc_type = ME_PAR; 125 1.1 gwr sc->sc_typename = "Parity"; 126 1.1 gwr sc->sc_csrbits = ME_PAR_STR; 127 1.1 gwr break; 128 1.1 gwr } 129 1.21 tsutsui aprint_normal(": (%s memory)\n", sc->sc_typename); 130 1.1 gwr 131 1.10 gwr mer = bus_mapin(ca->ca_bustype, ca->ca_paddr, sizeof(*mer)); 132 1.5 gwr if (mer == NULL) 133 1.21 tsutsui panic("%s: can not map register", device_xname(self)); 134 1.5 gwr sc->sc_reg = mer; 135 1.1 gwr 136 1.1 gwr /* Install interrupt handler. */ 137 1.11 chs isr_add_autovect(memerr_interrupt, sc, ca->ca_intpri); 138 1.1 gwr 139 1.1 gwr /* Enable error interrupt (and checking). */ 140 1.1 gwr if (sc->sc_type == ME_PAR) 141 1.1 gwr mer->me_csr = ME_CSR_IENA | ME_PAR_CHECK; 142 1.1 gwr else { 143 1.1 gwr /* 144 1.1 gwr * XXX: Some day, figure out how to decode 145 1.1 gwr * correctable errors and set ME_ECC_CE_ENA 146 1.1 gwr * here so we can log them... 147 1.1 gwr */ 148 1.2 gwr mer->me_csr = ME_CSR_IENA; /* | ME_ECC_CE_ENA */ 149 1.1 gwr } 150 1.11 chs memerr_attached = 1; 151 1.1 gwr } 152 1.1 gwr 153 1.1 gwr /***************************************************************** 154 1.1 gwr * Functions for ECC memory 155 1.1 gwr *****************************************************************/ 156 1.1 gwr 157 1.23 tsutsui static int 158 1.17 chs memerr_interrupt(void *arg) 159 1.1 gwr { 160 1.1 gwr struct memerr_softc *sc = arg; 161 1.1 gwr volatile struct memerr *me = sc->sc_reg; 162 1.21 tsutsui uint8_t csr, ctx; 163 1.1 gwr u_int pa, va; 164 1.1 gwr int pte; 165 1.21 tsutsui uint8_t bits[64]; 166 1.1 gwr 167 1.1 gwr csr = me->me_csr; 168 1.1 gwr if ((csr & ME_CSR_IPEND) == 0) 169 1.21 tsutsui return 0; 170 1.1 gwr 171 1.1 gwr va = me->me_vaddr; 172 1.1 gwr ctx = (va >> 28) & 0xF; 173 1.1 gwr va &= 0x0FFFffff; 174 1.1 gwr pte = get_pte(va); 175 1.1 gwr pa = PG_PA(pte); 176 1.1 gwr 177 1.4 christos printf("\nMemory error on %s cycle!\n", 178 1.21 tsutsui (ctx & 8) ? "DVMA" : "CPU"); 179 1.4 christos printf(" ctx=%d, vaddr=0x%x, paddr=0x%x\n", 180 1.21 tsutsui (ctx & 7), va, pa); 181 1.22 christos snprintb(bits, sizeof(bits), sc->sc_csrbits, csr); 182 1.22 christos printf(" csr=%s\n", bits); 183 1.1 gwr 184 1.2 gwr /* 185 1.2 gwr * If we have parity-checked memory, there is 186 1.2 gwr * not much to be done. Any error is fatal. 187 1.2 gwr */ 188 1.1 gwr if (sc->sc_type == ME_PAR) { 189 1.2 gwr if (csr & ME_PAR_EMASK) { 190 1.2 gwr /* Parity errors are fatal. */ 191 1.2 gwr goto die; 192 1.2 gwr } 193 1.2 gwr /* The IPEND bit was set, but no error bits. */ 194 1.2 gwr goto noerror; 195 1.1 gwr } 196 1.1 gwr 197 1.1 gwr /* 198 1.1 gwr * We have ECC memory. More complicated... 199 1.1 gwr */ 200 1.1 gwr if (csr & (ME_ECC_WBTMO | ME_ECC_WBERR)) { 201 1.4 christos printf(" write-back failed, pte=0x%x\n", pte); 202 1.1 gwr goto die; 203 1.1 gwr } 204 1.1 gwr if (csr & ME_ECC_UE) { 205 1.4 christos printf(" uncorrectable ECC error\n"); 206 1.1 gwr goto die; 207 1.1 gwr } 208 1.2 gwr if (csr & ME_ECC_CE) { 209 1.2 gwr /* Just log this and continue. */ 210 1.1 gwr memerr_correctable(sc); 211 1.2 gwr goto recover; 212 1.2 gwr } 213 1.2 gwr /* The IPEND bit was set, but no error bits. */ 214 1.2 gwr goto noerror; 215 1.1 gwr 216 1.1 gwr die: 217 1.1 gwr panic("all bets are off..."); 218 1.1 gwr 219 1.1 gwr noerror: 220 1.4 christos printf("memerr: no error bits set?\n"); 221 1.1 gwr 222 1.1 gwr recover: 223 1.1 gwr /* Clear the error by writing the address register. */ 224 1.1 gwr me->me_vaddr = 0; 225 1.21 tsutsui return 1; 226 1.1 gwr } 227 1.1 gwr 228 1.1 gwr /* 229 1.1 gwr * Announce (and log) a correctable ECC error. 230 1.1 gwr * Need to look at the ECC syndrome register on 231 1.1 gwr * the memory board that caused the error... 232 1.1 gwr */ 233 1.23 tsutsui void 234 1.17 chs memerr_correctable(struct memerr_softc *sc) 235 1.1 gwr { 236 1.21 tsutsui 237 1.1 gwr /* XXX: Not yet... */ 238 1.1 gwr } 239