memerr.c revision 1.14 1 1.14 thorpej /* $NetBSD: memerr.c,v 1.14 2002/10/02 16:02:26 thorpej Exp $ */
2 1.1 gwr
3 1.1 gwr /*
4 1.1 gwr * Copyright (c) 1992, 1993
5 1.1 gwr * The Regents of the University of California. All rights reserved.
6 1.1 gwr *
7 1.1 gwr * This software was developed by the Computer Systems Engineering group
8 1.1 gwr * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 1.1 gwr * contributed to Berkeley.
10 1.1 gwr *
11 1.1 gwr * All advertising materials mentioning features or use of this software
12 1.1 gwr * must display the following acknowledgement:
13 1.1 gwr * This product includes software developed by the University of
14 1.1 gwr * California, Lawrence Berkeley Laboratory.
15 1.1 gwr *
16 1.1 gwr * Redistribution and use in source and binary forms, with or without
17 1.1 gwr * modification, are permitted provided that the following conditions
18 1.1 gwr * are met:
19 1.1 gwr * 1. Redistributions of source code must retain the above copyright
20 1.1 gwr * notice, this list of conditions and the following disclaimer.
21 1.1 gwr * 2. Redistributions in binary form must reproduce the above copyright
22 1.1 gwr * notice, this list of conditions and the following disclaimer in the
23 1.1 gwr * documentation and/or other materials provided with the distribution.
24 1.1 gwr * 3. All advertising materials mentioning features or use of this software
25 1.1 gwr * must display the following acknowledgement:
26 1.1 gwr * This product includes software developed by the University of
27 1.1 gwr * California, Berkeley and its contributors.
28 1.1 gwr * 4. Neither the name of the University nor the names of its contributors
29 1.1 gwr * may be used to endorse or promote products derived from this software
30 1.1 gwr * without specific prior written permission.
31 1.1 gwr *
32 1.1 gwr * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33 1.1 gwr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 1.1 gwr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 1.1 gwr * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36 1.1 gwr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 1.1 gwr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 1.1 gwr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 1.1 gwr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40 1.1 gwr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41 1.1 gwr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 1.1 gwr * SUCH DAMAGE.
43 1.1 gwr *
44 1.1 gwr * @(#)memreg.c 8.1 (Berkeley) 6/11/93
45 1.1 gwr */
46 1.1 gwr
47 1.1 gwr #include <sys/param.h>
48 1.1 gwr #include <sys/systm.h>
49 1.1 gwr #include <sys/device.h>
50 1.1 gwr
51 1.1 gwr #include <machine/autoconf.h>
52 1.1 gwr #include <machine/cpu.h>
53 1.7 gwr #include <machine/idprom.h>
54 1.1 gwr #include <machine/pte.h>
55 1.1 gwr
56 1.10 gwr #include <sun3/sun3/machdep.h>
57 1.1 gwr #include <sun3/dev/memerr.h>
58 1.1 gwr /* #include <sun3/dev/eccreg.h> - not yet */
59 1.1 gwr
60 1.1 gwr #define ME_PRI 7 /* Interrupt level (NMI) */
61 1.1 gwr
62 1.1 gwr extern unsigned char cpu_machine_id;
63 1.1 gwr
64 1.1 gwr enum memerr_type { ME_PAR = 0, ME_ECC = 1 };
65 1.1 gwr
66 1.1 gwr struct memerr_softc {
67 1.1 gwr struct device sc_dev;
68 1.1 gwr struct memerr *sc_reg;
69 1.1 gwr enum memerr_type sc_type;
70 1.1 gwr char *sc_typename; /* "Parity" or "ECC" */
71 1.1 gwr char *sc_csrbits; /* how to print csr bits */
72 1.1 gwr /* XXX: counters? */
73 1.1 gwr };
74 1.1 gwr
75 1.7 gwr static int memerr_match __P((struct device *, struct cfdata *, void *));
76 1.1 gwr static void memerr_attach __P((struct device *, struct device *, void *));
77 1.1 gwr static int memerr_interrupt __P((void *));
78 1.1 gwr static void memerr_correctable __P((struct memerr_softc *));
79 1.1 gwr
80 1.13 thorpej CFATTACH_DECL(memerr, sizeof(struct memerr_softc),
81 1.14 thorpej memerr_match, memerr_attach, NULL, NULL);
82 1.1 gwr
83 1.11 chs int memerr_attached;
84 1.11 chs
85 1.1 gwr static int
86 1.7 gwr memerr_match(parent, cf, args)
87 1.11 chs struct device *parent;
88 1.11 chs struct cfdata *cf;
89 1.11 chs void *args;
90 1.1 gwr {
91 1.1 gwr struct confargs *ca = args;
92 1.1 gwr
93 1.11 chs /* This driver only supports one instance. */
94 1.11 chs if (memerr_attached)
95 1.1 gwr return (0);
96 1.1 gwr
97 1.8 gwr /* Make sure there is something there... */
98 1.5 gwr if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1)
99 1.1 gwr return (0);
100 1.1 gwr
101 1.5 gwr /* Default interrupt priority. */
102 1.5 gwr if (ca->ca_intpri == -1)
103 1.5 gwr ca->ca_intpri = ME_PRI;
104 1.5 gwr
105 1.5 gwr return (1);
106 1.1 gwr }
107 1.1 gwr
108 1.1 gwr static void
109 1.1 gwr memerr_attach(parent, self, args)
110 1.1 gwr struct device *parent;
111 1.1 gwr struct device *self;
112 1.1 gwr void *args;
113 1.1 gwr {
114 1.1 gwr struct memerr_softc *sc = (void *)self;
115 1.1 gwr struct confargs *ca = args;
116 1.1 gwr struct memerr *mer;
117 1.1 gwr
118 1.1 gwr /*
119 1.1 gwr * Which type of memory subsystem do we have?
120 1.1 gwr */
121 1.1 gwr switch (cpu_machine_id) {
122 1.1 gwr case SUN3_MACH_160: /* XXX: correct? */
123 1.1 gwr case SUN3_MACH_260:
124 1.10 gwr case SUN3X_MACH_470:
125 1.1 gwr sc->sc_type = ME_ECC;
126 1.1 gwr sc->sc_typename = "ECC";
127 1.1 gwr sc->sc_csrbits = ME_ECC_STR;
128 1.1 gwr break;
129 1.1 gwr
130 1.1 gwr default:
131 1.1 gwr sc->sc_type = ME_PAR;
132 1.1 gwr sc->sc_typename = "Parity";
133 1.1 gwr sc->sc_csrbits = ME_PAR_STR;
134 1.1 gwr break;
135 1.1 gwr }
136 1.5 gwr printf(": (%s memory)\n", sc->sc_typename);
137 1.1 gwr
138 1.10 gwr mer = bus_mapin(ca->ca_bustype, ca->ca_paddr, sizeof(*mer));
139 1.5 gwr if (mer == NULL)
140 1.5 gwr panic("memerr: can not map register");
141 1.5 gwr sc->sc_reg = mer;
142 1.1 gwr
143 1.1 gwr /* Install interrupt handler. */
144 1.11 chs isr_add_autovect(memerr_interrupt, sc, ca->ca_intpri);
145 1.1 gwr
146 1.1 gwr /* Enable error interrupt (and checking). */
147 1.1 gwr if (sc->sc_type == ME_PAR)
148 1.1 gwr mer->me_csr = ME_CSR_IENA | ME_PAR_CHECK;
149 1.1 gwr else {
150 1.1 gwr /*
151 1.1 gwr * XXX: Some day, figure out how to decode
152 1.1 gwr * correctable errors and set ME_ECC_CE_ENA
153 1.1 gwr * here so we can log them...
154 1.1 gwr */
155 1.2 gwr mer->me_csr = ME_CSR_IENA; /* | ME_ECC_CE_ENA */
156 1.1 gwr }
157 1.11 chs memerr_attached = 1;
158 1.1 gwr }
159 1.1 gwr
160 1.1 gwr /*****************************************************************
161 1.1 gwr * Functions for ECC memory
162 1.1 gwr *****************************************************************/
163 1.1 gwr
164 1.1 gwr static int
165 1.1 gwr memerr_interrupt(arg)
166 1.1 gwr void *arg;
167 1.1 gwr {
168 1.1 gwr struct memerr_softc *sc = arg;
169 1.1 gwr volatile struct memerr *me = sc->sc_reg;
170 1.7 gwr u_char csr, ctx;
171 1.1 gwr u_int pa, va;
172 1.1 gwr int pte;
173 1.6 thorpej char bits[64];
174 1.1 gwr
175 1.1 gwr csr = me->me_csr;
176 1.1 gwr if ((csr & ME_CSR_IPEND) == 0)
177 1.1 gwr return (0);
178 1.1 gwr
179 1.1 gwr va = me->me_vaddr;
180 1.1 gwr ctx = (va >> 28) & 0xF;
181 1.1 gwr va &= 0x0FFFffff;
182 1.1 gwr pte = get_pte(va);
183 1.1 gwr pa = PG_PA(pte);
184 1.1 gwr
185 1.4 christos printf("\nMemory error on %s cycle!\n",
186 1.1 gwr (ctx & 8) ? "DVMA" : "CPU");
187 1.4 christos printf(" ctx=%d, vaddr=0x%x, paddr=0x%x\n",
188 1.1 gwr (ctx & 7), va, pa);
189 1.6 thorpej printf(" csr=%s\n", bitmask_snprintf(csr, sc->sc_csrbits,
190 1.6 thorpej bits, sizeof(bits)));
191 1.1 gwr
192 1.2 gwr /*
193 1.2 gwr * If we have parity-checked memory, there is
194 1.2 gwr * not much to be done. Any error is fatal.
195 1.2 gwr */
196 1.1 gwr if (sc->sc_type == ME_PAR) {
197 1.2 gwr if (csr & ME_PAR_EMASK) {
198 1.2 gwr /* Parity errors are fatal. */
199 1.2 gwr goto die;
200 1.2 gwr }
201 1.2 gwr /* The IPEND bit was set, but no error bits. */
202 1.2 gwr goto noerror;
203 1.1 gwr }
204 1.1 gwr
205 1.1 gwr /*
206 1.1 gwr * We have ECC memory. More complicated...
207 1.1 gwr */
208 1.1 gwr if (csr & (ME_ECC_WBTMO | ME_ECC_WBERR)) {
209 1.4 christos printf(" write-back failed, pte=0x%x\n", pte);
210 1.1 gwr goto die;
211 1.1 gwr }
212 1.1 gwr if (csr & ME_ECC_UE) {
213 1.4 christos printf(" uncorrectable ECC error\n");
214 1.1 gwr goto die;
215 1.1 gwr }
216 1.2 gwr if (csr & ME_ECC_CE) {
217 1.2 gwr /* Just log this and continue. */
218 1.1 gwr memerr_correctable(sc);
219 1.2 gwr goto recover;
220 1.2 gwr }
221 1.2 gwr /* The IPEND bit was set, but no error bits. */
222 1.2 gwr goto noerror;
223 1.1 gwr
224 1.1 gwr die:
225 1.1 gwr panic("all bets are off...");
226 1.1 gwr
227 1.1 gwr noerror:
228 1.4 christos printf("memerr: no error bits set?\n");
229 1.1 gwr
230 1.1 gwr recover:
231 1.1 gwr /* Clear the error by writing the address register. */
232 1.1 gwr me->me_vaddr = 0;
233 1.1 gwr return (1);
234 1.1 gwr }
235 1.1 gwr
236 1.1 gwr /*
237 1.1 gwr * Announce (and log) a correctable ECC error.
238 1.1 gwr * Need to look at the ECC syndrome register on
239 1.1 gwr * the memory board that caused the error...
240 1.1 gwr */
241 1.1 gwr void
242 1.1 gwr memerr_correctable(sc)
243 1.1 gwr struct memerr_softc *sc;
244 1.1 gwr {
245 1.1 gwr /* XXX: Not yet... */
246 1.1 gwr }
247