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sereg.h revision 1.1
      1  1.1  gwr /*	$NetBSD: sereg.h,v 1.1 1997/10/17 03:39:48 gwr Exp $	*/
      2  1.1  gwr 
      3  1.1  gwr /*-
      4  1.1  gwr  * Copyright (c) 1997 The NetBSD Foundation, Inc.
      5  1.1  gwr  * All rights reserved.
      6  1.1  gwr  *
      7  1.1  gwr  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1  gwr  * by Gordon W. Ross.
      9  1.1  gwr  *
     10  1.1  gwr  * Redistribution and use in source and binary forms, with or without
     11  1.1  gwr  * modification, are permitted provided that the following conditions
     12  1.1  gwr  * are met:
     13  1.1  gwr  * 1. Redistributions of source code must retain the above copyright
     14  1.1  gwr  *    notice, this list of conditions and the following disclaimer.
     15  1.1  gwr  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1  gwr  *    notice, this list of conditions and the following disclaimer in the
     17  1.1  gwr  *    documentation and/or other materials provided with the distribution.
     18  1.1  gwr  * 3. All advertising materials mentioning features or use of this software
     19  1.1  gwr  *    must display the following acknowledgement:
     20  1.1  gwr  *        This product includes software developed by the NetBSD
     21  1.1  gwr  *        Foundation, Inc. and its contributors.
     22  1.1  gwr  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.1  gwr  *    contributors may be used to endorse or promote products derived
     24  1.1  gwr  *    from this software without specific prior written permission.
     25  1.1  gwr  *
     26  1.1  gwr  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.1  gwr  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.1  gwr  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.1  gwr  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.1  gwr  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.1  gwr  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.1  gwr  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.1  gwr  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.1  gwr  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.1  gwr  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.1  gwr  * POSSIBILITY OF SUCH DAMAGE.
     37  1.1  gwr  */
     38  1.1  gwr 
     39  1.1  gwr /*
     40  1.1  gwr  * Sun3/E SCSI/Ethernet board.  This is a VME board with some memory,
     41  1.1  gwr  * an Intel Ether, and an NCR5380 SCSI with a cheap DMA engine.
     42  1.1  gwr  */
     43  1.1  gwr 
     44  1.1  gwr /*****************************************************************
     45  1.1  gwr  * Register definitions for the SCSI portion.
     46  1.1  gwr  */
     47  1.1  gwr struct se_regs {
     48  1.1  gwr 	u_char			ncrregs[8];
     49  1.1  gwr 	/* +0x08 */
     50  1.1  gwr 	u_short			unused1;
     51  1.1  gwr 	u_short			dma_addr;	/* DMA offset register	*/
     52  1.1  gwr 	u_short			unused2;
     53  1.1  gwr 	u_short			dma_cntr;	/* DMA count down register */
     54  1.1  gwr 	/* +0x10 */
     55  1.1  gwr 	u_short			unused3[4];
     56  1.1  gwr 	/* +0x18 */
     57  1.1  gwr 	u_short			unused7;
     58  1.1  gwr 	u_short			se_csr;		/* control/status register */
     59  1.1  gwr 	u_char			unused9[3];
     60  1.1  gwr 	u_char			se_ivec;	/* interrupt vector	*/
     61  1.1  gwr 	/* +0x20 */
     62  1.1  gwr };
     63  1.1  gwr 
     64  1.1  gwr /*
     65  1.1  gwr  * SCSI Control and Status Register.
     66  1.1  gwr  * Note:
     67  1.1  gwr  *	(ro) 	indicates bit is read only.
     68  1.1  gwr  *	(rw)	indicates bit is read or write.
     69  1.1  gwr  */
     70  1.1  gwr #define SE_CSR_SBC_IP		0x0200	/* (ro) sbc interrupt pending */
     71  1.1  gwr #define SE_CSR_SEND 		0x0008	/* (rw) dma dir, 1=to device */
     72  1.1  gwr #define SE_CSR_INTR_EN		0x0004	/* (rw) interrupts enable */
     73  1.1  gwr #define	SE_CSR_VCC  		0x0002	/* (ro) power signal to the chip */
     74  1.1  gwr #define SE_CSR_SCSI_RES		0x0001	/* (rw) reset sbc and udc, 0=reset */
     75  1.1  gwr 
     76  1.1  gwr 
     77  1.1  gwr /*****************************************************************
     78  1.1  gwr  * Register definitions for the SCSI portion.
     79  1.1  gwr  */
     80  1.1  gwr struct ie_regs {
     81  1.1  gwr 	u_short			ie_pad0;
     82  1.1  gwr 	u_short			ie_csr;
     83  1.1  gwr 	u_short			ie_pad1[6];
     84  1.1  gwr 	u_char			ie_pad2[3];
     85  1.1  gwr 	u_char			ie_ivec;			/* interrupt vector */
     86  1.1  gwr 	u_short			ie_pad3[128-10];
     87  1.1  gwr };
     88  1.1  gwr 
     89  1.1  gwr /*
     90  1.1  gwr  * Ether Control and Status Register.
     91  1.1  gwr  */
     92  1.1  gwr #define IE_CSR_RESET		0x8000	/* board reset */
     93  1.1  gwr #define IE_CSR_NOLOOP		0x4000	/* loopback disable */
     94  1.1  gwr #define IE_CSR_ATTEN		0x2000	/* channel attention */
     95  1.1  gwr #define IE_CSR_IENAB		0x1000	/* interrupt enable */
     96  1.1  gwr #define IE_CSR_IPEND		0x0100	/* interrupt pending */
     97  1.1  gwr 
     98  1.1  gwr 
     99  1.1  gwr /*****************************************************************
    100  1.1  gwr  * Register definitions for the entire SCSI/Ethernet board.
    101  1.1  gwr  */
    102  1.1  gwr 
    103  1.1  gwr #define SE_NCRBUFSIZE	 0x10000	/* 64k */
    104  1.1  gwr #define SE_IEBUFSIZE	(0x10000 - 0x120)
    105  1.1  gwr struct sebuf_regs {
    106  1.1  gwr 	char	se_scsi_buf[SE_NCRBUFSIZE];
    107  1.1  gwr 	struct se_regs se_scsi_regs;
    108  1.1  gwr 	char	se_eth_buf[SE_IEBUFSIZE];
    109  1.1  gwr 	struct ie_regs se_eth_regs;
    110  1.1  gwr };	/* 128KB total */
    111